Update IDF to version 3cad00f (#310)

platform.txt

@@ -21,7 +21,7 @@ compiler.warning_flags.all=-Wall -Werror=all -Wextra
 
 compiler.path={runtime.tools.xtensa-esp32-elf-gcc.path}/bin/
 compiler.sdk.path={runtime.platform.path}/tools/sdk
-compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bluedroid" "-I{compiler.sdk.path}/include/app_update" "-I{compiler.sdk.path}/include/bootloader_support" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/ethernet" "-I{compiler.sdk.path}/include/fatfs" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/jsmn" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/mdns" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/mbedtls_port" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/sdmmc" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/ulp" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/coap" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip"
+compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DHAVE_CONFIG_H "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/bluedroid" "-I{compiler.sdk.path}/include/app_update" "-I{compiler.sdk.path}/include/bootloader_support" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/ethernet" "-I{compiler.sdk.path}/include/fatfs" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/jsmn" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/mdns" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/mbedtls_port" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/soc" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/sdmmc" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/ulp" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/coap" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/lwip"
 
 compiler.c.cmd=xtensa-esp32-elf-gcc
 compiler.c.flags=-std=gnu99 -Os -g3 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wpointer-arith {compiler.warning_flags} -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -Wno-old-style-declaration -MMD -c
@@ -34,7 +34,7 @@ compiler.S.flags=-c -g3 -x assembler-with-cpp -MMD -mlongcalls
 
 compiler.c.elf.cmd=xtensa-esp32-elf-gcc
 compiler.c.elf.flags=-nostdlib "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--undefined=uxTopUsedPriority
-compiler.c.elf.libs=-lgcc -lstdc++ -lapp_update -lbootloader_support -lbt -lbtdm_app -lc -lc_nano -lcoap -lcoexist -lcore -lcxx -ldriver -lesp32 -lethernet -lexpat -lfatfs -lfreertos -lhal -ljsmn -ljson -llog -llwip -lm -lmbedtls -lmdns -lmicro-ecc -lnet80211 -lnewlib -lnghttp -lnvs_flash -lopenssl -lphy -lpp -lrtc -lrtc_clk -lrtc_pm -lsdmmc -lsmartconfig -lspi_flash -ltcpip_adapter -lulp -lvfs -lwpa -lwpa2 -lwpa_supplicant -lwps -lxtensa-debug-module 
+compiler.c.elf.libs=-lgcc -lstdc++ -lapp_update -lbootloader_support -lbt -lbtdm_app -lc -lc_nano -lcoap -lcoexist -lcore -lcxx -ldriver -lesp32 -lethernet -lexpat -lfatfs -lfreertos -lhal -ljsmn -ljson -llog -llwip -lm -lmbedtls -lmdns -lmicro-ecc -lnet80211 -lnewlib -lnghttp -lnvs_flash -lopenssl -lphy -lpp -lrtc -lsdmmc -lsmartconfig -lsoc -lspi_flash -ltcpip_adapter -lulp -lvfs -lwpa -lwpa2 -lwpa_supplicant -lwps -lxtensa-debug-module 
 
 compiler.as.cmd=xtensa-esp32-elf-as
 

tools/platformio-build.py

@@ -67,6 +67,7 @@ env.Prepend(
         join(FRAMEWORK_DIR, "tools", "sdk", "include", "newlib"),
         join(FRAMEWORK_DIR, "tools", "sdk", "include", "nvs_flash"),
         join(FRAMEWORK_DIR, "tools", "sdk", "include", "openssl"),
+        join(FRAMEWORK_DIR, "tools", "sdk", "include", "soc"),
         join(FRAMEWORK_DIR, "tools", "sdk", "include", "spi_flash"),
         join(FRAMEWORK_DIR, "tools", "sdk", "include", "sdmmc"),
         join(FRAMEWORK_DIR, "tools", "sdk", "include", "tcpip_adapter"),
@@ -89,7 +90,7 @@ env.Prepend(
     ],
 
     LIBS=[
-        "gcc", "stdc++", "app_update", "bootloader_support", "bt", "btdm_app", "c", "c_nano", "coap", "coexist", "core", "cxx", "driver", "esp32", "ethernet", "expat", "fatfs", "freertos", "hal", "jsmn", "json", "log", "lwip", "m", "mbedtls", "mdns", "micro-ecc", "net80211", "newlib", "nghttp", "nvs_flash", "openssl", "phy", "pp", "rtc", "rtc_clk", "rtc_pm", "sdmmc", "smartconfig", "spi_flash", "tcpip_adapter", "ulp", "vfs", "wpa", "wpa2", "wpa_supplicant", "wps", "xtensa-debug-module"
+        "gcc", "stdc++", "app_update", "bootloader_support", "bt", "btdm_app", "c", "c_nano", "coap", "coexist", "core", "cxx", "driver", "esp32", "ethernet", "expat", "fatfs", "freertos", "hal", "jsmn", "json", "log", "lwip", "m", "mbedtls", "mdns", "micro-ecc", "net80211", "newlib", "nghttp", "nvs_flash", "openssl", "phy", "pp", "rtc", "sdmmc", "smartconfig", "soc", "spi_flash", "tcpip_adapter", "ulp", "vfs", "wpa", "wpa2", "wpa_supplicant", "wps", "xtensa-debug-module"
     ],
 
     UPLOADERFLAGS=[

tools/sdk/include/bluedroid/alarm.h

@@ -35,7 +35,10 @@ typedef struct alarm_t {
     void *cb_data;
 } osi_alarm_t;
 
+int osi_alarm_create_mux(void);
+int osi_alarm_delete_mux(void);
 void osi_alarm_init(void);
+void osi_alarm_deinit(void);
 
 // Creates a new alarm object. The returned object must be freed by calling
 // |alarm_free|. Returns NULL on failure.

tools/sdk/include/bluedroid/bta_api.h

@@ -1003,6 +1003,8 @@ typedef struct {
     tBTM_BLE_EVT_TYPE   ble_evt_type;
     tBT_DEVICE_TYPE     device_type;
     UINT8               flag;
+    UINT8               adv_data_len;
+    UINT8               scan_rsp_len;
 #endif
 
 } tBTA_DM_INQ_RES;

tools/sdk/include/bluedroid/btm_api.h

@@ -611,6 +611,8 @@ typedef struct {
     UINT8       ble_addr_type;
     tBTM_BLE_EVT_TYPE       ble_evt_type;
     UINT8                   flag;
+    UINT8       adv_data_len;
+    UINT8       scan_rsp_len;
 #endif
 } tBTM_INQ_RESULTS;
 

tools/sdk/include/bluedroid/esp_gap_ble_api.h

@@ -273,6 +273,8 @@ typedef union {
         uint8_t  ble_adv[ESP_BLE_ADV_DATA_LEN_MAX + ESP_BLE_SCAN_RSP_DATA_LEN_MAX];     /*!< Received EIR */
         int flag;                                   /*!< Advertising data flag bit */
         int num_resps;                              /*!< Scan result number */
+        uint8_t adv_data_len;                       /*!< Adv data length */
+        uint8_t scan_rsp_len;                       /*!< Scan response length */
     } scan_rst;                                     /*!< Event parameter of ESP_GAP_BLE_SCAN_RESULT_EVT */
     /**
      * @brief ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT

tools/sdk/include/bluedroid/thread.h

@@ -44,24 +44,24 @@ enum {
 };
 
 #define HCI_HOST_TASK_STACK_SIZE        (2048 + BT_TASK_EXTRA_STACK_SIZE)
-#define HCI_HOST_TASK_PRIO              (configMAX_PRIORITIES - 2)
+#define HCI_HOST_TASK_PRIO              (configMAX_PRIORITIES - 3)
 #define HCI_HOST_TASK_NAME              "hciHostT"
 #define HCI_HOST_QUEUE_NUM              40
 
 #define HCI_H4_TASK_STACK_SIZE          (2048 + BT_TASK_EXTRA_STACK_SIZE)
-#define HCI_H4_TASK_PRIO                (configMAX_PRIORITIES - 3)
+#define HCI_H4_TASK_PRIO                (configMAX_PRIORITIES - 4)
 #define HCI_H4_TASK_NAME                "hciH4T"
 #define HCI_H4_QUEUE_NUM                60
 
 #define BTU_TASK_STACK_SIZE             (3584 + BT_TASK_EXTRA_STACK_SIZE)
-#define BTU_TASK_PRIO                   (configMAX_PRIORITIES - 4)
+#define BTU_TASK_PRIO                   (configMAX_PRIORITIES - 5)
 #define BTU_TASK_NAME                   "btuT"
 #define BTU_QUEUE_NUM                   50
 
 #define BTC_TASK_STACK_SIZE             (CONFIG_BTC_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE)	//by menuconfig
 #define BTC_TASK_NAME                   "btcT"
-#define BTC_TASK_PRIO                   (configMAX_PRIORITIES - 5)
-#define BTC_TASK_QUEUE_NUM              20
+#define BTC_TASK_PRIO                   (configMAX_PRIORITIES - 6)
+#define BTC_TASK_QUEUE_NUM              60
 
 void btu_task_post(uint32_t sig);
 void hci_host_task_post(void);

tools/sdk/include/bt/bt.h

@@ -18,11 +18,44 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include "esp_err.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Controller config options, depend on config mask.
+ *        Config mask indicate which functions enabled, this means 
+ *        some options or parameters of some functions enabled by config mask.
+ */
+typedef struct {
+    uint8_t hci_uart_no;            /*!< If use UART1/2 as HCI IO interface, indicate UART number */
+    uint32_t hci_uart_baudrate;     /*!< If use UART1/2 as HCI IO interface, indicate UART baudrate */
+} esp_bt_controller_config_t;
+
+#ifdef CONFIG_BT_ENABLED
+
+#ifdef CONFIG_BT_HCI_UART_NO
+#define BT_HCI_UART_NO_DEFAULT CONFIG_BT_HCI_UART_NO
+#else
+#define BT_HCI_UART_NO_DEFAULT 1
+#endif /* BT_HCI_UART_NO_DEFAULT */
+
+#ifdef CONFIG_BT_HCI_UART_BAUDRATE
+#define BT_HCI_UART_BAUDRATE_DEFAULT CONFIG_BT_HCI_UART_BAUDRATE
+#else
+#define BT_HCI_UART_BAUDRATE_DEFAULT 921600
+#endif /* BT_HCI_UART_BAUDRATE_DEFAULT */
+
+#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() { \
+    .hci_uart_no = BT_HCI_UART_NO_DEFAULT,\
+    .hci_uart_baudrate = BT_HCI_UART_BAUDRATE_DEFAULT,\
+};
+#else
+#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h");
+#endif
+
 /**
  * @brief Bluetooth mode for controller enable/disable
  */
@@ -45,10 +78,11 @@ typedef enum {
 
 /**
  * @brief  Initialize BT controller to allocate task and other resource.
- *
+ * @param  cfg: Initial configuration of BT controller.
  * This function should be called only once, before any other BT functions are called.
+ * @return       ESP_OK - success, other - failed
  */
-void esp_bt_controller_init(void);
+esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg);
 
 /**
  * @brief  De-initialize BT controller to free resource and delete task.

tools/sdk/include/config/sdkconfig.h

@@ -46,6 +46,7 @@
 #define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1
 #define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1
 #define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1
+#define CONFIG_BTDM_CONTROLLER_RUN_CPU 0
 #define CONFIG_FATFS_CODEPAGE_850 1
 #define CONFIG_TASK_WDT 1
 #define CONFIG_MAIN_TASK_STACK_SIZE 4096
@@ -74,7 +75,7 @@
 #define CONFIG_FLASHMODE_QIO 1
 #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
 #define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048
-#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 0
+#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 1000
 #define CONFIG_PHY_DATA_OFFSET 0xf000
 #define CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET 0x10000
 #define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
@@ -110,6 +111,7 @@
 #define CONFIG_ESPTOOLPY_BAUD_921600B 1
 #define CONFIG_APP_OFFSET 0x10000
 #define CONFIG_MEMMAP_SMP 1
+#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
 #define CONFIG_LWIP_SO_RCVBUF 1
 #define CONFIG_MBEDTLS_HARDWARE_MPI 1
 #define CONFIG_MONITOR_BAUD_OTHER_VAL 115200

tools/sdk/include/driver/driver/rmt.h

@@ -564,7 +564,7 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu
  *     - ESP_ERR_INVALID_ARG Parameter error
  *     - ESP_OK Success
  */
-esp_err_t rmt_config(rmt_config_t* rmt_param);
+esp_err_t rmt_config(const rmt_config_t* rmt_param);
 
 /**
  * @brief   register RMT interrupt handler, the handler is an ISR.
@@ -612,7 +612,7 @@ esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle);
  *     - ESP_ERR_INVALID_ARG Parameter error
  *     - ESP_OK Success
  */
-esp_err_t rmt_fill_tx_items(rmt_channel_t channel, rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset);
+esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset);
 
 /**
  * @brief Initialize RMT driver
@@ -670,7 +670,7 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel);
  *     - ESP_ERR_INVALID_ARG Parameter error
  *     - ESP_OK Success
  */
-esp_err_t rmt_write_items(rmt_channel_t channel, rmt_item32_t* rmt_item, int item_num, bool wait_tx_done);
+esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, int item_num, bool wait_tx_done);
 
 /**
  * @brief Wait RMT TX finished.

tools/sdk/include/esp32/esp_err.h

@@ -61,7 +61,10 @@ void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const cha
  * Disabled if assertions are disabled.
  */
 #ifdef NDEBUG
-#define ESP_ERROR_CHECK(x) do { (x); } while (0)
+#define ESP_ERROR_CHECK(x) do {                                         \
+        esp_err_t rc = (x);                                             \
+        (void) sizeof(rc);                                              \
+    } while(0);
 #else
 #define ESP_ERROR_CHECK(x) do {                                         \
         esp_err_t rc = (x);                                             \

tools/sdk/include/esp32/esp_panic.h

@@ -61,6 +61,11 @@ esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
 void esp_clear_watchpoint(int no);
 
 
+/**
+ * @brief Stops panic WDT
+ */
+void esp_panic_wdt_stop(void);
+
 #endif
 
 #ifdef __cplusplus

tools/sdk/include/esp32/esp_task.h

@@ -33,7 +33,7 @@
 
 /* Bt contoller Task */
 /* controller */
-#define ESP_TASK_BT_CONTROLLER_PRIO   (ESP_TASK_PRIO_MAX - 1)
+#define ESP_TASK_BT_CONTROLLER_PRIO   (ESP_TASK_PRIO_MAX - 2)
 #ifdef CONFIG_NEWLIB_NANO_FORMAT
 #define BT_TASK_EXTRA_STACK_SIZE      (0)
 #else

tools/sdk/include/esp32/rom/rtc.h

@@ -61,8 +61,11 @@ extern "C" {
   *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
   *************************************************************************************
   */
+
 #define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
 #define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
+#define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
+#define RTC_APB_FREQ_REG        RTC_CNTL_STORE5_REG
 #define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
 

tools/sdk/include/esp32/soc/bb_reg.h

-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_BB_REG_H_
-#define _SOC_BB_REG_H_
-
-#define apb_bb_offset 0x6001c000
-
-#define BB_DLY                 apb_bb_offset + 0x00009b00  // reg 00
-#define BB_TEST                 apb_bb_offset + 0x00009b08  // reg 02
-#define BB_TM1                 apb_bb_offset + 0x00009b0c  // reg 03
-#define BB_TM_CNTL             apb_bb_offset + 0x00009b14  // reg 05
-#define BB_DEL_CNTL          apb_bb_offset + 0x00009b28  // reg 10
-#define BB_PARAL_CNTL          apb_bb_offset + 0x00009b2c  // reg 11
-#define BB_FSM1                 apb_bb_offset + 0x00009b44  // reg 17
-#define BB_MXG                 apb_bb_offset + 0x00009b48  // reg 18
-#define BB_MNOF                apb_bb_offset + 0x00009b4c  // reg 19
-#define BB_SIZE                apb_bb_offset + 0x00009b50  // reg 20
-#define BB_TM3a                apb_bb_offset + 0x00009b54  // reg 21
-#define BB_TM4a                apb_bb_offset + 0x00009b58  // reg 22
-#define BB_GAIN                apb_bb_offset + 0x00009b5c  // reg 23
-#define BB_CNTL                apb_bb_offset + 0x00009b60  // reg 24
-#define BB_CAD                 apb_bb_offset + 0x00009b64  // reg 25
-#define BB_DET                 apb_bb_offset + 0x00009b68  // reg 26
-#define BB_DETL                apb_bb_offset + 0x00009b6c  // reg 27
-
-#define BB_MASK_PCLL               apb_bb_offset + 0x00009d08  // reg 66
-#define BB_MASK_PCLH               apb_bb_offset + 0x00009d0c  // reg 67
-#define BB_RX_CTRL4                apb_bb_offset + 0x00009d10  // reg 68
-#define BB_RX_CTRL                apb_bb_offset + 0x00009d1c  // reg 71
-#define BB_RX_CTRL2                apb_bb_offset + 0x00009d20  // reg 72
-#define BB_RX_CTRL3                apb_bb_offset + 0x00009d24  // reg 73
-#define BB_DEL4                 apb_bb_offset + 0x00009d40  // reg 80
-#define BB_TM5                 apb_bb_offset + 0x00009d44  // reg 81
-#define BB_TM6                 apb_bb_offset + 0x00009d48  // reg 82
-#define BB_PMCTRL                 apb_bb_offset + 0x00009d4c  // reg 83
-#define BB_PWR                 apb_bb_offset + 0x00009d68  // reg 90
-#define BB_BCTRL2                 apb_bb_offset + 0x00009d70  // reg 92
-
-#define BB_MASK_PL               apb_bb_offset + 0x00009884  // reg 97
-#define BB_MASK_PCHL               apb_bb_offset + 0x00009888  // reg 98
-#define BB_MASK_PCHH               apb_bb_offset + 0x0000988c  // reg 99
-
-#define BB_MASK_CL               apb_bb_offset + 0x0000989c  // reg 103
-#define BB_TONE               apb_bb_offset + 0x000098a0  // reg 104
-#define BB_MASK_CH               apb_bb_offset + 0x000098d4  // reg 117
-#define BB_SER               apb_bb_offset + 0x000098ec  // reg 123
-#define BB_GN_TB               apb_bb_offset + 0x00009e00  // reg 128
-
-#define BB_MODE                apb_bb_offset + 0x00009c00  // reg 640
-#define BB_TXCTRL               apb_bb_offset + 0x00009c04  // reg 641
-#define BB_BCTRL3                apb_bb_offset + 0x00009c08  // reg 642
-#define BB_BCTRL                apb_bb_offset + 0x00009c28  // reg 650
-#define BB_SMCTRL               apb_bb_offset + 0x00009c48  // reg 658
-#define BB_SMCTRL2               apb_bb_offset + 0x00009c4C  // reg 659
-#define BB_TXCNT               apb_bb_offset + 0x00009c58  // reg 662
-#define BB_RXCTRL               apb_bb_offset + 0x00009c68  // reg 666
-
-#define BB_TXGAIN               apb_bb_offset + 0x00009900  // reg 704
-
-#define BB_RXS_CNTL        apb_bb_offset + 0x00009988  // reg 738
-#define BB_MASK2_PCLL               apb_bb_offset + 0x000099a8  // reg 746
-#define BB_MASK2_PCLH               apb_bb_offset + 0x000099ac  // reg 747
-#define BB_MASK_PH               apb_bb_offset + 0x000099b0  // reg 748
-#define BB_MASK2_PCHL               apb_bb_offset + 0x000099b8  // reg 750
-#define BB_MASK2_PCHH               apb_bb_offset + 0x000099bc  // reg 751
-//
-#define BB_TX_TONE_CNTL        apb_bb_offset + 0x000099f0  // reg 764
-#define BB_ADD_CNTL0        apb_bb_offset + 0x00009a28  // reg 778
-#define BB_ADD_CNTL2        apb_bb_offset + 0x00009a2c  // reg 779
-#define BB_GAIN_CNTL0        apb_bb_offset + 0x00009a34  // reg 781
-#define BB_GAIN_CNTL1        apb_bb_offset + 0x00009a38  // reg 782
-#define BB_GAIN_CNTL2        apb_bb_offset + 0x00009a3c  // reg 783
-#define BB_AGCMEM_CTRL         apb_bb_offset + 0x00009a68  // reg 794
-
-#define BB_11B_RECORD          apb_bb_offset + 0x00009808  // reg 802
-#define BB_FILTER_CNTL         apb_bb_offset + 0x0000980c  // reg 803
-#define BB_ANALOG_CTRL1        apb_bb_offset + 0x00009838
-#define BB_ANALOG_CTRL2         apb_bb_offset + 0x0000983c  //reg 815
-#define BB_ANALOG_CTRL3         apb_bb_offset + 0x00009840  //reg 816
-#define BB_RFCFG_CTRL0          apb_bb_offset + 0x00009844  //reg 817
-#define BB_RFCFG_CTRL1          apb_bb_offset + 0x00009848  //reg 818
-
-#define BB_ADD_CNTL1             apb_bb_offset + 0x00009860  //reg824
-#define BB_PA_CNTL             apb_bb_offset + 0x00009864  //reg825
-#define BB_RFCFG_CTRL2          apb_bb_offset + 0x0000986c  //reg827
-#define BB_RXDEL_CTRL        apb_bb_offset + 0x00009d18
-#define BB_RXLENGTH_CTRL        apb_bb_offset + 0x00009d1c
-
-#endif /* _SOC_BB_REG_H_ */
-

tools/sdk/include/freertos/freertos/portmacro.h

@@ -79,6 +79,8 @@ extern "C" {
 #include <xtensa/config/core.h>
 #include <xtensa/config/system.h>	/* required for XSHAL_CLIB */
 #include <xtensa/xtruntime.h>
+#include "esp_crosscore_int.h"
+
 
 //#include "xtensa_context.h"
 
@@ -261,6 +263,18 @@ void vPortYield( void );
 void _frxt_setup_switch( void );
 #define portYIELD()					vPortYield()
 #define portYIELD_FROM_ISR()		_frxt_setup_switch()
+
+static inline uint32_t xPortGetCoreID();
+
+/* Yielding within an API call (when interrupts are off), means the yield should be delayed
+   until interrupts are re-enabled.
+
+   To do this, we use the "cross-core" interrupt as a trigger to yield on this core when interrupts are re-enabled.This
+   is the same interrupt & code path which is used to trigger a yield between CPUs, although in this case the yield is
+   happening on the same CPU.
+*/
+#define portYIELD_WITHIN_API() esp_crosscore_int_send_yield(xPortGetCoreID())
+
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */

tools/sdk/include/mdns/mdns.h

@@ -18,7 +18,11 @@
 extern "C" {
 #endif
 
+#ifndef MDNS_TEST_MODE
 #include <tcpip_adapter.h>
+#else
+#include "esp32_compat.h"
+#endif
 
 struct mdns_server_s;
 typedef struct mdns_server_s mdns_server_t;

tools/sdk/include/soc/soc/apb_ctrl_reg.h

+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_CTRL_REG_H_
+#define _SOC_APB_CTRL_REG_H_
+
+#include "soc.h"
+#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x0)
+/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_QUICK_CLK_CHNG  (BIT(13))
+#define APB_CTRL_QUICK_CLK_CHNG_M  (BIT(13))
+#define APB_CTRL_QUICK_CLK_CHNG_V  0x1
+#define APB_CTRL_QUICK_CLK_CHNG_S  13
+/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_RST_TICK_CNT  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_V  0x1
+#define APB_CTRL_RST_TICK_CNT_S  12
+/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_EN  (BIT(11))
+#define APB_CTRL_CLK_EN_M  (BIT(11))
+#define APB_CTRL_CLK_EN_V  0x1
+#define APB_CTRL_CLK_EN_S  11
+/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_EN  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_V  0x1
+#define APB_CTRL_CLK_320M_EN_S  10
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define APB_CTRL_PRE_DIV_CNT  0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S  0
+
+#define APB_CTRL_XTAL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x4)
+/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define APB_CTRL_XTAL_TICK_NUM  0x000000FF
+#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
+#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
+#define APB_CTRL_XTAL_TICK_NUM_S  0
+
+#define APB_CTRL_PLL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x8)
+/* APB_CTRL_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */
+/*description: */
+#define APB_CTRL_PLL_TICK_NUM  0x000000FF
+#define APB_CTRL_PLL_TICK_NUM_M  ((APB_CTRL_PLL_TICK_NUM_V)<<(APB_CTRL_PLL_TICK_NUM_S))
+#define APB_CTRL_PLL_TICK_NUM_V  0xFF
+#define APB_CTRL_PLL_TICK_NUM_S  0
+
+#define APB_CTRL_CK8M_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0xC)
+/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */
+/*description: */
+#define APB_CTRL_CK8M_TICK_NUM  0x000000FF
+#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
+#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
+#define APB_CTRL_CK8M_TICK_NUM_S  0
+
+#define APB_CTRL_APB_SARADC_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x10)
+/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: I2S input data is from SAR ADC (for DMA)  0: I2S input data
+ is from GPIO matrix*/
+#define APB_CTRL_SARADC_DATA_TO_I2S  (BIT(26))
+#define APB_CTRL_SARADC_DATA_TO_I2S_M  (BIT(26))
+#define APB_CTRL_SARADC_DATA_TO_I2S_V  0x1
+#define APB_CTRL_SARADC_DATA_TO_I2S_S  26
+/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
+  in this case the resolution should not be larger than 11 bits.*/
+#define APB_CTRL_SARADC_DATA_SAR_SEL  (BIT(25))
+#define APB_CTRL_SARADC_DATA_SAR_SEL_M  (BIT(25))
+#define APB_CTRL_SARADC_DATA_SAR_SEL_V  0x1
+#define APB_CTRL_SARADC_DATA_SAR_SEL_S  25
+/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR  (BIT(24))
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V  0x1
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S  24
+/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR  (BIT(23))
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V  0x1
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S  23
+/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define APB_CTRL_SARADC_SAR2_PATT_LEN  0x0000000F
+#define APB_CTRL_SARADC_SAR2_PATT_LEN_M  ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S))
+#define APB_CTRL_SARADC_SAR2_PATT_LEN_V  0xF
+#define APB_CTRL_SARADC_SAR2_PATT_LEN_S  19
+/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define APB_CTRL_SARADC_SAR1_PATT_LEN  0x0000000F
+#define APB_CTRL_SARADC_SAR1_PATT_LEN_M  ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S))
+#define APB_CTRL_SARADC_SAR1_PATT_LEN_V  0xF
+#define APB_CTRL_SARADC_SAR1_PATT_LEN_S  15
+/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider*/
+#define APB_CTRL_SARADC_SAR_CLK_DIV  0x000000FF
+#define APB_CTRL_SARADC_SAR_CLK_DIV_M  ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S))
+#define APB_CTRL_SARADC_SAR_CLK_DIV_V  0xFF
+#define APB_CTRL_SARADC_SAR_CLK_DIV_S  7
+/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_SARADC_SAR_CLK_GATED  (BIT(6))
+#define APB_CTRL_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define APB_CTRL_SARADC_SAR_CLK_GATED_V  0x1
+#define APB_CTRL_SARADC_SAR_CLK_GATED_S  6
+/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: 0: SAR1  1: SAR2  only work for single SAR mode*/
+#define APB_CTRL_SARADC_SAR_SEL  (BIT(5))
+#define APB_CTRL_SARADC_SAR_SEL_M  (BIT(5))
+#define APB_CTRL_SARADC_SAR_SEL_V  0x1
+#define APB_CTRL_SARADC_SAR_SEL_S  5
+/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description: 0: single mode  1: double mode  2: alternate mode*/
+#define APB_CTRL_SARADC_WORK_MODE  0x00000003
+#define APB_CTRL_SARADC_WORK_MODE_M  ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S))
+#define APB_CTRL_SARADC_WORK_MODE_V  0x3
+#define APB_CTRL_SARADC_WORK_MODE_S  3
+/* APB_CTRL_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled
+ by PWDET CTRL*/
+#define APB_CTRL_SARADC_SAR2_MUX  (BIT(2))
+#define APB_CTRL_SARADC_SAR2_MUX_M  (BIT(2))
+#define APB_CTRL_SARADC_SAR2_MUX_V  0x1
+#define APB_CTRL_SARADC_SAR2_MUX_S  2
+/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_START  (BIT(1))
+#define APB_CTRL_SARADC_START_M  (BIT(1))
+#define APB_CTRL_SARADC_START_V  0x1
+#define APB_CTRL_SARADC_START_S  1
+/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_START_FORCE  (BIT(0))
+#define APB_CTRL_SARADC_START_FORCE_M  (BIT(0))
+#define APB_CTRL_SARADC_START_FORCE_V  0x1
+#define APB_CTRL_SARADC_START_FORCE_S  0
+
+#define APB_CTRL_APB_SARADC_CTRL2_REG          (DR_REG_APB_CTRL_BASE + 0x14)
+/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+#define APB_CTRL_SARADC_SAR2_INV  (BIT(10))
+#define APB_CTRL_SARADC_SAR2_INV_M  (BIT(10))
+#define APB_CTRL_SARADC_SAR2_INV_V  0x1
+#define APB_CTRL_SARADC_SAR2_INV_S  10
+/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+#define APB_CTRL_SARADC_SAR1_INV  (BIT(9))
+#define APB_CTRL_SARADC_SAR1_INV_M  (BIT(9))
+#define APB_CTRL_SARADC_SAR1_INV_V  0x1
+#define APB_CTRL_SARADC_SAR1_INV_S  9
+/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number*/
+#define APB_CTRL_SARADC_MAX_MEAS_NUM  0x000000FF
+#define APB_CTRL_SARADC_MAX_MEAS_NUM_M  ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S))
+#define APB_CTRL_SARADC_MAX_MEAS_NUM_V  0xFF
+#define APB_CTRL_SARADC_MAX_MEAS_NUM_S  1
+/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT  (BIT(0))
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define APB_CTRL_APB_SARADC_FSM_REG          (DR_REG_APB_CTRL_BASE + 0x18)
+/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
+/*description: sample cycles*/
+#define APB_CTRL_SARADC_SAMPLE_CYCLE  0x000000FF
+#define APB_CTRL_SARADC_SAMPLE_CYCLE_M  ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S))
+#define APB_CTRL_SARADC_SAMPLE_CYCLE_V  0xFF
+#define APB_CTRL_SARADC_SAMPLE_CYCLE_S  24
+/* APB_CTRL_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */
+/*description: */
+#define APB_CTRL_SARADC_START_WAIT  0x000000FF
+#define APB_CTRL_SARADC_START_WAIT_M  ((APB_CTRL_SARADC_START_WAIT_V)<<(APB_CTRL_SARADC_START_WAIT_S))
+#define APB_CTRL_SARADC_START_WAIT_V  0xFF
+#define APB_CTRL_SARADC_START_WAIT_S  16
+/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */
+/*description: */
+#define APB_CTRL_SARADC_STANDBY_WAIT  0x000000FF
+#define APB_CTRL_SARADC_STANDBY_WAIT_M  ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S))
+#define APB_CTRL_SARADC_STANDBY_WAIT_V  0xFF
+#define APB_CTRL_SARADC_STANDBY_WAIT_S  8
+/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: */
+#define APB_CTRL_SARADC_RSTB_WAIT  0x000000FF
+#define APB_CTRL_SARADC_RSTB_WAIT_M  ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S))
+#define APB_CTRL_SARADC_RSTB_WAIT_V  0xFF
+#define APB_CTRL_SARADC_RSTB_WAIT_S  0
+
+#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_APB_CTRL_BASE + 0x1C)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S  0
+
+#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_APB_CTRL_BASE + 0x20)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S  0
+
+#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_APB_CTRL_BASE + 0x24)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S  0
+
+#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_APB_CTRL_BASE + 0x28)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S  0
+
+#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_APB_CTRL_BASE + 0x2C)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S  0
+
+#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_APB_CTRL_BASE + 0x30)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S  0
+
+#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_APB_CTRL_BASE + 0x34)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S  0
+
+#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_APB_CTRL_BASE + 0x38)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S  0
+
+#define APB_CTRL_APLL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x3C)
+/* APB_CTRL_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */
+/*description: */
+#define APB_CTRL_APLL_TICK_NUM  0x000000FF
+#define APB_CTRL_APLL_TICK_NUM_M  ((APB_CTRL_APLL_TICK_NUM_V)<<(APB_CTRL_APLL_TICK_NUM_S))
+#define APB_CTRL_APLL_TICK_NUM_V  0xFF
+#define APB_CTRL_APLL_TICK_NUM_S  0
+
+#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x7C)
+/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
+/*description: */
+#define APB_CTRL_DATE  0xFFFFFFFF
+#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
+#define APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_CTRL_DATE_S  0
+
+
+
+
+#endif /*_SOC_APB_CTRL_REG_H_ */
+
+

tools/sdk/include/soc/soc/apb_ctrl_struct.h

+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_CTRL_STRUCT_H_
+#define _SOC_APB_CTRL_STRUCT_H_
+typedef struct {
+    union {
+        struct {
+            volatile uint32_t pre_div:       10;
+            volatile uint32_t clk_320m_en:    1;
+            volatile uint32_t clk_en:         1;
+            volatile uint32_t rst_tick:       1;
+            volatile uint32_t quick_clk_chng: 1;
+            volatile uint32_t reserved14:    18;
+        };
+        volatile uint32_t val;
+    }clk_conf;
+    union {
+        struct {
+            volatile uint32_t xtal_tick:     8;
+            volatile uint32_t reserved8:    24;
+        };
+        volatile uint32_t val;
+    }xtal_tick_conf;
+    union {
+        struct {
+            volatile uint32_t pll_tick:     8;
+            volatile uint32_t reserved8:   24;
+        };
+        volatile uint32_t val;
+    }pll_tick_conf;
+    union {
+        struct {
+            volatile uint32_t ck8m_tick:     8;
+            volatile uint32_t reserved8:    24;
+        };
+        volatile uint32_t val;
+    }ck8m_tick_conf;
+    union {
+        struct {
+            volatile uint32_t start_force:       1;
+            volatile uint32_t start:             1;
+            volatile uint32_t sar2_mux:          1;       /*1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled by PWDET CTRL*/
+            volatile uint32_t work_mode:         2;       /*0: single mode  1: double mode  2: alternate mode*/
+            volatile uint32_t sar_sel:           1;       /*0: SAR1  1: SAR2  only work for single SAR mode*/
+            volatile uint32_t sar_clk_gated:     1;
+            volatile uint32_t sar_clk_div:       8;       /*SAR clock divider*/
+            volatile uint32_t sar1_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
+            volatile uint32_t sar2_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
+            volatile uint32_t sar1_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC1 CTRL*/
+            volatile uint32_t sar2_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC2 CTRL*/
+            volatile uint32_t data_sar_sel:      1;       /*1: sar_sel will be coded by the MSB of the 16-bit output data  in this case the resolution should not be larger than 11 bits.*/
+            volatile uint32_t data_to_i2s:       1;       /*1: I2S input data is from SAR ADC (for DMA)  0: I2S input data is from GPIO matrix*/
+            volatile uint32_t reserved27:        5;
+        };
+        volatile uint32_t val;
+    }saradc_ctrl;
+    union {
+        struct {
+            volatile uint32_t meas_num_limit: 1;
+            volatile uint32_t max_meas_num:   8;          /*max conversion number*/
+            volatile uint32_t sar1_inv:       1;          /*1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+            volatile uint32_t sar2_inv:       1;          /*1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+            volatile uint32_t reserved11:    21;
+        };
+        volatile uint32_t val;
+    }saradc_ctrl2;
+    union {
+        struct {
+            volatile uint32_t rstb_wait:    8;
+            volatile uint32_t standby_wait: 8;
+            volatile uint32_t start_wait:   8;
+            volatile uint32_t sample_cycle: 8;            /*sample cycles*/
+        };
+        volatile uint32_t val;
+    }saradc_fsm;
+    volatile uint32_t saradc_sar1_patt_tab1;                 /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
+    volatile uint32_t saradc_sar1_patt_tab2;                 /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+    volatile uint32_t saradc_sar1_patt_tab3;                 /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
+    volatile uint32_t saradc_sar1_patt_tab4;                 /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
+    volatile uint32_t saradc_sar2_patt_tab1;                 /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
+    volatile uint32_t saradc_sar2_patt_tab2;                 /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
+    volatile uint32_t saradc_sar2_patt_tab3;                 /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
+    volatile uint32_t saradc_sar2_patt_tab4;                 /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
+    union {
+        struct {
+            volatile uint32_t apll_tick:     8;
+            volatile uint32_t reserved8:    24;
+        };
+        volatile uint32_t val;
+    }apll_tick_conf;
+    volatile uint32_t reserved_40;
+    volatile uint32_t reserved_44;
+    volatile uint32_t reserved_48;
+    volatile uint32_t reserved_4c;
+    volatile uint32_t reserved_50;
+    volatile uint32_t reserved_54;
+    volatile uint32_t reserved_58;
+    volatile uint32_t reserved_5c;
+    volatile uint32_t reserved_60;
+    volatile uint32_t reserved_64;
+    volatile uint32_t reserved_68;
+    volatile uint32_t reserved_6c;
+    volatile uint32_t reserved_70;
+    volatile uint32_t reserved_74;
+    volatile uint32_t reserved_78;
+    volatile uint32_t date;                                      /**/
+} apb_ctrl_dev_t;
+
+#endif  /* _SOC_APB_CTRL_STRUCT_H_ */

tools/sdk/include/soc/soc/bb_reg.h

+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_BB_REG_H_
+#define _SOC_BB_REG_H_
+
+/* Some of the baseband control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
+#define BB_FFT_FORCE_PU (BIT(3))
+#define BB_FFT_FORCE_PU_S 3
+#define BB_FFT_FORCE_PD (BIT(2))
+#define BB_FFT_FORCE_PD_S 2
+#define BB_DC_EST_FORCE_PU (BIT(1))
+#define BB_DC_EST_FORCE_PU_S 1
+#define BB_DC_EST_FORCE_PD (BIT(0))
+#define BB_DC_EST_FORCE_PD_S 0
+
+
+#endif /* _SOC_BB_REG_H_ */
+

tools/sdk/include/soc/soc/fe_reg.h

+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the RF frontend control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
+#define FE_IQ_EST_FORCE_PU (BIT(5))
+#define FE_IQ_EST_FORCE_PU_S 5
+#define FE_IQ_EST_FORCE_PD (BIT(4))
+#define FE_IQ_EST_FORCE_PD_S 4
+
+#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
+#define FE2_TX_INF_FORCE_PU (BIT(10))
+#define FE2_TX_INF_FORCE_PU_S 10
+#define FE2_TX_INF_FORCE_PD (BIT(9))
+#define FE2_TX_INF_FORCE_PD_S 9

tools/sdk/include/soc/soc/nrx_reg.h

+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the WiFi RX control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
+#define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_S 7
+#define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_S 6
+#define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_S 5
+#define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_S 4
+#define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_S 3
+#define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_S 2
+#define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_S 1
+#define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_S 0

tools/sdk/include/soc/soc/rtc.h

+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock, and sleep functions.
+ *
+ * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ * - rtc_sleep: entry into sleep modes
+ * - rtc_init: initialization
+ */
+
+
+/**
+ * @brief Possible main XTAL frequency values.
+ *
+ * Enum values should be equal to frequency in MHz.
+ */
+typedef enum {
+    RTC_XTAL_FREQ_AUTO = 0,     //!< Automatic XTAL frequency detection
+    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
+    RTC_XTAL_FREQ_26M = 26,     //!< 26 MHz XTAL
+    RTC_XTAL_FREQ_24M = 24,     //!< 24 MHz XTAL
+} rtc_xtal_freq_t;
+
+/**
+ * @brief CPU frequency values
+ */
+typedef enum {
+    RTC_CPU_FREQ_XTAL = 0,      //!< Main XTAL frequency
+    RTC_CPU_FREQ_80M = 1,       //!< 80 MHz
+    RTC_CPU_FREQ_160M = 2,      //!< 160 MHz
+    RTC_CPU_FREQ_240M = 3,      //!< 240 MHz
+    RTC_CPU_FREQ_2M = 4,        //!< 2 MHz
+} rtc_cpu_freq_t;
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef enum {
+    RTC_SLOW_FREQ_RTC = 0,      //!< Internal 150 kHz RC oscillator
+    RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
+    RTC_SLOW_FREQ_8MD256 = 2,   //!< Internal 8 MHz RC oscillator, divided by 256
+} rtc_slow_freq_t;
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef enum {
+    RTC_FAST_FREQ_XTALD4 = 0,   //!< Main XTAL, divided by 4
+    RTC_FAST_FREQ_8M = 1,       //!< Internal 8 MHz RC oscillator
+} rtc_fast_freq_t;
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = 0,       //!< Currently selected RTC SLOW_CLK
+    RTC_CAL_8MD256 = 1,        //!< Internal 8 MHz RC oscillator, divided by 256
+    RTC_CAL_32K_XTAL = 2       //!< External 32 kHz XTAL
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    rtc_xtal_freq_t xtal_freq : 8;  //!< Main XTAL frequency
+    rtc_cpu_freq_t cpu_freq : 3;    //!< CPU frequency to set
+    rtc_fast_freq_t fast_freq : 1;  //!< RTC_FAST_CLK frequency to set
+    rtc_slow_freq_t slow_freq : 2;  //!< RTC_SLOW_CLK frequency to set
+    uint32_t clk_8m_div : 3;        //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
+    uint32_t slow_clk_dcap : 8;     //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 8;      //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = RTC_XTAL_FREQ_AUTO, \
+    .cpu_freq = RTC_CPU_FREQ_80M, \
+    .fast_freq = RTC_FAST_FREQ_8M, \
+    .slow_freq = RTC_SLOW_FREQ_RTC, \
+    .clk_8m_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+}
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
+ * to auto detect XTAL frequency. Auto detection is performed by comparing
+ * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
+ * high temperatures the frequency of the internal 8MHz oscillator may drift
+ * enough for auto detection to be unreliable.
+ * Auto detection code will attempt to distinguish between 26MHz and 40MHz
+ * crystals. 24 MHz crystals are not supported by auto detection code.
+ * If XTAL frequency can not be auto detected, this 26MHz frequency will be used.
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value passed to rtc_clk_init function, or if the value was
+ * RTC_XTAL_FREQ_AUTO, the detected XTAL frequency.
+ *
+ * @return XTAL frequency, one of rtc_xtal_freq_t
+ */
+rtc_xtal_freq_t rtc_clk_xtal_freq_get();
+
+/**
+ * @brief Enable or disable 32 kHz XTAL oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_32k_enable(bool en);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled();
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * Output from 8 MHz internal oscillator is passed into a configurable
+ * divider, which by default divides the input clock frequency by 256.
+ * Output of the divider may be used as RTC_SLOW_CLK source.
+ * Output of the divider is referred to in register descriptions and code as
+ * 8md256 or simply d256. Divider values other than 256 may be configured, but
+ * this facility is not currently needed, so is not exposed in the code.
+ *
+ * When 8MHz/256 divided output is not needed, the divider should be disabled
+ * to reduce power consumption.
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ * @param d256_en true to enable /256 divider
+ */
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled();
+
+/**
+ * @brief Get the state of /256 divider which is applied to 8MHz clock
+ * @return true if the divided output is enabled
+ */
+bool rtc_clk_8md256_enabled();
+
+/**
+ * @brief Enable or disable APLL
+ *
+ * Output frequency is given by the formula:
+ * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
+ *
+ * The dividend in this expression should be in the range of 240 - 600 MHz.
+ *
+ * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
+ *
+ * @param enable  true to enable, false to disable
+ * @param sdm0  frequency adjustment parameter, 0..255
+ * @param sdm1  frequency adjustment parameter, 0..255
+ * @param sdm2  frequency adjustment parameter, 0..63
+ * @param o_div  frequency divider, 0..31
+ */
+void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1,
+        uint32_t sdm2, uint32_t o_div);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param slow_freq clock source (one of rtc_slow_freq_t values)
+ */
+void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of rtc_slow_freq_t values)
+ */
+rtc_slow_freq_t rtc_clk_slow_freq_get();
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param fast_freq clock source (one of rtc_fast_freq_t values)
+ */
+void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of rtc_fast_freq_t values)
+ */
+rtc_fast_freq_t rtc_clk_fast_freq_get();
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
+ * will enable the PLL. Otherwise, PLL will be disabled.
+ * Note: this function is not optimized for switching speed. It may take several
+ * hundred microseconds to perform frequency switch.
+ *
+ * @param cpu_freq  new CPU frequency
+ */
+void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq);
+
+/**
+ * @brief Get the currently selected CPU frequency
+ *
+ * Although CPU can be clocked by APLL and RTC 8M sources, such support is not
+ * exposed through this library. As such, this function will not return
+ * meaningful values when these clock sources are configured (e.g. using direct
+ * access to clock selection registers). In debug builds, it will assert; in
+ * release builds, it will return RTC_CPU_FREQ_XTAL.
+ *
+ * @return CPU frequency (one of rtc_cpu_freq_t values)
+ */
+rtc_cpu_freq_t rtc_clk_cpu_freq_get();
+
+/**
+ * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
+ * @param cpu_freq  CPU frequency, on of rtc_cpu_freq_t values
+ * @return CPU frequency, in HZ
+ */
+uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq);
+
+/**
+ * @brief Store new APB frequency value into RTC_APB_FREQ_REG
+ *
+ * This function doesn't change any hardware clocks.
+ *
+ * Functions which perform frequency switching and change APB frequency call
+ * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
+ * (one of RTC general purpose retention registers). This should not normally
+ * be called from application code.
+ *
+ * @param apb_freq  new APB frequency, in Hz
+ */
+void rtc_clk_apb_freq_update(uint32_t apb_freq);
+
+/**
+ * @brief Get the current stored APB frequency.
+ * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get();
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get();
+
+/**
+ * @brief sleep configuration for rtc_sleep_init function
+ */
+typedef struct {
+    uint32_t soc_clk_sel : 2;           //!< SoC clock select, see RTC_CNTL_SOC_CLK_SEL
+    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
+    uint32_t rtc_mem_inf_fpu : 1;       //!< force normal voltage in sleep mode (RTC memory)
+    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
+    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
+    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
+    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
+    uint32_t wifi_pd_en : 1;            //!< power down WiFi
+    uint32_t rom_mem_pd_en : 1;         //!< power down main RAM and ROM
+    uint32_t deep_slp : 1;              //!< power down digital domain
+    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
+    uint32_t dig_dbias_wak : 3;         //!< set bias for digital domain, in active mode
+    uint32_t dig_dbias_slp : 3;         //!< set bias for digital domain, in sleep mode
+    uint32_t rtc_dbias_wak : 3;         //!< set bias for RTC domain, in active mode
+    uint32_t rtc_dbias_slp : 3;         //!< set bias for RTC domain, in sleep mode
+    uint32_t lslp_meminf_pd : 1;        //!< remove all peripheral force power up flags
+} rtc_sleep_config_t;
+
+/**
+ * Default initializer for rtc_sleep_config_t
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use) based on a combination of RTC_SLEEP_PD_x flags.
+ *
+ * @param RTC_SLEEP_PD_x flags combined using bitwise OR
+ */
+#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
+    .soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL, \
+    .lslp_mem_inf_fpu = 0, \
+    .rtc_mem_inf_fpu = 0, \
+    .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
+    .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
+    .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
+    .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
+    .wifi_pd_en = 0, \
+    .rom_mem_pd_en = 0, \
+    .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
+    .wdt_flashboot_mod_en = 0, \
+    .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
+    .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
+    .rtc_dbias_wak = RTC_CNTL_DBIAS_0V90, \
+    .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
+    .lslp_meminf_pd = 1 \
+};
+
+#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
+#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
+#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
+#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
+#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
+
+/**
+ * @brief Prepare the chip to enter sleep mode
+ *
+ * This function configures various power control state machines to handle
+ * entry into light sleep or deep sleep mode, switches APB and CPU clock source
+ * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
+ *
+ * This function does not actually enter sleep mode; this is done using
+ * rtc_sleep_start function. Software may do some other actions between
+ * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
+ * wakeup sources.
+ * @param cfg sleep mode configuration
+ */
+void rtc_sleep_init(rtc_sleep_config_t cfg);
+
+
+/**
+ * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
+ * @param t value of RTC counter at which wakeup from sleep will happen;
+ *          only the lower 48 bits are used
+ */
+void rtc_sleep_set_wakeup_time(uint64_t t);
+
+
+#define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
+#define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup
+#define RTC_GPIO_TRIG_EN    BIT(2)  //!< GPIO wakeup (light sleep only)
+#define RTC_TIMER_TRIG_EN   BIT(3)  //!< Timer wakeup
+#define RTC_SDIO_TRIG_EN    BIT(4)  //!< SDIO wakeup (light sleep only)
+#define RTC_MAC_TRIG_EN     BIT(5)  //!< MAC wakeup (light sleep only)
+#define RTC_UART0_TRIG_EN   BIT(6)  //!< UART0 wakeup (light sleep only)
+#define RTC_UART1_TRIG_EN   BIT(7)  //!< UART1 wakeup (light sleep only)
+#define RTC_TOUCH_TRIG_EN   BIT(8)  //!< Touch wakeup
+#define RTC_ULP_TRIG_EN     BIT(9)  //!< ULP wakeup
+#define RTC_BT_TRIG_EN      BIT(10) //!< BT wakeup (light sleep only)
+
+/**
+ * @brief Enter deep or light sleep mode
+ *
+ * This function enters the sleep mode previously configured using rtc_sleep_init
+ * function. Before entering sleep, software should configure wake up sources
+ * appropriately (set up GPIO wakeup registers, timer wakeup registers,
+ * and so on).
+ *
+ * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
+ * rejected by hardware (based on reject_opt flags), this function never returns.
+ * When the chip wakes up from deep sleep, CPU is reset and execution starts
+ * from ROM bootloader.
+ *
+ * If light sleep mode was configured using rtc_sleep_init, this function
+ * returns on wakeup, or if sleep is rejected by hardware.
+ *
+ * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
+ *                    combined with OR)
+ * @param reject_opt  bit mask of sleep reject reasons:
+ *                      - RTC_CNTL_GPIO_REJECT_EN
+ *                      - RTC_CNTL_SDIO_REJECT_EN
+ *                    These flags are used to prevent entering sleep when e.g.
+ *                    an external host is communicating via SDIO slave
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
+
+/**
+ * RTC power and clock control initialization settings
+ */
+typedef struct {
+    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
+    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
+    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
+    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
+    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
+    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
+} rtc_config_t;
+
+/**
+ * Default initializer of rtc_config_t.
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use).
+ */
+#define RTC_CONFIG_DEFAULT() {\
+    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
+    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
+    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
+    .clkctl_init = 1, \
+    .pwrctl_init = 1, \
+    .rtc_dboost_fpd = 1 \
+}
+
+/**
+ * Initialize RTC clock and power control related functions
+ * @param cfg configuration options as rtc_config_t
+ */
+void rtc_init(rtc_config_t cfg);
+
+
+#ifdef __cplusplus
+}
+#endif
+

tools/sdk/include/esp32/soc/rtc_cntl_reg.h → tools/sdk/include/soc/soc/rtc_cntl_reg.h

@@ -321,18 +321,21 @@
 #define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
 #define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
 #define RTC_CNTL_PLL_BUF_WAIT_S  24
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
 /*description: XTAL wait cycles in slow_clk_rtc*/
 #define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
 #define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
 #define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
 #define RTC_CNTL_XTL_BUF_WAIT_S  14
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  20
 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
 /*description: CK8M wait cycles in slow_clk_rtc*/
 #define RTC_CNTL_CK8M_WAIT  0x000000FF
 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
 #define RTC_CNTL_CK8M_WAIT_V  0xFF
 #define RTC_CNTL_CK8M_WAIT_S  6
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
 /*description: CPU stall wait cycles in fast_clk_rtc*/
 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
@@ -892,6 +895,10 @@
 #define RTC_CNTL_SOC_CLK_SEL_M  ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S))
 #define RTC_CNTL_SOC_CLK_SEL_V  0x3
 #define RTC_CNTL_SOC_CLK_SEL_S  27
+#define RTC_CNTL_SOC_CLK_SEL_XTL    0
+#define RTC_CNTL_SOC_CLK_SEL_PLL    1
+#define RTC_CNTL_SOC_CLK_SEL_8M     2
+#define RTC_CNTL_SOC_CLK_SEL_APLL   3
 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
 /*description: CK8M force power up*/
 #define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
@@ -910,6 +917,7 @@
 #define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
 #define RTC_CNTL_CK8M_DFREQ_V  0xFF
 #define RTC_CNTL_CK8M_DFREQ_S  17
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
 /*description: CK8M force no gating during sleep*/
 #define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
@@ -1109,6 +1117,7 @@
 #define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
 #define RTC_CNTL_SCK_DCAP_V  0xFF
 #define RTC_CNTL_SCK_DCAP_S  14
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
 /*description: DIG_REG_DBIAS during wakeup*/
 #define RTC_CNTL_DIG_DBIAS_WAK  0x00000007
@@ -1128,6 +1137,19 @@
 #define RTC_CNTL_SCK_DCAP_FORCE_V  0x1
 #define RTC_CNTL_SCK_DCAP_FORCE_S  7
 
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ * Valid if RTC_CNTL_DBG_ATTEN is 0.
+ */
+#define RTC_CNTL_DBIAS_0V90 0
+#define RTC_CNTL_DBIAS_0V95 1
+#define RTC_CNTL_DBIAS_1V00 2
+#define RTC_CNTL_DBIAS_1V05 3
+#define RTC_CNTL_DBIAS_1V10 4
+#define RTC_CNTL_DBIAS_1V15 5
+#define RTC_CNTL_DBIAS_1V20 6
+#define RTC_CNTL_DBIAS_1V25 7
+
 #define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x80)
 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
 /*description: enable power down rtc_peri in sleep*/
@@ -1257,6 +1279,24 @@
 #define RTC_CNTL_FASTMEM_FORCE_NOISO_V  0x1
 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S  0
 
+/* Useful groups of RTC_CNTL_PWC_REG bits */
+#define RTC_CNTL_MEM_FORCE_ISO    \
+    (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO)
+#define RTC_CNTL_MEM_FORCE_NOISO  \
+    (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
+#define RTC_CNTL_MEM_PD_EN        \
+    (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN)
+#define RTC_CNTL_MEM_FORCE_PU     \
+    (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
+#define RTC_CNTL_MEM_FORCE_PD     \
+    (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD)
+#define RTC_CNTL_MEM_FOLW_CPU     \
+    (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
+#define RTC_CNTL_MEM_FORCE_LPU    \
+    (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU)
+#define RTC_CNTL_MEM_FORCE_LPD    \
+    (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD)
+
 #define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x84)
 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
 /*description: enable power down digital core in sleep*/
@@ -1415,6 +1455,20 @@
 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
 
+/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */
+#define RTC_CNTL_CPU_ROM_RAM_PD_EN \
+    (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\
+     RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\
+     RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN)
+#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \
+    (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\
+     RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\
+     RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU)
+#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \
+    (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\
+     RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\
+     RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD
+
 #define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x88)
 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
 /*description: digital core force no ISO*/
@@ -1567,6 +1621,16 @@
 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
 
+/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */
+#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO   \
+    (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\
+     RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\
+     RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO)
+#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \
+    (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\
+     RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\
+     RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO)
+
 #define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x8c)
 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
 /*description: enable RTC WDT*/
@@ -1650,6 +1714,12 @@
 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(7))
 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S  7
+/* RTC_CNTL_WDT_STGX : */
+/*description: stage action selection values */
+#define RTC_WDT_STG_SEL_OFF             0
+#define RTC_WDT_STG_SEL_INT             1
+#define RTC_WDT_STG_SEL_RESET_CPU       2
+#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
 
 #define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x90)
 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */

tools/sdk/include/soc/soc/rtc_io_struct.h

+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_IO_STRUCT_H_
+#define _SOC_RTC_IO_STRUCT_H_
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reserved0:        14;
+            uint32_t data:18;              /*GPIO0~17 output value*/
+        };
+        uint32_t val;
+    } out;
+    union {
+        struct {
+            uint32_t reserved0:             14;
+            uint32_t w1ts:18;         /*GPIO0~17 output value write 1 to set*/
+        };
+        uint32_t val;
+    } out_w1ts;
+    union {
+        struct {
+            uint32_t reserved0:             14;
+            uint32_t w1tc:18;         /*GPIO0~17 output value write 1 to clear*/
+        };
+        uint32_t val;
+    } out_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:      14;
+            uint32_t enable:18;                /*GPIO0~17 output enable*/
+        };
+        uint32_t val;
+    } enable;
+    union {
+        struct {
+            uint32_t reserved0:           14;
+            uint32_t w1ts:18;           /*GPIO0~17 output enable write 1 to set*/
+        };
+        uint32_t val;
+    } enable_w1ts;
+    union {
+        struct {
+            uint32_t reserved0:           14;
+            uint32_t w1tc:18;           /*GPIO0~17 output enable write 1 to clear*/
+        };
+        uint32_t val;
+    } enable_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:          14;
+            uint32_t status:18;            /*GPIO0~17 interrupt status*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t reserved0:               14;
+            uint32_t w1ts:18;       /*GPIO0~17 interrupt status write 1 to set*/
+        };
+        uint32_t val;
+    } status_w1ts;
+    union {
+        struct {
+            uint32_t reserved0:               14;
+            uint32_t w1tc:18;       /*GPIO0~17 interrupt status write 1 to clear*/
+        };
+        uint32_t val;
+    } status_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:       14;
+            uint32_t in:18;               /*GPIO0~17 input value*/
+        };
+        uint32_t val;
+    } in_val;
+    union {
+        struct {
+            uint32_t reserved0:                   2;
+            uint32_t pad_driver:    1;    /*if set to 0: normal output  if set to 1: open drain*/
+            uint32_t reserved3:                   4;
+            uint32_t int_type:      3;    /*if set to 0: GPIO interrupt disable  if set to 1: rising edge trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
+            uint32_t wakeup_enable: 1;    /*GPIO wake up enable  only available in light sleep*/
+            uint32_t reserved11:                 21;
+        };
+        uint32_t val;
+    } pin[18];
+    union {
+        struct {
+            uint32_t sel0:          5;
+            uint32_t sel1:          5;
+            uint32_t sel2:          5;
+            uint32_t sel3:          5;
+            uint32_t sel4:          5;
+            uint32_t no_gating_12m: 1;
+            uint32_t reserved26:              6;
+        };
+        uint32_t val;
+    } debug_sel;
+    uint32_t dig_pad_hold;                              /*select the digital pad hold value.*/
+    union {
+        struct {
+            uint32_t reserved0: 30;
+            uint32_t hall_phase: 1;                     /*Reverse phase of hall sensor*/
+            uint32_t xpd_hall:   1;                     /*Power on hall sensor and connect to VP and VN*/
+        };
+        uint32_t val;
+    } hall_sens;
+    union {
+        struct {
+            uint32_t reserved0:      4;
+            uint32_t sense4_fun_ie:  1;                 /*the input enable of the pad*/
+            uint32_t sense4_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
+            uint32_t sense4_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
+            uint32_t sense4_fun_sel: 2;                 /*the functional selection signal of the pad*/
+            uint32_t sense3_fun_ie:  1;                 /*the input enable of the pad*/
+            uint32_t sense3_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
+            uint32_t sense3_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
+            uint32_t sense3_fun_sel: 2;                 /*the functional selection signal of the pad*/
+            uint32_t sense2_fun_ie:  1;                 /*the input enable of the pad*/
+            uint32_t sense2_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
+            uint32_t sense2_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
+            uint32_t sense2_fun_sel: 2;                 /*the functional selection signal of the pad*/
+            uint32_t sense1_fun_ie:  1;                 /*the input enable of the pad*/
+            uint32_t sense1_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
+            uint32_t sense1_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
+            uint32_t sense1_fun_sel: 2;                 /*the functional selection signal of the pad*/
+            uint32_t sense4_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t sense3_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t sense2_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t sense1_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t sense4_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t sense3_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t sense2_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t sense1_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
+        };
+        uint32_t val;
+    } sensor_pads;
+    union {
+        struct {
+            uint32_t reserved0:   18;
+            uint32_t adc2_fun_ie:  1;                   /*the input enable of the pad*/
+            uint32_t adc2_slp_ie:  1;                   /*the input enable of the pad in sleep status*/
+            uint32_t adc2_slp_sel: 1;                   /*the sleep status selection signal of the pad*/
+            uint32_t adc2_fun_sel: 2;                   /*the functional selection signal of the pad*/
+            uint32_t adc1_fun_ie:  1;                   /*the input enable of the pad*/
+            uint32_t adc1_slp_ie:  1;                   /*the input enable of the pad in sleep status*/
+            uint32_t adc1_slp_sel: 1;                   /*the sleep status selection signal of the pad*/
+            uint32_t adc1_fun_sel: 2;                   /*the functional selection signal of the pad*/
+            uint32_t adc2_mux_sel: 1;                   /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t adc1_mux_sel: 1;                   /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t adc2_hold:    1;                   /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t adc1_hold:    1;                   /*hold the current value of the output when setting the hold to �1�*/
+        };
+        uint32_t val;
+    } adc_pad;
+    union {
+        struct {
+            uint32_t reserved0:          10;
+            uint32_t dac_xpd_force: 1;            /*Power on DAC1. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
+            uint32_t fun_ie:        1;            /*the input enable of the pad*/
+            uint32_t slp_oe:        1;            /*the output enable of the pad in sleep status*/
+            uint32_t slp_ie:        1;            /*the input enable of the pad in sleep status*/
+            uint32_t slp_sel:       1;            /*the sleep status selection signal of the pad*/
+            uint32_t fun_sel:       2;            /*the functional selection signal of the pad*/
+            uint32_t mux_sel:       1;            /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t xpd_dac:       1;            /*Power on DAC1. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
+            uint32_t dac:           8;            /*PAD DAC1 control code.*/
+            uint32_t rue:           1;            /*the pull up enable of the pad*/
+            uint32_t rde:           1;            /*the pull down enable of the pad*/
+            uint32_t hold:          1;            /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t drv:           2;            /*the driver strength of the pad*/
+        };
+        uint32_t val;
+    } pad_dac[2];
+    union {
+        struct {
+            uint32_t reserved0:      1;
+            uint32_t dbias_xtal_32k: 2;                 /*32K XTAL self-bias reference control.*/
+            uint32_t dres_xtal_32k:  2;                 /*32K XTAL resistor bias control.*/
+            uint32_t x32p_fun_ie:    1;                 /*the input enable of the pad*/
+            uint32_t x32p_slp_oe:    1;                 /*the output enable of the pad in sleep status*/
+            uint32_t x32p_slp_ie:    1;                 /*the input enable of the pad in sleep status*/
+            uint32_t x32p_slp_sel:   1;                 /*the sleep status selection signal of the pad*/
+            uint32_t x32p_fun_sel:   2;                 /*the functional selection signal of the pad*/
+            uint32_t x32n_fun_ie:    1;                 /*the input enable of the pad*/
+            uint32_t x32n_slp_oe:    1;                 /*the output enable of the pad in sleep status*/
+            uint32_t x32n_slp_ie:    1;                 /*the input enable of the pad in sleep status*/
+            uint32_t x32n_slp_sel:   1;                 /*the sleep status selection signal of the pad*/
+            uint32_t x32n_fun_sel:   2;                 /*the functional selection signal of the pad*/
+            uint32_t x32p_mux_sel:   1;                 /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t x32n_mux_sel:   1;                 /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t xpd_xtal_32k:   1;                 /*Power up 32kHz crystal oscillator*/
+            uint32_t dac_xtal_32k:   2;                 /*32K XTAL bias current DAC.*/
+            uint32_t x32p_rue:       1;                 /*the pull up enable of the pad*/
+            uint32_t x32p_rde:       1;                 /*the pull down enable of the pad*/
+            uint32_t x32p_hold:      1;                 /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t x32p_drv:       2;                 /*the driver strength of the pad*/
+            uint32_t x32n_rue:       1;                 /*the pull up enable of the pad*/
+            uint32_t x32n_rde:       1;                 /*the pull down enable of the pad*/
+            uint32_t x32n_hold:      1;                 /*hold the current value of the output when setting the hold to �1�*/
+            uint32_t x32n_drv:       2;                 /*the driver strength of the pad*/
+        };
+        uint32_t val;
+    } xtal_32k_pad;
+    union {
+        struct {
+            uint32_t reserved0:     23;
+            uint32_t dcur:     2;                 /*touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP  this setting is available*/
+            uint32_t drange:   2;                 /*touch sensor saw wave voltage range.*/
+            uint32_t drefl:    2;                 /*touch sensor saw wave bottom voltage.*/
+            uint32_t drefh:    2;                 /*touch sensor saw wave top voltage.*/
+            uint32_t xpd_bias: 1;                 /*touch sensor bias power on.*/
+        };
+        uint32_t val;
+    } touch_cfg;
+    union {
+        struct {
+            uint32_t reserved0:         12;
+            uint32_t to_gpio: 1;             /*connect the rtc pad input to digital pad input �0� is availbale GPIO4*/
+            uint32_t fun_ie:  1;             /*the input enable of the pad*/
+            uint32_t slp_oe:  1;             /*the output enable of the pad in sleep status*/
+            uint32_t slp_ie:  1;             /*the input enable of the pad in sleep status*/
+            uint32_t slp_sel: 1;             /*the sleep status selection signal of the pad*/
+            uint32_t fun_sel: 2;             /*the functional selection signal of the pad*/
+            uint32_t mux_sel: 1;             /*�1� select the digital function  �0�slection the rtc function*/
+            uint32_t xpd:     1;             /*touch sensor power on.*/
+            uint32_t tie_opt: 1;             /*default touch sensor tie option. 0: tie low  1: tie high.*/
+            uint32_t start:   1;             /*start touch sensor.*/
+            uint32_t dac:     3;             /*touch sensor slope control. 3-bit for each touch panel  default 100.*/
+            uint32_t reserved26:         1;
+            uint32_t rue:     1;             /*the pull up enable of the pad*/
+            uint32_t rde:     1;             /*the pull down enable of the pad*/
+            uint32_t drv:     2;             /*the driver strength of the pad*/
+            uint32_t hold:    1;             /*hold the current value of the output when setting the hold to �1�*/
+        };
+        uint32_t val;
+    } touch_pad[10];
+    union {
+        struct {
+            uint32_t reserved0:      27;
+            uint32_t sel: 5;                /*select the wakeup source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/
+        };
+        uint32_t val;
+    } ext_wakeup0;
+    union {
+        struct {
+            uint32_t reserved0:      27;
+            uint32_t sel: 5;                /*select the external xtl power source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/
+        };
+        uint32_t val;
+    } xtl_ext_ctr;
+    union {
+        struct {
+            uint32_t reserved0:        23;
+            uint32_t debug_bit_sel: 5;
+            uint32_t scl_sel:   2;              /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/
+            uint32_t sda_sel:   2;              /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/
+        };
+        uint32_t val;
+    } sar_i2c_io;
+    union {
+        struct {
+            uint32_t date:      28;                     /*date*/
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_io_dev_t;
+#endif  /* _SOC_RTC_IO_STRUCT_H_ */

tools/sdk/include/esp32/soc/soc.h → tools/sdk/include/soc/soc/soc.h

@@ -179,11 +179,14 @@
 #define DR_REG_LEDC_BASE                        0x3ff59000
 #define DR_REG_EFUSE_BASE                       0x3ff5A000
 #define DR_REG_SPI_ENCRYPT_BASE                 0x3ff5B000
+#define DR_REG_NRX_BASE                         0x3ff5CC00
+#define DR_REG_BB_BASE                          0x3ff5D000
 #define DR_REG_PWM_BASE                         0x3ff5E000
 #define DR_REG_TIMERGROUP0_BASE                 0x3ff5F000
 #define DR_REG_TIMERGROUP1_BASE                 0x3ff60000
 #define DR_REG_SPI2_BASE                        0x3ff64000
 #define DR_REG_SPI3_BASE                        0x3ff65000
+#define DR_REG_APB_CTRL_BASE                    0x3ff66000
 #define DR_REG_I2C1_EXT_BASE                    0x3ff67000
 #define DR_REG_SDMMC_BASE                       0x3ff68000
 #define DR_REG_EMAC_BASE                        0x3ff69000

tools/sdk/include/tcpip_adapter/tcpip_adapter.h

@@ -136,6 +136,39 @@ typedef enum{
     TCPIP_ADAPTER_IP_REQUEST_RETRY_TIME         = 52,   /**< request IP address retry counter */
 } tcpip_adapter_option_id_t;
 
+struct tcpip_adapter_api_msg_s;
+typedef int (*tcpip_adapter_api_fn)(struct tcpip_adapter_api_msg_s *msg);
+typedef struct tcpip_adapter_api_msg_s {
+    int type;  /**< The first field MUST be int */
+    int ret;
+    tcpip_adapter_api_fn api_fn;
+    tcpip_adapter_if_t tcpip_if;
+    tcpip_adapter_ip_info_t *ip_info;
+    uint8_t *mac;
+    const char *hostname;
+} tcpip_adapter_api_msg_t;
+
+#define TCPIP_ADAPTER_TRHEAD_SAFE 1
+#define TCPIP_ADAPTER_IPC_LOCAL   0 
+#define TCPIP_ADAPTER_IPC_REMOTE  1
+
+#define TCPIP_ADAPTER_IPC_CALL(_if, _mac, _ip, _hostname, _fn) do {\
+    tcpip_adapter_api_msg_t msg;\
+    memset(&msg, 0, sizeof(msg));\
+    msg.tcpip_if = (_if);\
+    msg.mac      = (_mac);\
+    msg.ip_info  = (_ip);\
+    msg.hostname = (_hostname);\
+    msg.api_fn   = (_fn);\
+    if (TCPIP_ADAPTER_IPC_REMOTE == tcpip_adapter_ipc_check(&msg)) {\
+        ESP_LOGD(TAG, "check: remote, if=%d fn=%p\n", (_if), (_fn));\
+        return msg.ret;\
+    } else {\
+        ESP_LOGD(TAG, "check: local, if=%d fn=%p\n", (_if), (_fn));\
+    }\
+}while(0)
+
+
 /**
  * @brief  Initialize tcpip adapter
  *

tools/sdk/ld/esp32.common.ld

@@ -88,8 +88,7 @@ SECTIONS
     *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)
     *libphy.a:(.literal .text .literal.* .text.*)
     *librtc.a:(.literal .text .literal.* .text.*)
-    *librtc_clk.a:(.literal .text .literal.* .text.*)
-    *librtc_pm.a:(.literal .text .literal.* .text.*)
+    *libsoc.a:(.literal .text .literal.* .text.*)
     *libpp.a:pp.o(.literal .text .literal.* .text.*)
     *libpp.a:lmac.o(.literal .text .literal.* .text.*)
     *libpp.a:wdev.o(.literal .text .literal.* .text.*)
@@ -97,6 +96,7 @@ SECTIONS
     *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)
     *libhal.a:(.literal .text .literal.* .text.*)
     *libcoexist.a:(.literal .text .literal.* .text.*)
+    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)
     _iram_text_end = ABSOLUTE(.);
   } > iram0_0_seg
 

tools/sdk/ld/esp32.rom.ld

@@ -125,7 +125,7 @@ PROVIDE ( __divdi3 = 0x4000ca84 );
 PROVIDE ( __divsc3 = 0x40064200 );
 PROVIDE ( __divsf3 = 0x4000234c );
 PROVIDE ( __divsi3 = 0x4000c7b8 );
-PROVIDE ( dummy_len_plus = 0x3ffae290 );
+PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );
 PROVIDE ( __dummy_lock = 0x4000c728 );
 PROVIDE ( __dummy_lock_try = 0x4000c730 );
 PROVIDE ( ecc_env = 0x3ffb8d60 );
@@ -1349,13 +1349,10 @@ PROVIDE ( sbrk = 0x400017f4 );
 PROVIDE ( _sbrk_r = 0x4000bce4 );
 PROVIDE ( __sccl = 0x4000c498 );
 PROVIDE ( __sclose = 0x400011b8 );
-PROVIDE ( SelectSpiFunction = 0x40061f84 );
-PROVIDE ( SelectSpiQIO = 0x40061ddc );
 PROVIDE ( __seofread = 0x40001148 );
 PROVIDE ( setjmp = 0x40056268 );
 PROVIDE ( setlocale = 0x40059568 );
 PROVIDE ( _setlocale_r = 0x4005950c );
-PROVIDE ( SetSpiDrvs = 0x40061e78 );
 PROVIDE ( __sf_fake_stderr = 0x3ff96458 );
 PROVIDE ( __sf_fake_stdin = 0x3ff96498 );
 PROVIDE ( __sf_fake_stdout = 0x3ff96478 );
@@ -1404,40 +1401,6 @@ PROVIDE ( slc_set_host_io_max_window = 0x4000b89c );
 PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );
 PROVIDE ( __smakebuf_r = 0x40059108 );
 PROVIDE ( specialModP256 = 0x4001600c );
-PROVIDE ( spi_cache_sram_init = 0x400626e4 );
-PROVIDE ( SPIClkConfig = 0x40062bc8 );
-PROVIDE ( SPI_Common_Command = 0x4006246c );
-PROVIDE ( spi_dummy_len_fix = 0x40061d90 );
-PROVIDE ( SPI_Encrypt_Write = 0x40062e78 );
-PROVIDE ( SPIEraseArea = 0x400631ac );
-PROVIDE ( SPIEraseBlock = 0x40062c4c );
-PROVIDE ( SPIEraseChip = 0x40062c14 );
-PROVIDE ( SPIEraseSector = 0x40062ccc );
-PROVIDE ( spi_flash_attach = 0x40062a6c );
-/* NB: SPIUnlock @ 0x400628b0 has been replaced with an updated
-    version in the "spi_flash" component */
-PROVIDE ( SPILock = 0x400628f0 );
-PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 );
-PROVIDE ( spi_modes = 0x3ff99270 );
-PROVIDE ( SPIParamCfg = 0x40063238 );
-PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c );
-PROVIDE ( SPIRead = 0x40062ed8 );
-PROVIDE ( SPIReadModeCnfig = 0x40062944 );
-/* This is static function, but can be used, not generated by script*/
-PROVIDE ( SPI_read_status = 0x4006226c );
-/* This is static function, but can be used, not generated by script*/
-PROVIDE ( SPI_read_status_high = 0x40062448 );
-PROVIDE ( SPI_user_command_read = 0x400621b0 );
-PROVIDE ( SPI_flashchip_data = 0x3ffae270 );
-PROVIDE ( SPIWrite = 0x40062d50 );
-/* This is static function, but can be used, not generated by script*/
-PROVIDE ( SPI_write_enable = 0x40062320 );
-PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 );
-PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 );
-/* This is static function, but can be used, not generated by script*/
-PROVIDE ( SPI_write_status = 0x400622f0 );
-/* This is static function, but can be used, not generated by script */
-PROVIDE ( SPI_Wait_Idle = 0x400622c0 );
 PROVIDE ( srand = 0x40001004 );
 PROVIDE ( __sread = 0x40001118 );
 PROVIDE ( __srefill_r = 0x400593d4 );
@@ -1569,6 +1532,13 @@ PROVIDE ( xthal_set_intclear = 0x4000c1ec );
 PROVIDE ( _xtos_set_intlevel = 0x4000bfdc );
 PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );
 PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );
+PROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );
+PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );
+PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );
+PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );
+PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );
+PROVIDE ( esp_rom_spiflash_master_config_readmode = 0x40062944 );
+PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
 
 /* 
 These functions are xtos-related (or call xtos-related functions) and do not play well 

tools/sdk/ld/esp32.rom.spiflash.ld

+/*
+	Address table for SPI driver functions in ESP32 ROM.
+	These functions are only linked from ROM when SPI_FLASH_ROM_DRIVER_PATCH is not set in configuration.
+*/
+
+PROVIDE ( esp_rom_spiflash_write_encrypted = 0x40062e78 );
+PROVIDE ( esp_rom_spiflash_erase_area = 0x400631ac );
+PROVIDE ( esp_rom_spiflash_erase_block = 0x40062c4c );
+PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 );
+PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc );
+PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 );
+PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 );
+PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062944 );
+PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c );
+PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 );
+PROVIDE ( esp_rom_spiflash_write = 0x40062d50 );
+PROVIDE ( esp_rom_spiflash_enable_write = 0x40062320 );
+PROVIDE ( esp_rom_spiflash_write_status = 0x400622f0 );
+
+/* always using patched versions of these functions 
+PROVIDE ( esp_rom_spiflash_wait_idle = 0x400622c0 );
+PROVIDE ( esp_rom_spiflash_unlock = 0x400????? );
+*/