Merge branch 'master' of https://github.com/Tencent/TencentOS-tiny

board/TencentOS_tiny_EVB_MX_Plus/KEIL/nb-iot_demo/startup_stm32l431xx.s

+;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;* File Name          : startup_stm32l431xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L431xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x100
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     0                                 ; Reserved
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                 ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     0                                 ; Reserved
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SDMMC1_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

devices/bc35_28_95_lwm2m/bc35_28_95_lwm2m.c

+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+#include "bc35_28_95_lwm2m.h"
+#include "tos.h"
+#include "tos_at.h"
+#include "tos_hal.h"
+#include "sal_module_wrapper.h"
+
+#include "stdio.h"
+#include "stdbool.h"
+#include "ctype.h"
+
+static char __num2hex(uint8_t num)
+{
+    if (num <= 0x9) {
+        return num + '0';
+    }
+
+    if ((0xA <= num) && (num <= 0xF)) {
+        return num - 0xA + 'A';
+    }
+
+    return (char)-1;
+}
+
+void __hex2str(uint8_t *in, char *out, int len)
+{
+	int i = 0;
+
+	for (i = 0; i < len; ++i) {
+		out[i * 2] = __num2hex(in[i] >> 4);
+		out[i * 2 + 1] = __num2hex(in[i] & 0x0F);
+	}
+	out[2 * len] = '\0';
+}
+
+static int bc35_28_95_reset(void){
+    int try = 0;
+    at_echo_t echo;
+
+    tos_at_echo_create(&echo, NULL, 0, "Neul");
+    while (try++ < 10) {
+        tos_at_cmd_exec(&echo, 6000, "AT+NRB\r\n");
+        if (echo.status == AT_ECHO_STATUS_EXPECT) {
+            printf("wait for bcxx reboot!\n");
+            return 0;
+        }
+    }
+    return -1; 
+}
+
+static int bc35_28_95_echo_close(void)
+{
+    at_echo_t echo;
+
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000, "ATE0\r\n");
+    if (echo.status == AT_ECHO_STATUS_OK) {
+        return 0;
+    }
+    return -1;
+}
+
+static int bc35_28_95_check_cfun(void)
+{
+    int try = 0;
+    at_echo_t echo;
+
+    tos_at_echo_create(&echo, NULL, 0, "+CFUN:1");
+    while (try++ < 10) {
+        tos_at_cmd_exec(&echo, 1000, "AT+CFUN?\r\n");
+        if (echo.status == AT_ECHO_STATUS_OK || echo.status == AT_ECHO_STATUS_EXPECT) {
+            return 0;
+        }
+    }
+    return -1;
+}
+
+static int bc35_28_95_cfun_set(char mode)
+{
+    int try = 0;
+    at_echo_t echo;
+
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    while (try++ < 10) {
+        if(mode){
+            tos_at_cmd_exec(&echo, 1000, "AT+CFUN=1\r\n");
+        }
+        else{
+            tos_at_cmd_exec(&echo, 1000, "AT+CFUN=0\r\n");
+        }
+        if (echo.status == AT_ECHO_STATUS_OK) {
+            return 0;
+        }
+    }
+    return -1;
+}
+
+static int bc35_28_95_net_set(char mode)
+{
+    int try = 0;
+    at_echo_t echo;
+
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    while (try++ < 10) {
+        if(mode){
+            tos_at_cmd_exec(&echo, 1000, "AT+CGATT=1\r\n");
+        }
+        else{
+            tos_at_cmd_exec(&echo, 1000, "AT+CGATT=0\r\n");
+        }
+        if (echo.status == AT_ECHO_STATUS_OK) {
+            return 0;
+        }
+    }
+    return -1;
+}
+
+static int bc35_28_95_check_net(void)
+{
+    int try = 0;
+    at_echo_t echo;
+
+    tos_at_echo_create(&echo, NULL, 0, "+CGATT:1");
+    while (try++ < 10) {
+        tos_at_cmd_exec(&echo, 1000, "AT+CGATT?\r\n");
+        if (echo.status == AT_ECHO_STATUS_EXPECT) {
+            return 0;
+        }
+    }
+    return -1;
+}
+
+static int bc35_28_95_signal_quality_check(void)
+{
+    int rssi, ber;
+    at_echo_t echo;
+    char echo_buffer[32], *str;
+
+    tos_at_echo_create(&echo, echo_buffer, sizeof(echo_buffer), NULL);
+    tos_at_cmd_exec(&echo, 1000, "AT+CSQ\r\n");
+    if (echo.status != AT_ECHO_STATUS_OK) {
+        return -1;
+    }
+
+    str = strstr(echo.buffer, "+CSQ:");
+    sscanf(str, "+CSQ:%d,%d", &rssi, &ber);
+    if (rssi == 99) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static int bc35_28_95_nband_set(char band){
+    at_echo_t echo;
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000, "AT+NBAND=%d\r\n",band);
+    if (echo.status == AT_ECHO_STATUS_OK) {
+        return 0;
+    }
+    return -1;
+}
+static int bc35_28_95_auto_report(char report){
+    at_echo_t echo;
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000, "AT+NNMI=%d\r\n",report);
+    if (echo.status == AT_ECHO_STATUS_OK) {
+        return 0;
+    }
+    return -1;
+}
+
+
+static int bc35_28_95_autoconnect_config(char mode)
+{
+    int try = 0;
+    at_echo_t echo;
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    while (try++ < 10) {
+        if(mode){
+            tos_at_cmd_exec(&echo, 1000, "AT+NCONFIG=AUTOCONNECT,TRUE\r\n");
+        }
+        else{
+            tos_at_cmd_exec(&echo, 1000, "AT+NCONFIG=AUTOCONNECT,FALSE\r\n");
+        }  
+        if(echo.status == AT_ECHO_STATUS_OK){
+            return 0;
+        }
+    }
+    return -1;
+}
+
+static int bc35_28_95_print_IMEI(void) {
+    at_echo_t echo;
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000, "AT+CGSN=1\r\n");
+    if (echo.status == AT_ECHO_STATUS_OK) {
+        return 0;
+    }
+    return -1;
+   
+}
+static int bc35_28_95_print_CIMI(void) {
+    at_echo_t echo;
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000, "AT+CIMI\r\n");
+    if (echo.status == AT_ECHO_STATUS_OK) {
+        return 0;
+    }
+    return -1;
+   
+}    
+static int bc35_28_95_print_NBAND(void) {
+    at_echo_t echo;
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000, "AT+NBAND=?\r\n");
+    if (echo.status == AT_ECHO_STATUS_OK) {
+        return 0;
+    }
+    return -1;
+   
+}
+
+static int bc35_28_95_lwm2m_init(void)
+{
+    printf("Init BC95_28_95 ...wait reset!\n" );
+    at_delay_ms(5000);
+    if (bc35_28_95_echo_close() != 0) {
+        printf("echo close FAILED\n");
+        return -1;
+    }
+    if(bc35_28_95_autoconnect_config(0)!=0){
+        printf("autoconnect false FAILED\n");
+        return -1;       
+    };
+    if (bc35_28_95_cfun_set(0) != 0) {
+        printf("close_cfun FAILED\n");
+        return -1;
+    }
+    if(bc35_28_95_nband_set(5)!=0){
+        printf("nband_set FAILED\n");
+        return -1;      
+    }
+
+    printf("Init bc35_28_95 Done\n" );
+    return 0;
+}
+
+static int bc35_28_95_lwm2m_connect(const char *ip, const char *port, sal_proto_t proto)
+{
+    int id, try = 0, is_connected = 0;
+    at_echo_t echo;
+    char echo_buffer[32];
+
+    tos_at_echo_create(&echo, echo_buffer, sizeof(echo_buffer), NULL);
+    tos_at_cmd_exec(&echo, 2000, "AT+NCDP=%s,%s\r\n,",ip,port);
+    if (echo.status != AT_ECHO_STATUS_OK) {
+        return -1;
+    }
+  
+    if(bc35_28_95_reset()!=0){
+        printf("reset FAILED\n");
+        return -1;            
+    }   
+    tos_task_delay(1000);
+    bc35_28_95_check_cfun();
+    bc35_28_95_cfun_set(1);
+    bc35_28_95_net_set(1);
+    bc35_28_95_autoconnect_config(1);
+    bc35_28_95_auto_report(1);
+    bc35_28_95_print_IMEI();
+    bc35_28_95_print_CIMI();
+    bc35_28_95_print_NBAND();
+    if (bc35_28_95_signal_quality_check() != 0) {
+        printf("check csq FAILED\n");
+        return -1;
+    }    
+    while (try++ < 10) {
+        if (bc35_28_95_check_net()==0){
+            is_connected = 1;
+            break;
+        }
+        tos_task_delay(1000);
+       continue;
+    }   
+    if(is_connected){
+        id=0;
+        sscanf(echo.buffer, "%d", &id);
+        id = tos_at_channel_alloc_id(id, ip, port);
+        if (id == -1) {
+            return -1;
+        }
+    } 
+    else{
+        return -1;
+    }
+    return id;
+}
+
+static int bc35_28_95_lwm2m_send(int id, const void *buf, size_t len)
+{
+    char *str_buf = NULL;
+    at_echo_t echo;
+
+    if (tos_at_global_lock_pend() != 0) {
+        return -1;
+    }
+    str_buf = tos_mmheap_calloc(2 * len + 1, sizeof(char));
+    if (!str_buf) {
+        tos_at_global_lock_post();
+        return -1;
+    }
+    __hex2str((uint8_t *)buf, str_buf, len);
+    tos_at_echo_create(&echo, NULL, 0, NULL);
+    tos_at_cmd_exec(&echo, 1000,
+                            "AT+NMGS=%d,%s\r\n",
+                            len, str_buf);
+    tos_mmheap_free(str_buf);
+    if (echo.status != AT_ECHO_STATUS_OK) {
+        tos_at_global_lock_post();
+        return -1;
+    }
+    tos_at_global_lock_post();
+    return len;
+}
+
+__STATIC__ uint8_t incoming_data_buffer[1024];
+
+__STATIC__ void bc35_28_95_lwm2m_incoming_data_process(void)
+{
+    uint8_t data;
+    int channel_id = 0, data_len = 0;
+
+    /*
+    +NNMI:2,aabb\r\n
+    2: Length
+    aabb: data
+    */
+
+    while (1) {
+        if (tos_at_uart_read(&data, 1) != 1) {
+            return;
+        }
+
+        if (data == ',') {
+            break;
+        }
+        data_len = data_len * 10 + (data - '0');
+    }
+    
+
+    if (data_len > sizeof(incoming_data_buffer)/2) {
+        data_len = sizeof(incoming_data_buffer)/2;
+    }  
+
+    if (tos_at_uart_read(incoming_data_buffer, data_len*2) != data_len*2) {
+        return;
+    }
+    
+    tos_at_channel_write(channel_id, incoming_data_buffer, data_len*2);
+}
+
+at_event_t bc35_28_95_at_event[] = {
+    { "+NNMI:", bc35_28_95_lwm2m_incoming_data_process },
+};
+
+static int bc35_28_95_lwm2m_recv_timeout(int id, void *buf, size_t len, uint32_t timeout)
+{
+     return tos_at_channel_read_timed(id, buf, len, timeout);
+}
+
+static int bc35_28_95_lwm2m_recv(int id, void *buf, size_t len)
+{
+    return bc35_28_95_lwm2m_recv_timeout(id, buf, len, (uint32_t)4000);
+}
+
+static int bc35_28_95_lwm2m_close(int id)
+{
+    tos_at_channel_free(id);
+    return 0;
+}
+
+sal_module_t sal_module_bc35_28_95_lwm2m = {
+    .init           = bc35_28_95_lwm2m_init,
+    .connect        = bc35_28_95_lwm2m_connect,
+    .send           = bc35_28_95_lwm2m_send,
+    .recv_timeout   = bc35_28_95_lwm2m_recv_timeout,
+    .recv           = bc35_28_95_lwm2m_recv,
+    .close          = bc35_28_95_lwm2m_close,
+    .parse_domain   = NULL,
+};
+
+int bc35_28_95_sal_lwm2m_init(hal_uart_port_t uart_port)
+{
+    if (tos_at_init(uart_port, bc35_28_95_at_event,
+                        sizeof(bc35_28_95_at_event) / sizeof(bc35_28_95_at_event[0])) != 0) {
+        return -1;
+    }
+
+    if (tos_sal_module_register(&sal_module_bc35_28_95_lwm2m) != 0) {
+        return -1;
+    }
+
+    if (tos_sal_module_init() != 0) {
+        return -1;
+    }
+
+    return 0;
+}

devices/bc35_28_95_lwm2m/bc35_28_95_lwm2m.h

+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __BC35_28_95_LWM2M_H__
+#define __BC35_28_95_LWM2M_H__
+
+#include "tos_at.h"
+
+int bc35_28_95_sal_lwm2m_init(hal_uart_port_t uart_port);
+
+#endif /* __BC35_28_95_LWM2M_H__ */
+

examples/nb-iot_demo/nb-iot_example.c

+#include "bc35_28_95_lwm2m.h"
+#include "mcu_init.h"
+#include "sal_module_wrapper.h"
+#include "cmsis_os.h"
+
+
+#define NB_IoT_TEST_TASK_STK_SIZE         1024
+void nb_iot_demo(void);
+osThreadDef(nb_iot_demo, osPriorityNormal, 1, NB_IoT_TEST_TASK_STK_SIZE);
+
+int socket_id=-1;
+#define RECV_LEN            1024
+uint8_t recv_data[RECV_LEN];
+
+void nb_iot_demo(void)
+{
+    int recv_len = -1;
+    int bc35_28_95_sal_lwm2m_init(hal_uart_port_t uart_port);
+    bc35_28_95_sal_lwm2m_init(HAL_UART_PORT_0);
+    socket_id = tos_sal_module_connect("49.4.85.232","5683",TOS_SAL_PROTO_UDP);
+    if(socket_id !=-1){
+        printf("connect to cloud success! fd: %d\n", socket_id);	
+    }
+	else{
+        printf("connect to cloud failed!\n");
+	}
+	while (1) {
+		tos_sal_module_send(socket_id, (const void*)"22", strlen("22"));
+
+		recv_len = tos_sal_module_recv(socket_id, recv_data, sizeof(recv_data));
+		if (recv_len < 0) {
+			printf("task receive error\n");
+		} else if (recv_len == 0) {
+		    printf("task receive none\n");
+		} else {
+			recv_data[recv_len] = 0;
+			printf("task: receive len: %d\nmsg from remote: %s\n", recv_len, recv_data);
+		}
+
+		tos_sleep_ms(2000);
+	}
+}
+
+void application_entry(void *arg)
+{
+    osThreadCreate(osThread(nb_iot_demo), NULL);
+}