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提交 ed2d2b0d 编写于 作者: B bernard
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Merge master branch to stable v1.2.x branch.

上级 17ef8ff6 40b7eba4
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.gitignore
浏览文件 @ ed2d2b0d
......@@ -11,3 +11,9 @@
*.ilk
build
*~
*.o
*.bak
*.dep
*.lib
*.a
README.md
浏览文件 @ ed2d2b0d
......@@ -24,7 +24,6 @@ RT-Thread RTOS can support many architectures:
* ARM Cortex-R4
* ARM Cortex-A8/A9
* ARM920T/ARM926 etc
* MIPS
* x86
* PowerPC
......
bsp/beaglebone/drivers/serial.c
浏览文件 @ ed2d2b0d
......@@ -10,6 +10,7 @@
* Change Logs:
* Date Author Notes
* 2013-07-06 Bernard the first version
* 2014-01-11 RTsien support UART0 to UART5 straightly
*/
#include <rthw.h>
......@@ -38,7 +39,7 @@ static void am33xx_uart_isr(int irqno, void* param)
iir = UART_IIR_REG(uart->base);
if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
{
rt_hw_serial_isr(serial);
}
......@@ -162,14 +163,66 @@ static const struct rt_uart_ops am33xx_uart_ops =
am33xx_getc,
};
/* UART1 device driver structure */
struct serial_ringbuffer uart1_int_rx;
struct am33xx_uart uart1 =
/* UART device driver structure */
#ifdef RT_USING_UART0
struct serial_ringbuffer uart0_int_rx;
struct am33xx_uart uart0 =
{
UART0_BASE,
UART0_INT,
};
struct rt_serial_device serial0;
#endif
#ifdef RT_USING_UART1
struct serial_ringbuffer uart1_int_rx;
struct am33xx_uart uart1 =
{
UART1_BASE,
UART1_INT,
};
struct rt_serial_device serial1;
#endif
#ifdef RT_USING_UART2
struct serial_ringbuffer uart2_int_rx;
struct am33xx_uart uart2 =
{
UART2_BASE,
UART2_INT,
};
struct rt_serial_device serial2;
#endif
#ifdef RT_USING_UART3
struct serial_ringbuffer uart3_int_rx;
struct am33xx_uart uart3 =
{
UART3_BASE,
UART3_INT,
};
struct rt_serial_device serial3;
#endif
#ifdef RT_USING_UART4
struct serial_ringbuffer uart4_int_rx;
struct am33xx_uart uart4 =
{
UART4_BASE,
UART4_INT,
};
struct rt_serial_device serial4;
#endif
#ifdef RT_USING_UART5
struct serial_ringbuffer uart5_int_rx;
struct am33xx_uart uart5 =
{
UART5_BASE,
UART5_INT,
};
struct rt_serial_device serial5;
#endif
#define write_reg(base, value) *(int*)(base) = value
#define read_reg(base) *(int*)(base)
......@@ -219,11 +272,41 @@ static void start_uart_clk(void)
;
/* enable uart1 */
#ifdef RT_USING_UART1
CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2;
/* wait for uart1 clk */
while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
;
#endif
#ifdef RT_USING_UART2
CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2;
/* wait for uart2 clk */
while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
;
#endif
#ifdef RT_USING_UART3
CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2;
/* wait for uart3 clk */
while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
;
#endif
#ifdef RT_USING_UART4
CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2;
/* wait for uart4 clk */
while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
;
#endif
#ifdef RT_USING_UART5
CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2;
/* wait for uart5 clk */
while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
;
#endif
/* Waiting for the L4LS UART clock */
while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10)))
;
......@@ -236,46 +319,173 @@ static void config_pinmux(void)
ctlm_base = AM33XX_CTLM_REGS;
/* make sure the pin mux is OK for uart */
#ifdef RT_USING_UART1
REG32(ctlm_base + 0x800 + 0x180) = 0x20;
REG32(ctlm_base + 0x800 + 0x184) = 0x00;
#endif
#ifdef RT_USING_UART2
REG32(ctlm_base + 0x800 + 0x150) = 0x20;
REG32(ctlm_base + 0x800 + 0x154) = 0x00;
#endif
#ifdef RT_USING_UART3
REG32(ctlm_base + 0x800 + 0x164) = 0x01;
#endif
#ifdef RT_USING_UART4
REG32(ctlm_base + 0x800 + 0x070) = 0x26;
REG32(ctlm_base + 0x800 + 0x074) = 0x06;
#endif
#ifdef RT_USING_UART5
REG32(ctlm_base + 0x800 + 0x0C4) = 0x24;
REG32(ctlm_base + 0x800 + 0x0C0) = 0x04;
#endif
}
int rt_hw_serial_init(void)
{
struct am33xx_uart* uart;
struct serial_configure config;
uart = &uart1;
uart->base = UART1_BASE;
poweron_per_domain();
start_uart_clk();
config_pinmux();
#ifdef RT_USING_UART0
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial0.ops = &am33xx_uart_ops;
serial0.int_rx = &uart0_int_rx;
serial0.config = config;
/* enable RX interrupt */
UART_IER_REG(uart0.base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(uart0.irq, am33xx_uart_isr, &serial0, "uart0");
rt_hw_interrupt_control(uart0.irq, 0, 0);
rt_hw_interrupt_mask(uart0.irq);
/* register UART0 device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
#endif
#ifdef RT_USING_UART1
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial1.ops = &am33xx_uart_ops;
serial1.int_rx = &uart1_int_rx;
serial1.config = config;
/* enable RX interrupt */
UART_IER_REG(uart1.base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(uart1.irq, am33xx_uart_isr, &serial1, "uart1");
rt_hw_interrupt_control(uart1.irq, 0, 0);
rt_hw_interrupt_mask(uart1.irq);
/* register UART0 device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart1);
#endif
#ifdef RT_USING_UART2
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial2.ops = &am33xx_uart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config = config;
/* enable RX interrupt */
UART_IER_REG(uart->base) = 0x01;
UART_IER_REG(uart2.base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(uart->irq, am33xx_uart_isr, &serial1, "uart1");
rt_hw_interrupt_control(uart->irq, 0, 0);
rt_hw_interrupt_mask(uart->irq);
rt_hw_interrupt_install(uart2.irq, am33xx_uart_isr, &serial2, "uart2");
rt_hw_interrupt_control(uart2.irq, 0, 0);
rt_hw_interrupt_mask(uart2.irq);
/* register UART2 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart2);
#endif
/* register UART1 device */
rt_hw_serial_register(&serial1, "uart1",
#ifdef RT_USING_UART3
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial3.ops = &am33xx_uart_ops;
serial3.int_rx = &uart_3_int_rx;
serial3.config = config;
/* enable RX interrupt */
UART_IER_REG(uart3.base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(uart3.irq, am33xx_uart_isr, &serial3, "uart3");
rt_hw_interrupt_control(uart3.irq, 0, 0);
rt_hw_interrupt_mask(uart3.irq);
/* register UART3 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
uart);
&uart3);
#endif
#ifdef RT_USING_UART4
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial4.ops = &am33xx_uart_ops;
serial4.int_rx = &uart4_int_rx;
serial4.config = config;
/* enable RX interrupt */
UART_IER_REG(uart4.base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(uart4.irq, am33xx_uart_isr, &serial4, "uart4");
rt_hw_interrupt_control(uart4.irq, 0, 0);
rt_hw_interrupt_mask(uart4.irq);
/* register UART4 device */
rt_hw_serial_register(&serial4, "uart4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart4);
#endif
#ifdef RT_USING_UART5
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial5.ops = &am33xx_uart_ops;
serial5.int_rx = &uart5_int_rx;
serial5.config = config;
/* enable RX interrupt */
UART_IER_REG(uart5.base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(uart5.irq, am33xx_uart_isr, &serial5, "uart5");
rt_hw_interrupt_control(uart5.irq, 0, 0);
rt_hw_interrupt_mask(uart5.irq);
/* register UART4 device */
rt_hw_serial_register(&serial5, "uart5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart5);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_serial_init);
bsp/beaglebone/rtconfig.h
浏览文件 @ ed2d2b0d
......@@ -73,6 +73,18 @@
#define RT_USING_DEVICE_IPC
// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
#define RT_USING_SERIAL
// <bool name="RT_USING_UART0" description="Using uart0" default="true" >
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using uart1" default="true" >
#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using uart2" default="true" >
#define RT_USING_UART2
// <bool name="RT_USING_UART3" description="Using uart3" default="true" >
//#define RT_USING_UART3
// <bool name="RT_USING_UART4" description="Using uart4" default="true" >
#define RT_USING_UART4
// <bool name="RT_USING_UART5" description="Using uart5" default="true" >
#define RT_USING_UART5
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
......@@ -84,7 +96,7 @@
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
......
bsp/simulator/drivers/nanddrv_file.c
浏览文件 @ ed2d2b0d
......@@ -4,23 +4,23 @@
#include <string.h>
#define NAND_SIM "nand.bin"
#if 1
#define OOB_SIZE 64
#define PAGE_DATA_SIZE 2048
#define PAGE_SIZE (2048 + 64)
#define PAGE_PER_BLOCK 64
#define BLOCK_SIZE (PAGE_SIZE * PAGE_PER_BLOCK)
#define ECC_SIZE ((PAGE_DATA_SIZE) * 3 / 256)
#define BLOCK_NUM 512
// #define BLOCK_NUM 2048
#else
#define OOB_SIZE 16
#define PAGE_SIZE (512 + OOB_SIZE)
#define PAGE_DATA_SIZE 512
#define PAGE_PER_BLOCK 32
#define BLOCK_SIZE (PAGE_SIZE * PAGE_PER_BLOCK)
#define ECC_SIZE ((PAGE_DATA_SIZE) * 3 / 256)
#define BLOCK_NUM 512
#endif
#define ECC_SIZE ((PAGE_DATA_SIZE) * 3 / 256)
#define BLOCK_SIZE (PAGE_SIZE * PAGE_PER_BLOCK)
#define PAGE_SIZE (PAGE_DATA_SIZE + OOB_SIZE)
static unsigned char block_data[BLOCK_SIZE];
static struct rt_mtd_nand_device _nanddrv_file_device;
......
bsp/simulator/drivers/sdl_fb.c
浏览文件 @ ed2d2b0d
......@@ -11,6 +11,8 @@
#define SDL_SCREEN_WIDTH 800
#define SDL_SCREEN_HEIGHT 480
extern void rt_hw_exit(void);
struct sdlfb_device
{
struct rt_device parent;
......@@ -54,7 +56,7 @@ static rt_err_t sdlfb_control(rt_device_t dev, rt_uint8_t cmd, void *args)
info = (struct rt_device_graphic_info *) args;
info->bits_per_pixel = 16;
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
info->framebuffer = device->screen->pixels;
info->width = device->screen->w;
info->height = device->screen->h;
......@@ -304,10 +306,14 @@ static void *sdl_loop(void *lpParam)
break;
}
if (quit)
break;
if (quit)
{
exit(1);
break;
}
}
//exit(0);
rt_hw_exit();
return 0;
}
......
components/CMSIS/Include/arm_common_tables.h
浏览文件 @ ed2d2b0d
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
......@@ -31,8 +48,46 @@ extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef[6144];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */
components/CMSIS/Include/arm_math.h
浏览文件 @ ed2d2b0d
此差异已折叠。
components/CMSIS/Include/core_cm0.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.01
* @date 13. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
......@@ -54,7 +69,7 @@
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
......@@ -590,9 +605,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
......@@ -640,9 +655,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
......
components/CMSIS/Include/core_cm0plus.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.01
* @date 22. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
......@@ -54,7 +69,7 @@
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
......@@ -361,8 +376,8 @@ typedef struct
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
......@@ -701,9 +716,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
......@@ -751,9 +766,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
......
components/CMSIS/Include/core_cm3.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V3.01
* @date 22. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
......@@ -54,7 +69,7 @@
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
......@@ -636,14 +651,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
......@@ -1516,9 +1531,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
......
components/CMSIS/Include/core_cm4.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V3.01
* @date 22. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
......@@ -54,7 +69,7 @@
/* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
__CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
......@@ -669,14 +684,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
......@@ -1661,9 +1676,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
......
components/CMSIS/Include/core_cm4_simd.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.01
* @date 06. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
......@@ -110,6 +124,8 @@
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
......@@ -624,6 +640,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1,
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
......
components/CMSIS/Include/core_cmFunc.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
......@@ -314,7 +328,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
__ASM volatile ("cpsie i" : : : "memory");
}
......@@ -325,7 +339,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
__ASM volatile ("cpsid i" : : : "memory");
}
......@@ -352,7 +366,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
......@@ -424,7 +438,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
......@@ -451,7 +465,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
......@@ -478,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
......@@ -491,7 +505,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t p
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
__ASM volatile ("cpsie f" : : : "memory");
}
......@@ -502,7 +516,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
__ASM volatile ("cpsid f" : : : "memory");
}
......@@ -529,7 +543,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
......@@ -556,7 +570,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
......@@ -575,7 +589,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
......@@ -592,7 +609,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
......
components/CMSIS/Include/core_cmInstr.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
* @version V3.20
* @date 05. March 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
......@@ -111,12 +125,13 @@
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
......@@ -125,11 +140,13 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
......@@ -143,6 +160,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
......@@ -279,6 +307,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
......@@ -364,10 +403,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
......@@ -382,7 +425,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
......@@ -396,10 +439,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
......@@ -413,12 +460,21 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
......@@ -446,9 +502,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
uint32_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
......@@ -462,9 +525,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
uint32_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
......@@ -480,7 +550,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
......@@ -498,7 +568,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
......@@ -516,7 +586,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
......@@ -534,7 +604,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
......@@ -546,7 +616,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
__ASM volatile ("clrex" ::: "memory");
}
......@@ -591,7 +661,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
......
components/CMSIS/Include/core_sc000.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V3.01
* @date 22. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
......@@ -54,7 +69,7 @@
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
......@@ -721,9 +736,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
......@@ -771,9 +786,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
......
components/CMSIS/Include/core_sc300.h
浏览文件 @ ed2d2b0d
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
* @version V3.01
* @date 22. March 2012
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
......@@ -54,7 +69,7 @@
/* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
......@@ -607,14 +622,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
......@@ -1487,9 +1502,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
......
components/dfs/filesystems/elmfat/dfs_elm.c
浏览文件 @ ed2d2b0d
......@@ -25,6 +25,7 @@
* 2012-07-26 aozima implement ff_memalloc and ff_memfree.
* 2012-12-19 Bernard fixed the O_APPEND and lseek issue.
* 2013-03-01 aozima fixed the stat(st_mtime) issue.
* 2014-01-26 Bernard Check the sector size before mount.
*/
#include <rtthread.h>
......@@ -110,20 +111,30 @@ int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *d
FATFS *fat;
FRESULT result;
int index;
struct rt_device_blk_geometry geometry;
/* get an empty position */
index = get_disk(RT_NULL);
if (index == -1)
return -DFS_STATUS_ENOSPC;
return -DFS_STATUS_ENOENT;
/* save device */
disk[index] = fs->dev_id;
/* check sector size */
if (rt_device_control(fs->dev_id, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry) == RT_EOK)
{
if (geometry.bytes_per_sector > _MAX_SS)
{
rt_kprintf("The sector size of device is greater than the sector size of FAT.\n");
return -DFS_STATUS_EINVAL;
}
}
fat = (FATFS *)rt_malloc(sizeof(FATFS));
if (fat == RT_NULL)
{
disk[index] = RT_NULL;
return -1;
return -DFS_STATUS_ENOMEM;
}
/* mount fatfs, always 0 logic driver */
......
components/dfs/filesystems/nfs/dfs_nfs.c
浏览文件 @ ed2d2b0d
......@@ -233,7 +233,7 @@ static nfs_fh3 *get_dir_handle(struct nfs_filesystem *nfs, const char *name)
copy_handle(handle, &nfs->current_handle);
}
while ((file = strtok_r(RT_NULL, "/", &path)) != RT_NULL && path != RT_NULL)
while ((file = strtok_r(RT_NULL, "/", &path)) != RT_NULL && path[0] != 0)
{
LOOKUP3args args;
LOOKUP3res res;
......@@ -678,7 +678,9 @@ int nfs_write(struct dfs_fd *file, const void *buf, rt_size_t count)
total += bytes;
/* update current position */
file->pos = fd->offset;
/* todo: update file size */
/* update file size */
if (fd->size < fd->offset) fd->size = fd->offset;
file->size = fd->size;
}
xdr_free((xdrproc_t)xdr_WRITE3res, (char *)&res);
} while (count > 0);
......@@ -796,6 +798,7 @@ int nfs_open(struct dfs_fd *file)
/* set private file */
file->data = fp;
file->size = fp->size;
}
return 0;
......@@ -1092,8 +1095,6 @@ int nfs_getdents(struct dfs_fd *file, struct dirent *dirp, rt_uint32_t count)
index = 0;
while (1)
{
char *fn;
d = dirp + index;
name = nfs_readdir(nfs, dir);
......
components/dfs/filesystems/nfs/mount.h
浏览文件 @ ed2d2b0d
......@@ -20,7 +20,7 @@ extern "C" {
#define FHSIZE3 64
typedef struct {
u_int fhandle3_len;
unsigned int fhandle3_len;
char *fhandle3_val;
} fhandle3;
......@@ -51,7 +51,7 @@ typedef enum mountstat3 mountstat3;
struct mountres3_ok {
fhandle3 fhandle;
struct {
u_int auth_flavors_len;
unsigned int auth_flavors_len;
int *auth_flavors_val;
} auth_flavors;
};
......
components/dfs/filesystems/nfs/mount_xdr.c
浏览文件 @ ed2d2b0d
......@@ -11,14 +11,7 @@
bool_t
xdr_fhandle3(register XDR *xdrs, fhandle3 *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_bytes(xdrs, (char **)&objp->fhandle3_val, (u_int *) &objp->fhandle3_len, FHSIZE3))
if (!xdr_bytes(xdrs, (char **)&objp->fhandle3_val, (unsigned int *) &objp->fhandle3_len, FHSIZE3))
return (FALSE);
return (TRUE);
}
......@@ -26,13 +19,6 @@ xdr_fhandle3(register XDR *xdrs, fhandle3 *objp)
bool_t
xdr_dirpath(register XDR *xdrs, dirpath *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_string(xdrs, objp, MNTPATHLEN))
return (FALSE);
return (TRUE);
......@@ -41,13 +27,6 @@ xdr_dirpath(register XDR *xdrs, dirpath *objp)
bool_t
xdr_name(register XDR *xdrs, name *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_string(xdrs, objp, MNTNAMLEN))
return (FALSE);
return (TRUE);
......@@ -56,13 +35,6 @@ xdr_name(register XDR *xdrs, name *objp)
bool_t
xdr_exports(register XDR *xdrs, exports *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct exportnode), (xdrproc_t) xdr_exportnode))
return (FALSE);
return (TRUE);
......@@ -71,13 +43,6 @@ xdr_exports(register XDR *xdrs, exports *objp)
bool_t
xdr_groups(register XDR *xdrs, groups *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct groupnode), (xdrproc_t) xdr_groupnode))
return (FALSE);
return (TRUE);
......@@ -86,13 +51,6 @@ xdr_groups(register XDR *xdrs, groups *objp)
bool_t
xdr_mountlist(register XDR *xdrs, mountlist *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_pointer(xdrs, (char **)objp, sizeof (struct mountbody), (xdrproc_t) xdr_mountbody))
return (FALSE);
return (TRUE);
......@@ -103,17 +61,11 @@ xdr_mountstat3(register XDR *xdrs, mountstat3 *objp)
{
int enum_objp;
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
enum_objp = *objp;
if (!xdr_enum(xdrs, (enum_t *)&enum_objp))
{
*objp = enum_objp;
*objp = (mountstat3)enum_objp;
return (FALSE);
}
......@@ -123,16 +75,9 @@ xdr_mountstat3(register XDR *xdrs, mountstat3 *objp)
bool_t
xdr_mountres3_ok(register XDR *xdrs, mountres3_ok *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_fhandle3(xdrs, &objp->fhandle))
return (FALSE);
if (!xdr_array(xdrs, (char **)&objp->auth_flavors.auth_flavors_val, (u_int *) &objp->auth_flavors.auth_flavors_len, ~0,
if (!xdr_array(xdrs, (char **)&objp->auth_flavors.auth_flavors_val, (unsigned int *) &objp->auth_flavors.auth_flavors_len, ~0,
sizeof (int), (xdrproc_t) xdr_int))
return (FALSE);
return (TRUE);
......@@ -141,13 +86,6 @@ xdr_mountres3_ok(register XDR *xdrs, mountres3_ok *objp)
bool_t
xdr_mountres3(register XDR *xdrs, mountres3 *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_mountstat3(xdrs, &objp->fhs_status))
return (FALSE);
switch (objp->fhs_status) {
......@@ -162,13 +100,6 @@ xdr_mountres3(register XDR *xdrs, mountres3 *objp)
bool_t
xdr_mountbody(register XDR *xdrs, mountbody *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_name(xdrs, &objp->ml_hostname))
return (FALSE);
if (!xdr_dirpath(xdrs, &objp->ml_directory))
......@@ -181,13 +112,6 @@ xdr_mountbody(register XDR *xdrs, mountbody *objp)
bool_t
xdr_groupnode(register XDR *xdrs, groupnode *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_name(xdrs, &objp->gr_name))
return (FALSE);
if (!xdr_groups(xdrs, &objp->gr_next))
......@@ -198,13 +122,6 @@ xdr_groupnode(register XDR *xdrs, groupnode *objp)
bool_t
xdr_exportnode(register XDR *xdrs, exportnode *objp)
{
#if defined(_LP64) || defined(_KERNEL)
register int *buf;
#else
register long *buf;
#endif
if (!xdr_dirpath(xdrs, &objp->ex_dir))
return (FALSE);
if (!xdr_groups(xdrs, &objp->ex_groups))
......
components/dfs/filesystems/nfs/nfs.h
浏览文件 @ ed2d2b0d
......@@ -130,7 +130,7 @@ typedef struct specdata3 specdata3;
struct nfs_fh3 {
struct {
u_int data_len;
unsigned int data_len;
char *data_val;
} data;
};
......@@ -408,7 +408,7 @@ struct READ3resok {
count3 count;
bool_t eof;
struct {
u_int data_len;
unsigned int data_len;
char *data_val;
} data;
};
......@@ -434,7 +434,7 @@ struct WRITE3args {
count3 count;
stable_how stable;
struct {
u_int data_len;
unsigned int data_len;
char *data_val;
} data;
};
......
components/dfs/filesystems/nfs/nfs_xdr.c
浏览文件 @ ed2d2b0d
......@@ -151,7 +151,7 @@ xdr_nfsstat3(register XDR *xdrs, nfsstat3 *objp)
enum_objp = *objp;
if (!xdr_enum(xdrs, (enum_t *)objp))
{
*objp = enum_objp;
*objp = (nfsstat3)enum_objp;
return (FALSE);
}
......@@ -165,7 +165,7 @@ xdr_ftype3(register XDR *xdrs, ftype3 *objp)
enum_objp = *objp;
if (!xdr_enum(xdrs, (enum_t *)objp))
{
*objp = enum_objp;
*objp = (ftype3)enum_objp;
return (FALSE);
}
......@@ -179,7 +179,7 @@ xdr_stable_how(register XDR *xdrs, stable_how *objp)
enum_objp = *objp;
if (!xdr_enum(xdrs, (enum_t *)objp))
{
*objp = enum_objp;
*objp = (stable_how)enum_objp;
return (FALSE);
}
......@@ -193,7 +193,7 @@ xdr_createmode3(register XDR *xdrs, createmode3 *objp)
enum_objp = *objp;
if (!xdr_enum(xdrs, (enum_t *)objp))
{
*objp = enum_objp;
*objp = (createmode3)enum_objp;
return (FALSE);
}
......@@ -213,7 +213,7 @@ xdr_specdata3(register XDR *xdrs, specdata3 *objp)
bool_t
xdr_nfs_fh3(register XDR *xdrs, nfs_fh3 *objp)
{
if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (u_int *) &objp->data.data_len, NFS3_FHSIZE))
if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, NFS3_FHSIZE))
return (FALSE);
return (TRUE);
}
......@@ -343,7 +343,7 @@ xdr_time_how(register XDR *xdrs, time_how *objp)
enum_objp = *objp;
if (!xdr_enum(xdrs, (enum_t *)objp))
{
*objp = enum_objp;
*objp = (time_how)enum_objp;
return (FALSE);
}
......@@ -713,7 +713,7 @@ xdr_READ3resok(register XDR *xdrs, READ3resok *objp)
return (FALSE);
if (!xdr_bool(xdrs, &objp->eof))
return (FALSE);
if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (u_int *) &objp->data.data_len, ~0))
if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, ~0))
return (FALSE);
return (TRUE);
}
......@@ -755,7 +755,7 @@ xdr_WRITE3args(register XDR *xdrs, WRITE3args *objp)
return (FALSE);
if (!xdr_stable_how(xdrs, &objp->stable))
return (FALSE);
if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (u_int *) &objp->data.data_len, ~0))
if (!xdr_bytes(xdrs, (char **)&objp->data.data_val, (unsigned int *) &objp->data.data_len, ~0))
return (FALSE);
return (TRUE);
}
......
components/dfs/filesystems/nfs/rpc/auth_none.c
浏览文件 @ ed2d2b0d
......@@ -73,6 +73,7 @@ AUTH *authnone_create()
register struct authnone_private *ap = authnone_private;
XDR xdr_stream;
register XDR *xdrs;
extern bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap);
if (ap == 0) {
ap = (struct authnone_private *) rt_malloc (sizeof(*ap));
......@@ -95,9 +96,7 @@ AUTH *authnone_create()
}
/*ARGSUSED*/
static bool_t authnone_marshal(client, xdrs)
AUTH *client;
XDR *xdrs;
static bool_t authnone_marshal(AUTH *client, XDR *xdrs)
{
register struct authnone_private *ap = authnone_private;
......
components/dfs/filesystems/nfs/rpc/clnt_udp.c
浏览文件 @ ed2d2b0d
......@@ -135,6 +135,10 @@ CLIENT *clntudp_bufcreate(struct sockaddr_in *raddr,
if (raddr->sin_port == 0) {
unsigned short port;
extern unsigned short pmap_getport(struct sockaddr_in *address,
unsigned long program,
unsigned long version,
unsigned int protocol);
if ((port =
pmap_getport(raddr, program, version, IPPROTO_UDP)) == 0) {
......@@ -165,8 +169,6 @@ CLIENT *clntudp_bufcreate(struct sockaddr_in *raddr,
cu->cu_xdrpos = XDR_GETPOS(&(cu->cu_outxdrs));
if (*sockp < 0)
{
int dontblock = 1;
*sockp = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
if (*sockp < 0)
{
......@@ -229,7 +231,10 @@ call_again:
if ((!XDR_PUTLONG(xdrs, (long *) &proc)) ||
(!AUTH_MARSHALL(cl->cl_auth, xdrs)) || (!(*xargs) (xdrs, argsp)))
return (cu->cu_error.re_status = RPC_CANTENCODEARGS);
{
cu->cu_error.re_status = RPC_CANTENCODEARGS;
return RPC_CANTENCODEARGS;
}
outlen = (int) XDR_GETPOS(xdrs);
send_again:
......@@ -238,7 +243,9 @@ send_again:
!= outlen)
{
cu->cu_error.re_errno = errno;
return (cu->cu_error.re_status = RPC_CANTSEND);
cu->cu_error.re_status = RPC_CANTSEND;
return RPC_CANTSEND;
}
/*
......@@ -264,7 +271,9 @@ send_again:
{
rt_kprintf("recv error, len %d\n", inlen);
cu->cu_error.re_errno = errno;
return (cu->cu_error.re_status = RPC_CANTRECV);
cu->cu_error.re_status = RPC_CANTRECV;
return RPC_CANTRECV;
}
/* see if reply transaction id matches sent id */
......@@ -292,6 +301,8 @@ send_again:
}
if (reply_msg.acpted_rply.ar_verf.oa_base != NULL)
{
extern bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap);
xdrs->x_op = XDR_FREE;
(void) xdr_opaque_auth(xdrs, &(reply_msg.acpted_rply.ar_verf));
}
......@@ -311,7 +322,7 @@ send_again:
cu->cu_error.re_status = RPC_CANTDECODERES;
}
return (cu->cu_error.re_status);
return (enum clnt_stat)(cu->cu_error.re_status);
}
static void clntudp_geterr(CLIENT *cl, struct rpc_err *errp)
......
components/dfs/filesystems/nfs/rpc/pmap.c
浏览文件 @ ed2d2b0d
......@@ -6,9 +6,7 @@ static struct timeval timeout = { 5, 0 };
static struct timeval tottimeout = { 60, 0 };
bool_t xdr_pmap(xdrs, regs)
XDR *xdrs;
struct pmap *regs;
bool_t xdr_pmap(XDR *xdrs, struct pmap *regs)
{
if (xdr_u_long(xdrs, &regs->pm_prog) &&
xdr_u_long(xdrs, &regs->pm_vers) &&
......@@ -22,11 +20,7 @@ struct pmap *regs;
* Calls the pmap service remotely to do the lookup.
* Returns 0 if no map exists.
*/
unsigned short pmap_getport(address, program, version, protocol)
struct sockaddr_in *address;
unsigned long program;
unsigned long version;
unsigned int protocol;
unsigned short pmap_getport(struct sockaddr_in *address, unsigned long program, unsigned long version, unsigned int protocol)
{
unsigned short port = 0;
int socket = -1;
......
components/dfs/filesystems/nfs/rpc/rpc_prot.c
浏览文件 @ ed2d2b0d
......@@ -52,9 +52,7 @@ static char sccsid[] = "@(#)rpc_prot.c 1.36 87/08/11 Copyr 1984 Sun Micro";
* XDR an opaque authentication struct
* (see auth.h)
*/
bool_t xdr_opaque_auth(xdrs, ap)
register XDR *xdrs;
register struct opaque_auth *ap;
bool_t xdr_opaque_auth(XDR *xdrs, struct opaque_auth *ap)
{
if (xdr_enum(xdrs, &(ap->oa_flavor)))
......@@ -66,9 +64,7 @@ register struct opaque_auth *ap;
/*
* XDR a DES block
*/
bool_t xdr_des_block(xdrs, blkp)
register XDR *xdrs;
register des_block *blkp;
bool_t xdr_des_block(XDR *xdrs, des_block *blkp)
{
return (xdr_opaque(xdrs, (char*) blkp, sizeof(des_block)));
}
......@@ -78,9 +74,7 @@ register des_block *blkp;
/*
* XDR the MSG_ACCEPTED part of a reply message union
*/
static bool_t xdr_accepted_reply(xdrs, ar)
register XDR *xdrs;
register struct accepted_reply *ar;
static bool_t xdr_accepted_reply(XDR *xdrs, struct accepted_reply *ar)
{
/* personalized union, rather than calling xdr_union */
......@@ -104,9 +98,7 @@ register struct accepted_reply *ar;
/*
* XDR the MSG_DENIED part of a reply message union
*/
static bool_t xdr_rejected_reply(xdrs, rr)
register XDR *xdrs;
register struct rejected_reply *rr;
static bool_t xdr_rejected_reply(XDR *xdrs, struct rejected_reply *rr)
{
/* personalized union, rather than calling xdr_union */
......@@ -134,9 +126,7 @@ static struct xdr_discrim reply_dscrm[3] = {
/*
* XDR a reply message
*/
bool_t xdr_replymsg(xdrs, rmsg)
register XDR *xdrs;
register struct rpc_msg *rmsg;
bool_t xdr_replymsg(XDR *xdrs, struct rpc_msg *rmsg)
{
if (xdr_u_long(xdrs, &(rmsg->rm_xid)) &&
xdr_enum(xdrs, (enum_t *) & (rmsg->rm_direction)) &&
......@@ -153,9 +143,7 @@ register struct rpc_msg *rmsg;
* The fields include: rm_xid, rm_direction, rpcvers, prog, and vers.
* The rm_xid is not really static, but the user can easily munge on the fly.
*/
bool_t xdr_callhdr(xdrs, cmsg)
register XDR *xdrs;
register struct rpc_msg *cmsg;
bool_t xdr_callhdr(XDR *xdrs, struct rpc_msg *cmsg)
{
cmsg->rm_direction = CALL;
......@@ -172,9 +160,7 @@ register struct rpc_msg *cmsg;
/* ************************** Client utility routine ************* */
static void accepted(acpt_stat, error)
register enum accept_stat acpt_stat;
register struct rpc_err *error;
static void accepted(enum accept_stat acpt_stat, struct rpc_err *error)
{
switch (acpt_stat) {
......@@ -209,9 +195,7 @@ register struct rpc_err *error;
error->re_lb.s2 = (long) acpt_stat;
}
static void rejected(rjct_stat, error)
register enum reject_stat rjct_stat;
register struct rpc_err *error;
static void rejected(enum reject_stat rjct_stat, struct rpc_err *error)
{
switch (rjct_stat) {
......@@ -233,9 +217,7 @@ register struct rpc_err *error;
/*
* given a reply message, fills in the error
*/
void _seterr_reply(msg, error)
register struct rpc_msg *msg;
register struct rpc_err *error;
void _seterr_reply(struct rpc_msg *msg, struct rpc_err *error)
{
/* optimized for normal, SUCCESSful case */
......@@ -246,11 +228,11 @@ register struct rpc_err *error;
error->re_status = RPC_SUCCESS;
return;
};
accepted(msg->acpted_rply.ar_stat, error);
accepted((enum accept_stat)msg->acpted_rply.ar_stat, error);
break;
case MSG_DENIED:
rejected(msg->rjcted_rply.rj_stat, error);
rejected((enum reject_stat)msg->rjcted_rply.rj_stat, error);
break;
default:
......
components/dfs/filesystems/nfs/rpc/xdr.c
浏览文件 @ ed2d2b0d
......@@ -50,8 +50,8 @@ static char sccsid[] = "@(#)xdr.c 1.35 87/08/12";
/*
* constants specific to the xdr "protocol"
*/
#define XDR_FALSE ((long) 0)
#define XDR_TRUE ((long) 1)
#define XDR_FALSE ((long) 0)
#define XDR_TRUE ((long) 1)
#define LASTUNSIGNED ((unsigned int) 0-1)
/*
......@@ -327,9 +327,7 @@ bool_t xdr_u_char(XDR* xdrs, unsigned char* cp)
/*
* XDR booleans
*/
bool_t xdr_bool(xdrs, bp)
register XDR *xdrs;
bool_t *bp;
bool_t xdr_bool(XDR *xdrs, bool_t *bp)
{
long lb;
......@@ -355,9 +353,7 @@ bool_t *bp;
/*
* XDR enumerations
*/
bool_t xdr_enum(xdrs, ep)
XDR *xdrs;
enum_t *ep;
bool_t xdr_enum(XDR *xdrs, enum_t *ep)
{
/*
* enums are treated as ints
......@@ -370,10 +366,7 @@ enum_t *ep;
* Allows the specification of a fixed size sequence of opaque bytes.
* cp points to the opaque object and cnt gives the byte length.
*/
bool_t xdr_opaque(xdrs, cp, cnt)
register XDR *xdrs;
char* cp;
register unsigned int cnt;
bool_t xdr_opaque(XDR *xdrs, char* cp, unsigned int cnt)
{
register unsigned int rndup;
static char crud[BYTES_PER_XDR_UNIT];
......@@ -421,11 +414,7 @@ register unsigned int cnt;
* *cpp is a pointer to the bytes, *sizep is the count.
* If *cpp is NULL maxsize bytes are allocated
*/
bool_t xdr_bytes(xdrs, cpp, sizep, maxsize)
register XDR *xdrs;
char **cpp;
register unsigned int *sizep;
unsigned int maxsize;
bool_t xdr_bytes(XDR *xdrs, char** cpp, unsigned int *sizep, unsigned int maxsize)
{
register char *sp = *cpp; /* sp is the actual string pointer */
register unsigned int nodesize;
......@@ -475,11 +464,8 @@ unsigned int maxsize;
/*
* Implemented here due to commonality of the object.
*/
bool_t xdr_netobj(xdrs, np)
XDR *xdrs;
struct netobj *np;
bool_t xdr_netobj(XDR *xdrs, struct netobj *np)
{
return (xdr_bytes(xdrs, &np->n_bytes, &np->n_len, MAX_NETOBJ_SZ));
}
......@@ -537,10 +523,7 @@ bool_t xdr_union(XDR* xdrs, enum_t* dscmp, char* unp, const struct xdr_discrim*
* storage is allocated. The last parameter is the max allowed length
* of the string as specified by a protocol.
*/
bool_t xdr_string(xdrs, cpp, maxsize)
register XDR *xdrs;
char **cpp;
unsigned int maxsize;
bool_t xdr_string(XDR *xdrs, char **cpp, unsigned int maxsize)
{
register char *sp = *cpp; /* sp is the actual string pointer */
unsigned int size;
......@@ -600,9 +583,7 @@ unsigned int maxsize;
* Wrapper for xdr_string that can be called directly from
* routines like clnt_call
*/
bool_t xdr_wrapstring(xdrs, cpp)
XDR *xdrs;
char **cpp;
bool_t xdr_wrapstring(XDR *xdrs, char **cpp)
{
if (xdr_string(xdrs, cpp, LASTUNSIGNED)) {
return (TRUE);
......@@ -617,13 +598,7 @@ char **cpp;
* elsize is the size (in bytes) of each element, and elproc is the
* xdr procedure to call to handle each element of the array.
*/
bool_t xdr_array(xdrs, addrp, sizep, maxsize, elsize, elproc)
register XDR *xdrs;
char* *addrp; /* array pointer */
unsigned int *sizep; /* number of elements */
unsigned int maxsize; /* max numberof elements */
unsigned int elsize; /* size in bytes of each element */
xdrproc_t elproc; /* xdr routine to handle each element */
bool_t xdr_array(XDR *xdrs, char **addrp, unsigned int *sizep, unsigned int maxsize, unsigned int elsize, xdrproc_t elproc)
{
register unsigned int i;
register char* target = *addrp;
......@@ -700,12 +675,7 @@ xdrproc_t elproc; /* xdr routine to handle each element */
* > elemsize: size of each element
* > xdr_elem: routine to XDR each element
*/
bool_t xdr_vector(xdrs, basep, nelem, elemsize, xdr_elem)
register XDR *xdrs;
register char *basep;
register unsigned int nelem;
register unsigned int elemsize;
register xdrproc_t xdr_elem;
bool_t xdr_vector(XDR *xdrs, char *basep, unsigned int nelem, unsigned int elemsize, xdrproc_t xdr_elem)
{
register unsigned int i;
register char *elptr;
......@@ -730,11 +700,7 @@ register xdrproc_t xdr_elem;
* size is the sizeof the referneced structure.
* proc is the routine to handle the referenced structure.
*/
bool_t xdr_reference(xdrs, pp, size, proc)
register XDR *xdrs;
char* *pp; /* the pointer to work on */
unsigned int size; /* size of the object pointed to */
xdrproc_t proc; /* xdr routine to handle the object */
bool_t xdr_reference(XDR *xdrs, char **pp, unsigned int size, xdrproc_t proc)
{
register char* loc = *pp;
register bool_t stat;
......@@ -783,11 +749,7 @@ xdrproc_t proc; /* xdr routine to handle the object */
* > xdr_obj: routine to XDR an object.
*
*/
bool_t xdr_pointer(xdrs, objpp, obj_size, xdr_obj)
register XDR *xdrs;
char **objpp;
unsigned int obj_size;
xdrproc_t xdr_obj;
bool_t xdr_pointer(XDR *xdrs, char **objpp, unsigned int obj_size, xdrproc_t xdr_obj)
{
bool_t more_data;
......
components/dfs/filesystems/nfs/rpc/xdr_mem.c
浏览文件 @ ed2d2b0d
......@@ -135,9 +135,7 @@ static unsigned int xdrmem_getpos (const XDR *xdrs)
return ((unsigned long) xdrs->x_private - (unsigned long) xdrs->x_base);
}
static bool_t xdrmem_setpos(xdrs, pos)
register XDR *xdrs;
unsigned int pos;
static bool_t xdrmem_setpos(XDR *xdrs, unsigned int pos)
{
register char* newaddr = xdrs->x_base + pos;
register char* lastaddr = xdrs->x_private + xdrs->x_handy;
......
components/dfs/filesystems/ramfs/dfs_ramfs.c
浏览文件 @ ed2d2b0d
......@@ -414,6 +414,7 @@ int dfs_ramfs_init(void)
return 0;
}
INIT_FS_EXPORT(dfs_ramfs_init);
struct dfs_ramfs* dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size)
{
......
components/dfs/filesystems/romfs/mkromfs.py
浏览文件 @ ed2d2b0d
......@@ -4,6 +4,7 @@ import string
basename = ''
output = ''
sep = os.sep
def mkromfs_output(out):
# print '%s' % out,
......@@ -54,12 +55,12 @@ def mkromfs_dir(dirname, is_root = False):
fullpath = os.path.join(path, item)
if os.path.isfile(fullpath):
subpath = fullpath[len(basename):]
array = subpath.split('\\')
array = subpath.split(sep)
arrayname = string.join(array, '_')
mkromfs_file(fullpath, arrayname)
subpath = path[len(basename):]
dir = subpath.split('\\')
dir = subpath.split(sep)
direntname = string.join(dir, '_')
if is_root:
mkromfs_output('const struct romfs_dirent _root_dirent[] = {\n')
......@@ -69,12 +70,12 @@ def mkromfs_dir(dirname, is_root = False):
for item in list:
fullpath = os.path.join(path, item)
fn = fullpath[len(dirname):]
if fn[0] == '\\':
if fn[0] == sep:
fn = fn[1:]
fn = fn.replace('\\', '/')
subpath = fullpath[len(basename):]
items = subpath.split('\\')
items = subpath.split(sep)
item_name = string.join(items, '_')
item_name = item_name.replace('.', '_')
item_name = item_name.replace('-', '_')
......@@ -92,12 +93,12 @@ def mkromfs_dir(dirname, is_root = False):
for item in list:
fullpath = os.path.join(path, item)
fn = fullpath[len(dirname):]
if fn[0] == '\\':
if fn[0] == sep:
fn = fn[1:]
fn = fn.replace('\\', '/')
subpath = fullpath[len(basename):]
items = subpath.split('\\')
items = subpath.split(sep)
item_name = string.join(items, '_')
item_name = item_name.replace('.', '_')
item_name = item_name.replace('-', '_')
......
components/dfs/src/dfs_file.c
浏览文件 @ ed2d2b0d
......@@ -593,7 +593,7 @@ void cat(const char* filename)
FINSH_FUNCTION_EXPORT(cat, print file)
#define BUF_SZ 4096
void copy(const char *src, const char *dst)
static void copyfile(const char *src, const char *dst)
{
struct dfs_fd src_fd;
rt_uint8_t *block_ptr;
......@@ -637,7 +637,171 @@ void copy(const char *src, const char *dst)
dfs_file_close(&fd);
rt_free(block_ptr);
}
FINSH_FUNCTION_EXPORT(copy, copy source file to destination file)
extern int mkdir(const char *path, mode_t mode);
static void copydir(const char * src, const char * dst)
{
struct dfs_fd fd;
struct dirent dirent;
struct stat stat;
int length;
if (dfs_file_open(&fd, src, DFS_O_DIRECTORY) < 0)
{
rt_kprintf("open %s failed\n", src);
return ;
}
do
{
rt_memset(&dirent, 0, sizeof(struct dirent));
length = dfs_file_getdents(&fd, &dirent, sizeof(struct dirent));
if (length > 0)
{
char * src_entry_full = RT_NULL;
char * dst_entry_full = RT_NULL;
if (strcmp(dirent.d_name, "..") == 0 || strcmp(dirent.d_name, ".") == 0)
continue;
/* build full path for each file */
if ((src_entry_full = dfs_normalize_path(src, dirent.d_name)) == RT_NULL)
{
rt_kprintf("out of memory!\n");
break;
}
if ((dst_entry_full = dfs_normalize_path(dst, dirent.d_name)) == RT_NULL)
{
rt_kprintf("out of memory!\n");
rt_free(src_entry_full);
break;
}
rt_memset(&stat, 0, sizeof(struct stat));
if (dfs_file_stat(src_entry_full, &stat) != 0)
{
rt_kprintf("open file: %s failed\n", dirent.d_name);
continue;
}
if (DFS_S_ISDIR(stat.st_mode))
{
mkdir(dst_entry_full, 0);
copydir(src_entry_full, dst_entry_full);
}
else
{
copyfile(src_entry_full, dst_entry_full);
}
rt_free(src_entry_full);
rt_free(dst_entry_full);
}
}while(length > 0);
dfs_file_close(&fd);
}
static const char *_get_path_lastname(const char *path)
{
char * ptr;
if ((ptr = strrchr(path, '/')) == RT_NULL)
return path;
/* skip the '/' then return */
return ++ptr;
}
void copy(const char *src, const char *dst)
{
#define FLAG_SRC_TYPE 0x03
#define FLAG_SRC_IS_DIR 0x01
#define FLAG_SRC_IS_FILE 0x02
#define FLAG_SRC_NON_EXSIT 0x00
#define FLAG_DST_TYPE 0x0C
#define FLAG_DST_IS_DIR 0x04
#define FLAG_DST_IS_FILE 0x08
#define FLAG_DST_NON_EXSIT 0x00
struct stat stat;
rt_uint32_t flag = 0;
/* check the staus of src and dst */
if (dfs_file_stat(src, &stat) < 0)
{
rt_kprintf("copy failed, bad %s\n", src);
return;
}
if (DFS_S_ISDIR(stat.st_mode))
flag |= FLAG_SRC_IS_DIR;
else
flag |= FLAG_SRC_IS_FILE;
if (dfs_file_stat(dst, &stat) < 0)
{
flag |= FLAG_DST_NON_EXSIT;
}
else
{
if (DFS_S_ISDIR(stat.st_mode))
flag |= FLAG_DST_IS_DIR;
else
flag |= FLAG_DST_IS_FILE;
}
//2. check status
if ((flag & FLAG_SRC_IS_DIR) && (flag & FLAG_DST_IS_FILE))
{
rt_kprintf("cp faild, cp dir to file is not permitted!\n");
return ;
}
//3. do copy
if (flag & FLAG_SRC_IS_FILE)
{
if (flag & FLAG_DST_IS_DIR)
{
char * fdst;
fdst = dfs_normalize_path(dst, _get_path_lastname(src));
if (fdst == NULL)
{
rt_kprintf("out of memory\n");
return;
}
copyfile(src, fdst);
rt_free(fdst);
}
else
{
copyfile(src, dst);
}
}
else //flag & FLAG_SRC_IS_DIR
{
if (flag & FLAG_DST_IS_DIR)
{
char * fdst;
fdst = dfs_normalize_path(dst, _get_path_lastname(src));
if (fdst == NULL)
{
rt_kprintf("out of memory\n");
return;
}
mkdir(fdst, 0);
copydir(src, fdst);
rt_free(fdst);
}
else if ((flag & FLAG_DST_TYPE) == FLAG_DST_NON_EXSIT)
{
mkdir(dst, 0);
copydir(src, dst);
}
else
{
copydir(src, dst);
}
}
}
FINSH_FUNCTION_EXPORT(copy, copy file or dir)
#endif
/* @} */
......
components/drivers/serial/serial.c
浏览文件 @ ed2d2b0d
......@@ -368,20 +368,25 @@ static rt_err_t rt_serial_control(struct rt_device *dev,
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_RESUME:
/* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_CONFIG:
/* configure device */
serial->ops->configure(serial, (struct serial_configure *)args);
break;
case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_RESUME:
/* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
break;
case RT_DEVICE_CTRL_CONFIG:
/* configure device */
serial->ops->configure(serial, (struct serial_configure *)args);
break;
default :
/* control device */
serial->ops->control(serial, cmd, args);
break;
}
return RT_EOK;
......
components/finsh/cmd.c
浏览文件 @ ed2d2b0d
......@@ -516,8 +516,8 @@ int list_module(void)
return 0;
}
FINSH_FUNCTION_EXPORT(list_module, list module in system)
FINSH_FUNCTION_EXPORT(list_module, list module in system);
MSH_CMD_EXPORT(list_module, list module in system);
int list_mod_detail(const char *name)
{
......@@ -536,7 +536,7 @@ int list_mod_detail(const char *name)
/* list main thread in module */
if (module->module_thread != RT_NULL)
{
{
rt_kprintf("main thread pri status sp stack size max used left tick error\n");
rt_kprintf("------------- ---- ------- ---------- ---------- ---------- ---------- ---\n");
thread = module->module_thread;
......@@ -555,7 +555,7 @@ int list_mod_detail(const char *name)
thread->stack_size - ((rt_uint32_t) ptr - (rt_uint32_t)thread->stack_addr),
thread->remaining_tick,
thread->error);
}
}
/* list sub thread in module */
tlist = &module->module_object[RT_Object_Class_Thread].object_list;
......@@ -605,20 +605,24 @@ int list_mod_detail(const char *name)
if (!rt_list_isempty(tlist)) _list_timer(tlist);
}
rt_kprintf("symbol address \n");
rt_kprintf("-------- ----------\n");
/* list module export symbols */
for (i=0; i<module->nsym; i++)
{
rt_kprintf("%s 0x%x\n",
module->symtab[i].name, module->symtab[i].addr);
}
if (module->nsym > 0)
{
rt_kprintf("symbol address \n");
rt_kprintf("-------- ----------\n");
/* list module export symbols */
for (i=0; i<module->nsym; i++)
{
rt_kprintf("%s 0x%x\n",
module->symtab[i].name, module->symtab[i].addr);
}
}
}
return 0;
}
FINSH_FUNCTION_EXPORT(list_mod_detail, list module objects in system)
MSH_CMD_EXPORT(list_mod_detail, list module objects in system)
#endif
long list(void)
......
components/finsh/msh.c
浏览文件 @ ed2d2b0d
此差异已折叠。
components/finsh/msh_cmd.c
浏览文件 @ ed2d2b0d
......@@ -179,6 +179,18 @@ FINSH_FUNCTION_EXPORT_ALIAS(cmd_mkdir, __cmd_mkdir, Create the DIRECTORY.);
#endif
#ifdef RT_USING_LWIP
int cmd_ifconfig(int argc, char** argv)
{
extern void list_if(void);
list_if();
return 0;
}
FINSH_FUNCTION_EXPORT_ALIAS(cmd_ifconfig, __cmd_ifconfig, list the information of network interfaces);
#endif
int cmd_ps(int argc, char** argv)
{
extern long list_thread(void);
......
components/finsh/shell.c
浏览文件 @ ed2d2b0d
......@@ -58,11 +58,18 @@ struct finsh_shell* shell;
#include <dfs_posix.h>
const char* finsh_get_prompt()
{
#define _PROMPT "finsh "
static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {_PROMPT};
#define _MSH_PROMPT "msh "
#define _PROMPT "finsh "
static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {0};
#ifdef FINSH_USING_MSH
if (msh_is_used()) strcpy(finsh_prompt, _MSH_PROMPT);
else
#endif
strcpy(finsh_prompt, _PROMPT);
/* get current working directory */
getcwd(&finsh_prompt[6], RT_CONSOLEBUF_SIZE - 8);
getcwd(&finsh_prompt[rt_strlen(finsh_prompt)], RT_CONSOLEBUF_SIZE - rt_strlen(finsh_prompt));
strcat(finsh_prompt, ">");
return finsh_prompt;
......
components/init/components.c
浏览文件 @ ed2d2b0d
......@@ -148,6 +148,10 @@ void rt_components_init(void)
dfs_romfs_init();
#endif
#ifdef RT_USING_DFS_RAMFS
dfs_ramfs_init();
#endif
#ifdef RT_USING_DFS_DEVFS
devfs_init();
#endif
......
components/net/lwip-1.4.1/src/arch/sys_arch.c
浏览文件 @ ed2d2b0d
......@@ -622,6 +622,14 @@ RTM_EXPORT(lwip_select);
RTM_EXPORT(lwip_ioctl);
RTM_EXPORT(lwip_fcntl);
RTM_EXPORT(lwip_htons);
RTM_EXPORT(lwip_ntohs);
RTM_EXPORT(lwip_htonl);
RTM_EXPORT(lwip_ntohl);
RTM_EXPORT(ipaddr_aton);
RTM_EXPORT(ipaddr_ntoa);
#if LWIP_DNS
#include <lwip/netdb.h>
RTM_EXPORT(lwip_gethostbyname);
......
components/pthreads/posix_types.h
浏览文件 @ ed2d2b0d
此差异已折叠。
components/pthreads/pthread.c
浏览文件 @ ed2d2b0d
......@@ -347,13 +347,13 @@ RTM_EXPORT(pthread_once);
int pthread_atfork(void (*prepare)(void), void (*parent)(void), void (*child)(void))
{
return ENOTSUP;
return EOPNOTSUPP;
}
RTM_EXPORT(pthread_atfork);
int pthread_kill(pthread_t thread, int sig)
{
return ENOTSUP;
return EOPNOTSUPP;
}
RTM_EXPORT(pthread_kill);
......
components/pthreads/pthread_attr.c
浏览文件 @ ed2d2b0d
此差异已折叠。
components/pthreads/sched.c
浏览文件 @ ed2d2b0d
......@@ -51,6 +51,6 @@ RTM_EXPORT(sched_get_priority_max);
int sched_setscheduler(pid_t pid, int policy)
{
return ENOTSUP;
return EOPNOTSUPP;
}
RTM_EXPORT(sched_setscheduler);
include/rtdebug.h
浏览文件 @ ed2d2b0d
......@@ -64,7 +64,7 @@
#endif
#ifndef RT_DEBUG_INIT
#define RT_DEBUG_INIT 0
#define RT_DEBUG_INIT 0
#endif
/* Turn on this to enable context check */
......
include/rtdef.h
浏览文件 @ ed2d2b0d
此差异已折叠。
include/rtthread.h
浏览文件 @ ed2d2b0d
此差异已折叠。
libcpu/arm/am335x/am33xx.h
浏览文件 @ ed2d2b0d
此差异已折叠。
src/module.c
浏览文件 @ ed2d2b0d
此差异已折叠。
src/thread.c
浏览文件 @ ed2d2b0d
此差异已折叠。
tools/building.py
浏览文件 @ ed2d2b0d
此差异已折叠。
tools/ua.py 0 → 100644
浏览文件 @ ed2d2b0d
此差异已折叠。
tools/wizard.py 100644 → 100755
浏览文件 @ ed2d2b0d
文件模式从 100644 更改为 100755
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