• S
    component: sdio: fix potential ricky clock setting · 4c7106fa
    Shawn Lin 提交于
    Currently RTT mmc stack only support Highspeed mode or
    blow, which means the max speed should be 52MHz according
    to JEDEC spec. Two problems show here:
    
    (1) max_data_rate = (unsigned int)-1. The value of unsigned int
    depends on compilers/arch. Moreover, it makes no sense to assume
    cpu addressing width with IP clock rate limit.
    (1)hs_max_data_rate was set to 200MHz.
    
    So what should BSP drivers do if 52MHz < max_data_rate < 200MHz?
    Either it blindly sets a spec-violated clock rate to drive a Highspeed
    card, or just adjust the clock rate internally. Both cases are
    really bad for practice.
    
    If the card claims to support Highspeed, we set the clock to not
    to exceed 52MHz. Otherwise it should be set according to
    card->max_data_rate parsed by ext_csd. This patch fixes it as-is,
    and also simplify the code a lot.
    Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
    4c7106fa
mmc.c 16.1 KB