add stm32sky bsp.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@12 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm32sky001/application.c

+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+#include <rtthread.h>
+
+int rt_application_init()
+{
+	return 0;
+}
+
+/*@}*/

bsp/stm32sky001/board.c

+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-23     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "stm32f10x_lib.h"
+
+static void rt_hw_console_init(void);
+
+/**
+ * @addtogroup STM32SKY
+ */
+
+/*@{*/
+
+ErrorStatus HSEStartUpStatus;
+
+/*******************************************************************************
+ * Function Name  : RCC_Configuration
+ * Description    : Configures the different system clocks.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void RCC_Configuration(void)
+{
+	/* RCC system reset(for debug purpose) */
+	RCC_DeInit();
+
+	/* Enable HSE */
+	RCC_HSEConfig(RCC_HSE_ON);
+
+	/* Wait till HSE is ready */
+	HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+	if(HSEStartUpStatus == SUCCESS)
+	{
+		/* HCLK = SYSCLK */
+		RCC_HCLKConfig(RCC_SYSCLK_Div1);
+
+		/* PCLK2 = HCLK */
+		RCC_PCLK2Config(RCC_HCLK_Div1);
+		/* PCLK1 = HCLK/2 */
+		RCC_PCLK1Config(RCC_HCLK_Div2);
+
+		/* Flash 2 wait state */
+		FLASH_SetLatency(FLASH_Latency_2);
+		/* Enable Prefetch Buffer */
+		FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
+
+		/* PLLCLK = 8MHz * 9 = 72 MHz */
+		RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+
+		/* Enable PLL */
+		RCC_PLLCmd(ENABLE);
+
+		/* Wait till PLL is ready */
+		while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
+
+		/* Select PLL as system clock source */
+		RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+		/* Wait till PLL is used as system clock source */
+		while(RCC_GetSYSCLKSource() != 0x08) ;
+	}
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+	/* Set the Vector Table base location at 0x20000000 */
+	NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else  /* VECT_TAB_FLASH  */
+	/* Set the Vector Table base location at 0x08000000 */
+	NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    rt_uint32_t         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+
+    SysTick_SetReload(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+    SysTick_CounterCmd(SysTick_Counter_Enable);
+    SysTick_ITConfig(ENABLE);
+}
+
+extern void rt_hw_interrupt_thread_switch(void);
+/**
+ * This is the timer interrupt service routine.
+ * 
+ */
+void rt_hw_timer_handler(void)
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+	
+	/* leave interrupt */
+	rt_interrupt_leave();
+	rt_hw_interrupt_thread_switch();
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+void rt_hw_board_init()
+{
+	/* Configure the system clocks */
+	RCC_Configuration();
+
+	/* NVIC Configuration */
+	NVIC_Configuration();
+	
+	/* Configure the SysTick */
+	SysTick_Configuration();
+	
+	rt_hw_console_init();
+}
+
+/* init console to support rt_kprintf */
+static void rt_hw_console_init()
+{
+	/* Enable USART1 and GPIOA clocks */
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+	/* GPIO configuration */
+	{
+	GPIO_InitTypeDef GPIO_InitStructure;
+
+	/* Configure USART1 Tx (PA.09) as alternate function push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	/* Configure USART1 Rx (PA.10) as input floating */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+	}
+
+	/* USART configuration */
+	{
+	USART_InitTypeDef USART_InitStructure;
+	
+	/* USART1 configured as follow:
+		- BaudRate = 115200 baud
+		- Word Length = 8 Bits
+		- One Stop Bit
+		- No parity
+		- Hardware flow control disabled (RTS and CTS signals)
+		- Receive and transmit enabled
+		- USART Clock disabled
+		- USART CPOL: Clock is active low
+		- USART CPHA: Data is captured on the middle
+		- USART LastBit: The clock pulse of the last data bit is not output to
+		  the SCLK pin
+	*/
+	USART_InitStructure.USART_BaudRate = 115200;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;
+	USART_InitStructure.USART_Parity = USART_Parity_No;
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+	USART_Init(USART1, &USART_InitStructure);
+	/* Enable USART1 */
+	USART_Cmd(USART1, ENABLE);
+	}
+}
+
+/* write one character to serial, must not trigger interrupt */
+static void rt_hw_console_putc(const char c)
+{
+	/*
+		to be polite with serial console add a line feed
+		to the carriage return character
+	*/
+	if (c=='\n')rt_hw_console_putc('\r');
+
+	while (!(USART1->SR & USART_FLAG_TXE));
+	USART1->DR = (c & 0x1FF);
+}
+
+/**
+ * This function is used by rt_kprintf to display a string on console.
+ * 
+ * @param str the displayed string
+ */
+void rt_hw_console_output(const char* str)
+{
+	while (*str)
+	{
+		rt_hw_console_putc (*str++);
+	}
+}
+
+/*@}*/

bsp/stm32sky001/board.h

+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-10-08     Bernard      add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+void rt_hw_board_led_on(int n);
+void rt_hw_board_led_off(int n);
+void rt_hw_board_init(void);
+
+void rt_hw_usart_init(void);
+void rt_hw_sdcard_init(void);
+
+#endif

bsp/stm32sky001/cortexm3_macro.s

+;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+;* File Name          : cortexm3_macro.s
+;* Author             : MCD Application Team
+;* Version            : V1.1
+;* Date               : 11/26/2007
+;* Description        : Instruction wrappers for special Cortex-M3 instructions.
+;*******************************************************************************
+; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+    
+  THUMB
+  REQUIRE8
+  PRESERVE8
+    
+  AREA |.text|, CODE, READONLY, ALIGN=2
+
+  ; Exported functions
+  EXPORT __WFI
+  EXPORT __WFE
+  EXPORT __SEV
+  EXPORT __ISB
+  EXPORT __DSB
+  EXPORT __DMB
+  EXPORT __SVC
+  EXPORT __MRS_CONTROL
+  EXPORT __MSR_CONTROL
+  EXPORT __MRS_PSP
+  EXPORT __MSR_PSP
+  EXPORT __MRS_MSP
+  EXPORT __MSR_MSP   
+  EXPORT __SETPRIMASK
+  EXPORT __RESETPRIMASK
+  EXPORT __SETFAULTMASK
+  EXPORT __RESETFAULTMASK
+  EXPORT __BASEPRICONFIG
+  EXPORT __GetBASEPRI
+  EXPORT __REV_HalfWord
+  EXPORT __REV_Word
+
+;*******************************************************************************
+; Function Name  : __WFI
+; Description    : Assembler function for the WFI instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__WFI 
+ 
+    WFI
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __WFE
+; Description    : Assembler function for the WFE instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__WFE
+
+    WFE
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SEV
+; Description    : Assembler function for the SEV instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__SEV
+
+    SEV
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __ISB
+; Description    : Assembler function for the ISB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__ISB
+
+    ISB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __DSB
+; Description    : Assembler function for the DSB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__DSB
+
+    DSB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __DMB
+; Description    : Assembler function for the DMB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__DMB
+
+    DMB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SVC
+; Description    : Assembler function for the SVC instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__SVC
+
+    SVC 0x01
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_CONTROL
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Cortex-M3 CONTROL register value.
+;*******************************************************************************
+__MRS_CONTROL
+
+  MRS r0, CONTROL
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_CONTROL
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Cortex-M3 CONTROL register new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_CONTROL
+
+  MSR CONTROL, r0
+  ISB
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_PSP
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Process Stack value.
+;*******************************************************************************
+__MRS_PSP
+
+  MRS r0, PSP
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_PSP
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Process Stack new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_PSP 
+ 
+    MSR PSP, r0 ; set Process Stack value
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_MSP
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Main Stack value.
+;*******************************************************************************
+__MRS_MSP
+
+  MRS r0, MSP
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_MSP
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Main Stack new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_MSP 
+ 
+    MSR MSP, r0 ; set Main Stack value
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SETPRIMASK
+; Description    : Assembler function to set the PRIMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__SETPRIMASK
+
+  CPSID i
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __RESETPRIMASK
+; Description    : Assembler function to reset the PRIMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__RESETPRIMASK
+
+  CPSIE i
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __SETFAULTMASK
+; Description    : Assembler function to set the FAULTMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__SETFAULTMASK
+
+  CPSID f
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __RESETFAULTMASK
+; Description    : Assembler function to reset the FAULTMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__RESETFAULTMASK
+
+  CPSIE f
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __BASEPRICONFIG
+; Description    : Assembler function to set the Base Priority.
+; Input          : - r0 : Base Priority new value  
+; Return         : None
+;*******************************************************************************
+__BASEPRICONFIG
+
+  MSR BASEPRI, r0
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __GetBASEPRI
+; Description    : Assembler function to get the Base Priority value.
+; Input          : None 
+; Return         : - r0 : Base Priority value 
+;*******************************************************************************
+__GetBASEPRI
+
+  MRS r0, BASEPRI_MAX
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __REV_HalfWord
+; Description    : Reverses the byte order in HalfWord(16-bit) input variable.
+; Input          : - r0 : specifies the input variable
+; Return         : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_HalfWord 
+ 
+  REV16 r0, r0
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __REV_Word
+; Description    : Reverses the byte order in Word(32-bit) input variable.
+; Input          : - r0 : specifies the input variable
+; Return         : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_Word 
+ 
+  REV r0, r0
+  BX r14
+    
+  END
+  
+;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****

bsp/stm32sky001/enc28j60.h

+#ifndef __ENC28J60_H__
+#define __ENC28J60_H__
+
+#include <rtthread.h>
+
+// ENC28J60 Control Registers
+// Control register definitions are a combination of address,
+// bank number, and Ethernet/MAC/PHY indicator bits.
+// - Register address        (bits 0-4)
+// - Bank number        (bits 5-6)
+// - MAC/PHY indicator        (bit 7)
+#define ADDR_MASK        0x1F
+#define BANK_MASK        0x60
+#define SPRD_MASK        0x80
+// All-bank registers
+#define EIE              0x1B
+#define EIR              0x1C
+#define ESTAT            0x1D
+#define ECON2            0x1E
+#define ECON1            0x1F
+// Bank 0 registers
+#define ERDPTL           (0x00|0x00)
+#define ERDPTH           (0x01|0x00)
+#define EWRPTL           (0x02|0x00)
+#define EWRPTH           (0x03|0x00)
+#define ETXSTL           (0x04|0x00)
+#define ETXSTH           (0x05|0x00)
+#define ETXNDL           (0x06|0x00)
+#define ETXNDH           (0x07|0x00)
+#define ERXSTL           (0x08|0x00)
+#define ERXSTH           (0x09|0x00)
+#define ERXNDL           (0x0A|0x00)
+#define ERXNDH           (0x0B|0x00)
+#define ERXRDPTL         (0x0C|0x00)
+#define ERXRDPTH         (0x0D|0x00)
+#define ERXWRPTL         (0x0E|0x00)
+#define ERXWRPTH         (0x0F|0x00)
+#define EDMASTL          (0x10|0x00)
+#define EDMASTH          (0x11|0x00)
+#define EDMANDL          (0x12|0x00)
+#define EDMANDH          (0x13|0x00)
+#define EDMADSTL         (0x14|0x00)
+#define EDMADSTH         (0x15|0x00)
+#define EDMACSL          (0x16|0x00)
+#define EDMACSH          (0x17|0x00)
+// Bank 1 registers
+#define EHT0             (0x00|0x20)
+#define EHT1             (0x01|0x20)
+#define EHT2             (0x02|0x20)
+#define EHT3             (0x03|0x20)
+#define EHT4             (0x04|0x20)
+#define EHT5             (0x05|0x20)
+#define EHT6             (0x06|0x20)
+#define EHT7             (0x07|0x20)
+#define EPMM0            (0x08|0x20)
+#define EPMM1            (0x09|0x20)
+#define EPMM2            (0x0A|0x20)
+#define EPMM3            (0x0B|0x20)
+#define EPMM4            (0x0C|0x20)
+#define EPMM5            (0x0D|0x20)
+#define EPMM6            (0x0E|0x20)
+#define EPMM7            (0x0F|0x20)
+#define EPMCSL           (0x10|0x20)
+#define EPMCSH           (0x11|0x20)
+#define EPMOL            (0x14|0x20)
+#define EPMOH            (0x15|0x20)
+#define EWOLIE           (0x16|0x20)
+#define EWOLIR           (0x17|0x20)
+#define ERXFCON          (0x18|0x20)
+#define EPKTCNT          (0x19|0x20)
+// Bank 2 registers
+#define MACON1           (0x00|0x40|0x80)
+#define MACON2           (0x01|0x40|0x80)
+#define MACON3           (0x02|0x40|0x80)
+#define MACON4           (0x03|0x40|0x80)
+#define MABBIPG          (0x04|0x40|0x80)
+#define MAIPGL           (0x06|0x40|0x80)
+#define MAIPGH           (0x07|0x40|0x80)
+#define MACLCON1         (0x08|0x40|0x80)
+#define MACLCON2         (0x09|0x40|0x80)
+#define MAMXFLL          (0x0A|0x40|0x80)
+#define MAMXFLH          (0x0B|0x40|0x80)
+#define MAPHSUP          (0x0D|0x40|0x80)
+#define MICON            (0x11|0x40|0x80)
+#define MICMD            (0x12|0x40|0x80)
+#define MIREGADR         (0x14|0x40|0x80)
+#define MIWRL            (0x16|0x40|0x80)
+#define MIWRH            (0x17|0x40|0x80)
+#define MIRDL            (0x18|0x40|0x80)
+#define MIRDH            (0x19|0x40|0x80)
+// Bank 3 registers
+#define MAADR1           (0x00|0x60|0x80)
+#define MAADR0           (0x01|0x60|0x80)
+#define MAADR3           (0x02|0x60|0x80)
+#define MAADR2           (0x03|0x60|0x80)
+#define MAADR5           (0x04|0x60|0x80)
+#define MAADR4           (0x05|0x60|0x80)
+#define EBSTSD           (0x06|0x60)
+#define EBSTCON          (0x07|0x60)
+#define EBSTCSL          (0x08|0x60)
+#define EBSTCSH          (0x09|0x60)
+#define MISTAT           (0x0A|0x60|0x80)
+#define EREVID           (0x12|0x60)
+#define ECOCON           (0x15|0x60)
+#define EFLOCON          (0x17|0x60)
+#define EPAUSL           (0x18|0x60)
+#define EPAUSH           (0x19|0x60)
+// PHY registers
+#define PHCON1           0x00
+#define PHSTAT1          0x01
+#define PHHID1           0x02
+#define PHHID2           0x03
+#define PHCON2           0x10
+#define PHSTAT2          0x11
+#define PHIE             0x12
+#define PHIR             0x13
+#define PHLCON           0x14
+
+// ENC28J60 ERXFCON Register Bit Definitions
+#define ERXFCON_UCEN     0x80
+#define ERXFCON_ANDOR    0x40
+#define ERXFCON_CRCEN    0x20
+#define ERXFCON_PMEN     0x10
+#define ERXFCON_MPEN     0x08
+#define ERXFCON_HTEN     0x04
+#define ERXFCON_MCEN     0x02
+#define ERXFCON_BCEN     0x01
+// ENC28J60 EIE Register Bit Definitions
+#define EIE_INTIE        0x80
+#define EIE_PKTIE        0x40
+#define EIE_DMAIE        0x20
+#define EIE_LINKIE       0x10
+#define EIE_TXIE         0x08
+#define EIE_WOLIE        0x04
+#define EIE_TXERIE       0x02
+#define EIE_RXERIE       0x01
+// ENC28J60 EIR Register Bit Definitions
+#define EIR_PKTIF        0x40
+#define EIR_DMAIF        0x20
+#define EIR_LINKIF       0x10
+#define EIR_TXIF         0x08
+#define EIR_WOLIF        0x04
+#define EIR_TXERIF       0x02
+#define EIR_RXERIF       0x01
+// ENC28J60 ESTAT Register Bit Definitions
+#define ESTAT_INT        0x80
+#define ESTAT_LATECOL    0x10
+#define ESTAT_RXBUSY     0x04
+#define ESTAT_TXABRT     0x02
+#define ESTAT_CLKRDY     0x01
+// ENC28J60 ECON2 Register Bit Definitions
+#define ECON2_AUTOINC    0x80
+#define ECON2_PKTDEC     0x40
+#define ECON2_PWRSV      0x20
+#define ECON2_VRPS       0x08
+// ENC28J60 ECON1 Register Bit Definitions
+#define ECON1_TXRST      0x80
+#define ECON1_RXRST      0x40
+#define ECON1_DMAST      0x20
+#define ECON1_CSUMEN     0x10
+#define ECON1_TXRTS      0x08
+#define ECON1_RXEN       0x04
+#define ECON1_BSEL1      0x02
+#define ECON1_BSEL0      0x01
+// ENC28J60 MACON1 Register Bit Definitions
+#define MACON1_LOOPBK    0x10
+#define MACON1_TXPAUS    0x08
+#define MACON1_RXPAUS    0x04
+#define MACON1_PASSALL   0x02
+#define MACON1_MARXEN    0x01
+// ENC28J60 MACON2 Register Bit Definitions
+#define MACON2_MARST     0x80
+#define MACON2_RNDRST    0x40
+#define MACON2_MARXRST   0x08
+#define MACON2_RFUNRST   0x04
+#define MACON2_MATXRST   0x02
+#define MACON2_TFUNRST   0x01
+// ENC28J60 MACON3 Register Bit Definitions
+#define MACON3_PADCFG2   0x80
+#define MACON3_PADCFG1   0x40
+#define MACON3_PADCFG0   0x20
+#define MACON3_TXCRCEN   0x10
+#define MACON3_PHDRLEN   0x08
+#define MACON3_HFRMLEN   0x04
+#define MACON3_FRMLNEN   0x02
+#define MACON3_FULDPX    0x01
+// ENC28J60 MACON4 Register Bit Definitions
+#define	MACON4_DEFER	(1<<6)
+#define	MACON4_BPEN		(1<<5)
+#define	MACON4_NOBKOFF	(1<<4)
+// ENC28J60 MICMD Register Bit Definitions
+#define MICMD_MIISCAN    0x02
+#define MICMD_MIIRD      0x01
+// ENC28J60 MISTAT Register Bit Definitions
+#define MISTAT_NVALID    0x04
+#define MISTAT_SCAN      0x02
+#define MISTAT_BUSY      0x01
+// ENC28J60 PHY PHCON1 Register Bit Definitions
+#define PHCON1_PRST      0x8000
+#define PHCON1_PLOOPBK   0x4000
+#define PHCON1_PPWRSV    0x0800
+#define PHCON1_PDPXMD    0x0100
+// ENC28J60 PHY PHSTAT1 Register Bit Definitions
+#define PHSTAT1_PFDPX    0x1000
+#define PHSTAT1_PHDPX    0x0800
+#define PHSTAT1_LLSTAT   0x0004
+#define PHSTAT1_JBSTAT   0x0002
+/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
+#define PHSTAT2_TXSTAT	(1 << 13)
+#define PHSTAT2_RXSTAT	(1 << 12)
+#define PHSTAT2_COLSTAT	(1 << 11)
+#define PHSTAT2_LSTAT	(1 << 10)
+#define PHSTAT2_DPXSTAT	(1 << 9)
+#define PHSTAT2_PLRITY	(1 << 5)
+// ENC28J60 PHY PHCON2 Register Bit Definitions
+#define PHCON2_FRCLINK   0x4000
+#define PHCON2_TXDIS     0x2000
+#define PHCON2_JABBER    0x0400
+#define PHCON2_HDLDIS    0x0100
+
+// ENC28J60 Packet Control Byte Bit Definitions
+#define PKTCTRL_PHUGEEN  0x08
+#define PKTCTRL_PPADEN   0x04
+#define PKTCTRL_PCRCEN   0x02
+#define PKTCTRL_POVERRIDE 0x01
+
+// SPI operation codes
+#define ENC28J60_READ_CTRL_REG       0x00
+#define ENC28J60_READ_BUF_MEM        0x3A
+#define ENC28J60_WRITE_CTRL_REG      0x40
+#define ENC28J60_WRITE_BUF_MEM       0x7A
+#define ENC28J60_BIT_FIELD_SET       0x80
+#define ENC28J60_BIT_FIELD_CLR       0xA0
+#define ENC28J60_SOFT_RESET          0xFF
+
+// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
+// buffer boundaries applied to internal 8K ram
+// the entire available packet buffer space is allocated
+//
+
+// start with recbuf at 0/
+#define RXSTART_INIT	0x0
+// receive buffer end
+#define RXSTOP_INIT		(0x1FFF-0x0600) - 1
+// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
+
+#define TXSTART_INIT	(0x1FFF-0x0600)
+// stp TX buffer at end of mem
+#define TXSTOP_INIT		0x1FFF
+
+// max frame length which the conroller will accept:
+#define MAX_FRAMELEN	1518
+
+int rt_hw_enc28j60_init(void);
+
+#endif

bsp/stm32sky001/project.Uv2

+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (RT-Thread/STM32Sky), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Startup)
+Group (Library)
+Group (Kernel)
+Group (STM32)
+Group (finsh)
+
+File 1,1,<.\application.c><application.c>
+File 1,1,<.\board.c><board.c>
+File 1,1,<.\startup.c><startup.c>
+File 1,2,<.\cortexm3_macro.s><cortexm3_macro.s>
+File 1,1,<.\stm32f10x_it.c><stm32f10x_it.c>
+File 1,5,<.\stm32f10x_conf.h><stm32f10x_conf.h>
+File 1,5,<.\rtconfig.h><rtconfig.h>
+File 1,1,<.\usart.c><usart.c>
+File 1,1,<.\rtc.c><rtc.c>
+File 2,1,<.\library\src\stm32f10x_adc.c><stm32f10x_adc.c>
+File 2,1,<.\library\src\stm32f10x_bkp.c><stm32f10x_bkp.c>
+File 2,1,<.\library\src\stm32f10x_can.c><stm32f10x_can.c>
+File 2,1,<.\library\src\stm32f10x_crc.c><stm32f10x_crc.c>
+File 2,1,<.\library\src\stm32f10x_dac.c><stm32f10x_dac.c>
+File 2,1,<.\library\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c>
+File 2,1,<.\library\src\stm32f10x_dma.c><stm32f10x_dma.c>
+File 2,1,<.\library\src\stm32f10x_exti.c><stm32f10x_exti.c>
+File 2,1,<.\library\src\stm32f10x_flash.c><stm32f10x_flash.c>
+File 2,1,<.\library\src\stm32f10x_fsmc.c><stm32f10x_fsmc.c>
+File 2,1,<.\library\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
+File 2,1,<.\library\src\stm32f10x_i2c.c><stm32f10x_i2c.c>
+File 2,1,<.\library\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c>
+File 2,1,<.\library\src\stm32f10x_lib.c><stm32f10x_lib.c>
+File 2,1,<.\library\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
+File 2,1,<.\library\src\stm32f10x_pwr.c><stm32f10x_pwr.c>
+File 2,1,<.\library\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
+File 2,1,<.\library\src\stm32f10x_rtc.c><stm32f10x_rtc.c>
+File 2,1,<.\library\src\stm32f10x_sdio.c><stm32f10x_sdio.c>
+File 2,1,<.\library\src\stm32f10x_spi.c><stm32f10x_spi.c>
+File 2,1,<.\library\src\stm32f10x_systick.c><stm32f10x_systick.c>
+File 2,1,<.\library\src\stm32f10x_tim.c><stm32f10x_tim.c>
+File 2,1,<.\library\src\stm32f10x_usart.c><stm32f10x_usart.c>
+File 2,1,<.\library\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c>
+File 3,1,<..\..\src\clock.c><clock.c>
+File 3,1,<..\..\src\idle.c><idle.c>
+File 3,1,<..\..\src\ipc.c><ipc.c>
+File 3,1,<..\..\src\mem.c><mem.c>
+File 3,1,<..\..\src\mempool.c><mempool.c>
+File 3,1,<..\..\src\object.c><object.c>
+File 3,1,<..\..\src\scheduler.c><scheduler.c>
+File 3,1,<..\..\src\thread.c><thread.c>
+File 3,1,<..\..\src\timer.c><timer.c>
+File 3,1,<..\..\src\irq.c><irq.c>
+File 3,1,<..\..\src\kservice.c><kservice.c>
+File 3,1,<..\..\src\device.c><device.c>
+File 3,1,<..\..\src\slab.c><slab.c>
+File 4,1,<..\..\libcpu\arm\stm32\stack.c><stack.c>
+File 4,1,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c>
+File 4,1,<..\..\libcpu\arm\stm32\cpu.c><cpu.c>
+File 4,1,<..\..\libcpu\arm\stm32\serial.c><serial.c>
+File 4,2,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S>
+File 4,2,<..\..\libcpu\arm\stm32\start_rvds.s><start_rvds.s>
+File 4,1,<..\..\libcpu\arm\stm32\fault.c><fault.c>
+File 4,2,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S>
+File 5,1,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
+File 5,1,<..\..\finsh\finsh_error.c><finsh_error.c>
+File 5,1,<..\..\finsh\finsh_heap.c><finsh_heap.c>
+File 5,1,<..\..\finsh\finsh_init.c><finsh_init.c>
+File 5,1,<..\..\finsh\finsh_node.c><finsh_node.c>
+File 5,1,<..\..\finsh\finsh_ops.c><finsh_ops.c>
+File 5,1,<..\..\finsh\finsh_parser.c><finsh_parser.c>
+File 5,1,<..\..\finsh\finsh_token.c><finsh_token.c>
+File 5,1,<..\..\finsh\finsh_var.c><finsh_var.c>
+File 5,1,<..\..\finsh\finsh_vm.c><finsh_vm.c>
+File 5,1,<..\..\finsh\shell.c><shell.c>
+File 5,1,<..\..\finsh\symbol.c><symbol.c>
+File 5,1,<..\..\finsh\cmd.c><cmd.c>
+
+
+Options 1,0,0  // Target 'RT-Thread/STM32Sky'
+ Device (STM32F103ZE)
+ Vendor (STMicroelectronics)
+ Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3"))
+ FlashUt ()
+ StupF ("STARTUP\ST\STM32F10x.s" ("STM32 Startup Code"))
+ FlashDR (UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000))
+ DevID (4216)
+ Rgf (stm32f10x_lib.h)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (ST\STM32F10x\)
+ OrgReg (ST\STM32F10x\)
+ TgStat=16
+ OutDir (.\obj\)
+ OutName (rtthread-stm32)
+ GenApp=1
+ GenLib=0
+ GenHex=1
+ Debug=1
+ Browse=1
+ LstDir (.\obj\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP ("Cortex-M3")
+ RVDEV ()
+ ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }
+ OCMADSIROM { 1,0,0,0,8,0,0,8,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD (.;.\library\inc;.\library\src;..\..\include;..\..\libcpu\arm\stm32;..\..\finsh)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x08000000)
+ ADSLDDA (0x20000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC (--keep __fsym_* --keep __vsym_*)
+ ADSLDIF ()
+ ADSLDDW ()
+  OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE)
+  OPTDBG 48117,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
+ FLASH1 { 9,0,0,0,1,0,0,0,5,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (Segger\JLTAgdi.dll)
+ FLASH3 ("" ())
+ FLASH4 ()
+EndOpt
+

bsp/stm32sky001/project.eww

+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/stm32sky001/rtc.h

+#ifndef __RTC_H__
+#define __RTC_H__
+
+void rt_hw_rtc_init(void);
+
+#endif

bsp/stm32sky001/rtconfig.h

+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX	256
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+#define RT_DEBUG
+/* #define RT_THREAD_DEBUG */
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+
+/* Using SLAB Allocator*/
+/* #define RT_USING_SLAB */
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+// #define RT_USING_UART2
+// #define RT_USING_UART3
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+/* #define RT_USING_MINILIBC */
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* #define RT_USING_RTGUI */
+
+/* #define RT_USING_DFS */
+/* SECTION: DFS options */
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					8
+/* the max number of cached sector 		*/
+#define DFS_CACHE_MAX_NUM   		8
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+/* #define RT_USING_LWIP */
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+/* #define RT_LWIP_IGMP */
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* TCP sender buffer space*/
+#define RT_LWIP_TCP_SND_BUF	1500
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+#define RT_LWIP_DNS
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		120
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		128
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+#endif

bsp/stm32sky001/usart.h

+#ifndef __USART_H__
+#define __USART_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+void rt_hw_usart_init(void);
+
+#endif