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体验新版 GitCode,发现更多精彩内容 >>
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598f2d36
编写于
5月 09, 2019
作者:
E
EvalZero
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电子邮件补丁
差异文件
[bsp][stm32l475-atk-pandora]adapt new pm interface for stm32l475-atk-pandora.
上级
b242b1e6
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
217 addition
and
44 deletion
+217
-44
bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
...-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
+1
-1
bsp/stm32/stm32l475-atk-pandora/board/board.c
bsp/stm32/stm32l475-atk-pandora/board/board.c
+210
-43
bsp/stm32/stm32l475-atk-pandora/board/board.h
bsp/stm32/stm32l475-atk-pandora/board/board.h
+6
-0
未找到文件。
bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
浏览文件 @
598f2d36
...
...
@@ -69,7 +69,7 @@
#define HAL_IWDG_MODULE_ENABLED
/*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
#define HAL_LPTIM_MODULE_ENABLED
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
...
...
bsp/stm32/stm32l475-atk-pandora/board/board.c
浏览文件 @
598f2d36
...
...
@@ -10,55 +10,222 @@
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2019-05-09 Zero-Free Adding multiple configurations for system clock frequency
*/
#include <board.h>
#include <rtthread.h>
void
SystemClock_Config
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInit
=
{
0
};
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInit
=
{
0
};
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
1
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
20
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV7
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInit
.
PeriphClockSelection
=
RCC_PERIPHCLK_USART1
|
RCC_PERIPHCLK_USART2
;
PeriphClkInit
.
Usart1ClockSelection
=
RCC_USART1CLKSOURCE_PCLK2
;
PeriphClkInit
.
Usart2ClockSelection
=
RCC_USART2CLKSOURCE_PCLK1
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInit
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure the main internal regulator output voltage
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
1
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
20
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV7
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInit
.
PeriphClockSelection
=
RCC_PERIPHCLK_USART1
|
RCC_PERIPHCLK_USART2
;
PeriphClkInit
.
Usart1ClockSelection
=
RCC_USART1CLKSOURCE_PCLK2
;
PeriphClkInit
.
Usart2ClockSelection
=
RCC_USART2CLKSOURCE_PCLK1
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInit
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Configure the main internal regulator output voltage
*/
if
(
HAL_PWREx_ControlVoltageScaling
(
PWR_REGULATOR_VOLTAGE_SCALE1
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
#ifdef RT_USING_PM
void
SystemClock_MSI_ON
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
/* Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_MSI
;
RCC_OscInitStruct
.
MSIState
=
RCC_MSI_ON
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
RT_ASSERT
(
0
);
}
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_SYSCLK
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_MSI
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_1
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_MSI_OFF
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_MSI
;
RCC_OscInitStruct
.
HSIState
=
RCC_MSI_OFF
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_NONE
;
/* No update on PLL */
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_80M
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
;
RCC_ClkInitTypeDef
RCC_ClkInitStruct
;
/**Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
1
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
20
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV7
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_24M
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
;
RCC_ClkInitTypeDef
RCC_ClkInitStruct
;
/** Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
1
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
12
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV7
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV4
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB busses clocks */
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_1
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_2M
(
void
)
{
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
/* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_MSI
;
RCC_OscInitStruct
.
MSIState
=
RCC_MSI_ON
;
RCC_OscInitStruct
.
MSIClockRange
=
RCC_MSIRANGE_5
;
RCC_OscInitStruct
.
MSICalibrationValue
=
RCC_MSICALIBRATION_DEFAULT
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_NONE
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
/* Initialization Error */
Error_Handler
();
}
/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_SYSCLK
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_MSI
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_0
)
!=
HAL_OK
)
{
/* Initialization Error */
Error_Handler
();
}
}
/**
* @brief Configures system clock after wake-up from STOP: enable HSI, PLL
* and select PLL as system clock source.
* @param None
* @retval None
*/
if
(
HAL_PWREx_ControlVoltageScaling
(
PWR_REGULATOR_VOLTAGE_SCALE1
)
!=
HAL_OK
)
{
Error_Handler
();
}
void
SystemClock_ReConfig
(
uint8_t
mode
)
{
SystemClock_MSI_ON
();
switch
(
mode
)
{
case
PM_RUN_MODE_HIGH_SPEED
:
case
PM_RUN_MODE_NORMAL_SPEED
:
SystemClock_80M
();
break
;
case
PM_RUN_MODE_MEDIUM_SPEED
:
SystemClock_24M
();
break
;
case
PM_RUN_MODE_LOW_SPEED
:
SystemClock_2M
();
break
;
default:
break
;
}
// SystemClock_MSI_OFF();
}
#endif
bsp/stm32/stm32l475-atk-pandora/board/board.h
浏览文件 @
598f2d36
...
...
@@ -32,6 +32,12 @@ extern "C" {
#define HEAP_END STM32_SRAM1_END
void
SystemClock_Config
(
void
);
void
SystemClock_MSI_ON
(
void
);
void
SystemClock_MSI_OFF
(
void
);
void
SystemClock_80M
(
void
);
void
SystemClock_24M
(
void
);
void
SystemClock_2M
(
void
);
void
SystemClock_ReConfig
(
uint8_t
mode
);
#ifdef __cplusplus
}
...
...
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