add raspi2 and raspi3 BSP

bsp/raspberry-pi/raspi2/Kconfig

+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2836_SOC
+    bool
+    select ARCH_ARM_CORTEX_A7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "driver/Kconfig"

bsp/raspi2/SConstruct → bsp/raspberry-pi/raspi2/SConstruct

@@ -22,7 +22,7 @@ Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
 
 # make a building
 DoBuilding(TARGET, objs)

bsp/raspi2/rtconfig.py → bsp/raspberry-pi/raspi2/rtconfig.py

@@ -8,13 +8,13 @@ CROSS_TOOL  ='gcc'
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = r'../..'
+    RTT_ROOT = r'../../..'
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
 PLATFORM    = 'gcc'
-EXEC_PATH   = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+EXEC_PATH   = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin'
 
 if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')

bsp/raspberry-pi/raspi3-32/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=4
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+CONFIG_RT_USING_MEMTRACE=y
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_DEVICE_OPS=y
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40002
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_CORTEX_A=y
+CONFIG_ARCH_ARM_CORTEX_A7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_USING_I2C_BITOPS is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_SDIO_STACK_SIZE=512
+CONFIG_RT_SDIO_THREAD_PRIORITY=15
+CONFIG_RT_MMCSD_STACK_SIZE=1024
+CONFIG_RT_MMCSD_THREAD_PREORITY=22
+CONFIG_RT_MMCSD_MAX_PARTITION=16
+# CONFIG_RT_SDIO_DEBUG is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_LCD_DRIVERS is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+CONFIG_BCM2836_SOC=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+# CONFIG_RT_USING_UART0 is not set
+CONFIG_RT_USING_UART1=y
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_SYSTIMER=y
+CONFIG_RT_USING_SYSTIMER1=y
+CONFIG_RT_USING_SYSTIMER3=y
+CONFIG_BSP_USING_I2C=y
+CONFIG_BSP_USING_I2C0=y
+CONFIG_BSP_USING_I2C1=y
+CONFIG_BSP_USING_SPI=y
+CONFIG_BSP_USING_SPI0_BUS=y
+CONFIG_BSP_USING_SPI0_DEVICE0=y
+CONFIG_BSP_USING_SPI0_DEVICE1=y
+CONFIG_BSP_USING_WDT=y
+CONFIG_BSP_USING_RTC=y
+# CONFIG_BSP_USING_ALARM is not set
+CONFIG_BSP_USING_SDIO=y
+CONFIG_BSP_USING_SDIO0=y
+CONFIG_BSP_USING_HDMI=y

bsp/raspberry-pi/raspi3-32/README.md

+# Raspberry PI 3B(32位)板级支持包说明
+
+## 1. 简介
+
+树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3采用4核Broadcom BCM2837 (ARMv8)芯片、双核VideoCore IV GPU和1GB内存。
+
+这份RT-Thread BSP是针对 Raspberry Pi 3B （32位）的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+随着RT-Thread的发展，它越来越多的向一些Cortex-A等AP类处理器提供支持，例如全志的ARM9、Cortex-A处理器，Xilinx的Zynq处理器等。
+
+而RT-Thread也是一套高度社区化发展的操作系统，所以在一些方向推进上希望以社区化方式，大家一起来推动的方式向前发展，在这个过程中RT-Thread得到了不同开发者、不同领域的应用，一步步把RT-Thread推向成熟。而在Cortex-A平台上，目前最流行的硬件平台是树莓派，分树莓派[2B](https://www.raspberrypi.org/products/raspberry-pi-2-model-b/)、[3B](https://www.raspberrypi.org/products/raspberry-pi-3-model-b/)以及最新的[4B](https://www.raspberrypi.org/products/raspberry-pi-4-model-b/)等。
+
+RT-Thread对树莓派的支持主要从树莓派2B开始，它是一个四核Cortex-A7的平台，以32位单核的模式运行。后续将推动着RT-Thread向树莓派3，四核Cortex-A53 64位模式发展（中间当然也可能出现四核Cortex-A7模式执行的过渡性版本）。
+
+![raspi3_f](figures/raspi3_f.jpg)
+
+![raspi3_b](figures/raspi3_b.jpg)
+
+当前Raspberry Pi 3B对应的硬件特性：
+
+| 硬件   | 描述 |
+|------- | ------------------------------- |
+|  CPU   | quad-core ARM Cortex A53(ARMv8) |
+|  主频  | 1.2 GHz |
+| GPU | VideoCore IV |
+| GPU频率 | 400MHz |
+| Memory | 1GB  (0x0000000 - 0x40000000) |
+| | 其中0x3f000000 - 0x40000000为peripheral |
+
+硬件引脚分布情况
+
+![GPIO-Pinout-Diagram-2](figures/GPIO-Pinout-Diagram-2.png)
+
+## 2. 编译说明
+
+Windows环境下推荐使用[env工具][1]进行编译。
+
+Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。
+
+```
+tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
+```
+
+Linux环境下需要修改编译器目录设置，修改`bsp/raspi3-32/rtconfig.py`中的
+
+```
+EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+```
+
+为编译工具的实际所在目录，这里注意要加上后缀 `/bin`
+
+进入到`rt-thread/bsp/raspi3-32`目录中，运行以下命令：
+
+```
+scons
+```
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、kernel7.img文件。
+kernel7.img即是要cp到raspberry SD卡中根目录的文件
+
+### 2.1 eclipse 编码环境 ###
+第一步： 安装 eclipse cdt 
+第二步： 打开 eclipse cdt 设置workspace ,推荐设置于xxx\xxx\rt-thread\bsp
+第三步： Import 工程 General-> Existing Peojects into Workspace 然后 Browse.. 你的raspi3目录，点击Finish
+
+btw:编译依旧使用scons,目前不支持qemu debug,后期如果有大佬实现ARM JTAG调试
+
+## 3. 执行
+
+### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
+
+Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
+
+解开下载的镜像文件, linux下使用如下的命令
+
+```
+unzip 2018-06-27-raspbian-stretch-lite.zip
+```
+
+准备一张空SD卡，linux环境下，插入电脑并执行
+
+```
+sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
+```
+
+**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+
+Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+
+最后把kernel7.img放入SD boot分区，覆盖原来的文件。
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
+
+
+
+![raspberrypi-console](figures/raspberrypi-console.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+按上面的方法做好SD卡后，插入树莓派3B，通电可以在串口上看到如下所示的输出信息：
+
+```text
+heap: 0x0005d784 - 0x0045d784
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.2 build Jan  9 2020
+ 2006 - 2019 Copyright by rt-thread team
+[I/I2C] I2C bus [i2c0] registered
+[I/I2C] I2C bus [i2c1] registered
+[I/SDIO] SD card capacity 15558144 KB.
+found part[0], begin: 1048576, size: 63.0MB
+found part[1], begin: 67108864, size: 14.793GB
+file system initialization done!
+boot cpu:3
+msh />cpu = 0x00000003
+cpu 3 startup.
+start OK: CPU 3
+boot cpu:2
+cpu = 0x00000002
+cpu 2 startup.
+start OK: CPU 2
+boot cpu:1
+cpu = 0x00000001
+cpu 1 startup.
+start OK: CPU 1
+Hello RT-Thread!
+
+msh />
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+| GPIO | 支持 | |
+| IIC | 支持 | |
+| SPI | 支持 | |
+| CPU Timer | 支持 | |
+| SD卡驱动 | 支持 | |
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong

bsp/raspberry-pi/raspi3-32/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/raspberry-pi/raspi3-32/SConstruct

+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/raspberry-pi/raspi3-32/applications/SConscript

+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/raspberry-pi/raspi3-32/applications/main.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hello RT-Thread!\n");
+
+    return 0;
+}

bsp/raspberry-pi/raspi3-32/applications/mnt.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_SDIO0
+#include <dfs_fs.h>
+
+int mnt_init(void)
+{
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("file system initialization done!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+

bsp/raspberry-pi/raspi3-32/applications/test_device.c

+/*
+ * File      : test_driver.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <string.h>
+#include <drivers/hwtimer.h>
+#include "raspi.h"
+
+#ifdef BSP_USING_HDMI
+#include "drv_fb.h"
+#endif
+
+void test_hdmi()
+{
+    rt_kprintf("Hello Test hdmi!\n");
+#ifdef BSP_USING_HDMI
+    print_fb_info();
+#ifdef BSP_USING_HDMI_DISPLAY
+    rt_kprintf("hdmi is tested!\n");
+#else
+    rt_console_set_device("hdmi");
+    rt_kprintf("hdmi is testing!\n");
+#endif
+    rt_kprintf("search hdmi device");
+    rt_device_t hdmi = rt_device_find("hdmi");
+    if (hdmi == RT_NULL)
+    {
+        rt_kprintf("cannot find hdmi device");
+    }
+    int color = COLOR_YELLOW;
+    rt_kprintf("begin test hdmi deivice");
+    rt_graphix_ops(hdmi) -> set_pixel((char *)&color, 5, 5);
+
+    rt_graphix_ops(hdmi) -> get_pixel((char *)&color, 5, 5);
+    rt_kprintf("color is %x\n",color);
+    rt_graphix_ops(hdmi) -> draw_hline((char *)&color, 10, 100, 10);
+    color = COLOR_GREEN;
+    rt_graphix_ops(hdmi) -> draw_vline((char *)&color, 10, 10, 100);
+    int colors[100];
+    int i=0;
+    for (; i < 20; i++)  colors[i] = COLOR_RED;
+    rt_graphix_ops(hdmi) -> blit_line((char *)colors, 20, 20, 20);
+    
+#endif
+}
+
+#ifdef RT_USING_SMP
+#define _CPUS_NR                RT_CPUS_NR
+#else
+#define _CPUS_NR                1
+#endif
+
+#ifdef RT_USING_SMP
+static rt_uint8_t rt_thread_stack[_CPUS_NR][128];
+static struct rt_thread smp[_CPUS_NR];
+void smp_test_entry()
+{
+    rt_kprintf("cpu %d is running.\n",rt_hw_cpu_id());
+}
+#endif
+
+void test_cpusmp(void)
+{
+    rt_kprintf("Hello Test SMP!\n");
+#ifdef RT_USING_SMP
+    int i;    
+    char test_name[RT_NAME_MAX]; 
+    for (i = 0; i < _CPUS_NR; i++)
+    {
+        rt_sprintf(test_name, "smp%d", i);
+        rt_thread_init(&smp[i],
+                test_name,
+                smp_test_entry,
+                RT_NULL,
+                &rt_thread_stack[i][0],
+                sizeof(rt_thread_stack[i]),
+                RT_THREAD_PRIORITY_MAX - 2,
+                32);
+        rt_thread_control(&smp[i], RT_THREAD_CTRL_BIND_CPU, (void*)i);
+        /* startup */
+        rt_thread_startup(&smp[i]);
+        rt_thread_delay(RT_TICK_PER_SECOND);
+    }
+#endif
+}
+
+#ifdef BSP_USING_PIN
+#define TEST_PIN_OUT 33
+#define TEST_PIN_IN 37
+
+void gpio_rising_test()
+{
+     rt_kprintf("gpio rising irq function ok!\n");
+}
+#endif
+
+void test_gpio(void)
+{
+#ifdef BSP_USING_PIN
+    rt_uint32_t ret;
+    rt_kprintf("Hello Test GPIO!\n");
+
+    rt_pin_mode(TEST_PIN_OUT, PIN_MODE_OUTPUT);
+    rt_pin_write(TEST_PIN_OUT, PIN_HIGH);
+    rt_pin_mode(TEST_PIN_IN, PIN_MODE_INPUT);
+
+    ret = rt_pin_read(TEST_PIN_IN);
+    rt_kprintf("common high input test read result: %d\n",ret);
+
+    rt_pin_write(TEST_PIN_OUT, PIN_LOW);
+    ret = rt_pin_read(TEST_PIN_IN);
+    rt_kprintf("common low input test read result: %d\n",ret);
+
+    rt_pin_mode(TEST_PIN_IN, PIN_MODE_INPUT_PULLDOWN);
+    rt_pin_attach_irq(TEST_PIN_IN, PIN_IRQ_MODE_RISING, gpio_rising_test, RT_NULL);
+    rt_pin_irq_enable(TEST_PIN_IN, PIN_IRQ_ENABLE);
+    rt_pin_write(TEST_PIN_OUT, PIN_HIGH);
+
+    rt_pin_irq_enable(TEST_PIN_IN, PIN_IRQ_DISABLE);
+#endif
+}
+
+#ifdef BSP_USING_I2C1
+#define DS3231_I2C_BUS_NAME      "i2c1"
+#define DS3231_ADDR               0x68
+struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+static rt_err_t read_regs(struct rt_i2c_bus_device *bus, rt_uint8_t len, rt_uint8_t *buf)
+{
+    struct rt_i2c_msg msgs;
+    msgs.addr = DS3231_ADDR;
+    msgs.flags = RT_I2C_RD;
+    msgs.buf = buf;
+    msgs.len = len;
+
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+        return RT_EOK;
+    else
+        return -RT_ERROR;
+}
+#endif
+
+void test_i2c(void)
+{
+#ifdef BSP_USING_I2C1
+    rt_kprintf("Hello Test I2C!\n");
+    char name[RT_NAME_MAX];
+    rt_uint8_t  buf[]={0x00,0x00,0x43,0x15,0x05,0x01,0x03,0x19};
+
+    rt_strncpy(name, DS3231_I2C_BUS_NAME, RT_NAME_MAX);
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
+    if (i2c_bus == RT_NULL)
+        rt_kprintf("can't find %s device!\n", name);
+    else
+    {
+    	read_regs(i2c_bus, 7, buf);
+    	buf[0] = buf[0]&0x7F; //sec
+    	buf[1] = buf[1]&0x7F; //min
+    	buf[2] = buf[2]&0x3F; //hour
+    	buf[3] = buf[3]&0x07; //week
+    	buf[4] = buf[4]&0x3F; //day
+    	buf[5] = buf[5]&0x1F; //mouth
+    	//year/month/day
+    	rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]);
+    	//hour:minute/second
+    	rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]);
+    }
+#endif
+}
+
+#define W25Q_SPI_DEVICE_NAME     "spi0.0"
+void test_spi(void)
+{
+#ifdef BSP_USING_SPI
+    rt_kprintf("Hello Test SPI!\n");
+    struct rt_spi_device *spi0_dev0;
+    struct rt_spi_device *spi0_dev1;
+
+    char name0[RT_NAME_MAX];
+    char name1[RT_NAME_MAX];
+
+    rt_uint8_t w25x_read_id = 0x90;
+    rt_uint8_t id[5] = {0};
+
+    rt_strncpy(name0, "spi0.0", RT_NAME_MAX);
+    rt_strncpy(name1, "spi0.1", RT_NAME_MAX);
+
+    spi0_dev0 = (struct rt_spi_device *)rt_device_find(name0);
+    spi0_dev1 = (struct rt_spi_device *)rt_device_find(name1);
+
+
+    if (!spi0_dev0 || !spi0_dev1)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", name0);
+    }
+    else
+    {
+        struct rt_spi_message msg1, msg2;
+
+        msg1.send_buf   = &w25x_read_id;
+        msg1.recv_buf   = RT_NULL;
+        msg1.length     = 1;
+        msg1.cs_take    = 1;
+        msg1.cs_release = 0;
+        msg1.next       = &msg2;
+
+        msg2.send_buf   = RT_NULL;
+        msg2.recv_buf   = id;
+        msg2.length     = 5;
+        msg2.cs_take    = 0;
+        msg2.cs_release = 1;
+        msg2.next       = RT_NULL;
+
+        rt_spi_transfer_message(spi0_dev0, &msg1);
+        rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
+
+    }
+#endif
+}
+
+#ifdef BSP_USING_SYSTIMER
+#define TIMER   "timer1"
+
+static rt_err_t timer_timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("enter hardware timer isr\n");
+    return 0;
+}
+#endif
+rt_err_t test_hwtimer(void)
+{
+#ifdef BSP_USING_SYSTIMER
+    rt_kprintf("Hello Test HW Timer!\n");
+    rt_err_t err;
+    rt_hwtimerval_t val;
+    rt_device_t dev = RT_NULL;
+    rt_tick_t tick;
+    rt_hwtimer_mode_t mode;
+    int t = 5;
+
+    if ((dev = rt_device_find(TIMER)) == RT_NULL)
+    {
+        rt_kprintf("No Device: %s\n", TIMER);
+        return -1;
+    }
+
+    if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK)
+    {
+        rt_kprintf("Open %s Fail\n", TIMER);
+        return -1;
+    }
+
+    mode = HWTIMER_MODE_PERIOD;
+    err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode);
+
+    tick = rt_tick_get();
+    rt_kprintf("Start Timer> Tick: %d\n", tick);
+
+    val.sec = t;
+    val.usec = 0;
+    rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec);
+    if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val))
+    {
+        rt_kprintf("SetTime Fail\n");
+        goto EXIT;
+    }
+    rt_kprintf("Sleep %d sec\n", t);
+    rt_thread_delay(t*RT_TICK_PER_SECOND);
+
+    err = rt_device_control(dev, HWTIMER_CTRL_STOP, RT_NULL);
+    rt_kprintf("Timer Stoped\n");
+
+    rt_device_read(dev, 0, &val, sizeof(val));
+    rt_kprintf("Read: Sec = %d, Usec = %d\n", val.sec, val.usec);
+
+    rt_device_set_rx_indicate(dev, timer_timeout_cb);
+
+    mode = HWTIMER_MODE_PERIOD;
+    err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode);
+
+    val.sec = t;
+    val.usec = 0;
+    rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec);
+    if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val))
+    {
+        rt_kprintf("SetTime Fail\n");
+        goto EXIT;
+    }
+
+    rt_thread_delay((t *5 + 1)*RT_TICK_PER_SECOND);
+
+EXIT:
+    err = rt_device_close(dev);
+    rt_kprintf("Close %s\n", TIMER);
+
+    return err;
+#endif
+}
+
+#ifdef RT_USING_WDT
+#define WDT_DEVICE_NAME    "wdg"    /* 鐪嬮棬鐙楄澶囧悕绉� */
+static rt_device_t wdg_dev;         /* 鐪嬮棬鐙楄澶囧彞鏌� */
+static void idle_hook(void)
+{
+    /* 鍦ㄧ┖闂茬嚎绋嬬殑鍥炶皟鍑芥暟閲屽杺鐙� */
+    rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL);
+    //rt_kprintf("feed the dog!\n ");
+}
+
+rt_err_t test_wdt(void)
+{
+    rt_kprintf("Hello Test WDT!\n");
+    rt_err_t ret = RT_EOK;
+    rt_uint32_t timeout = 1;        /* 婧㈠嚭鏃堕棿锛屽崟浣嶏細绉� */
+    char device_name[RT_NAME_MAX];
+    rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX);
+    /* 鏍规嵁璁惧鍚嶇О鏌ユ壘鐪嬮棬鐙楄澶囷紝鑾峰彇璁惧鍙ユ焺 */
+    wdg_dev = rt_device_find(device_name);
+    if (!wdg_dev)
+    {
+        rt_kprintf("find %s failed!\n", device_name);
+        return RT_ERROR;
+    }
+    /* 鍒濆鍖栬澶� */
+    ret = rt_device_init(wdg_dev);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("initialize %s failed!\n", device_name);
+        return RT_ERROR;
+    }
+    /* 璁剧疆鐪嬮棬鐙楁孩鍑烘椂闂� */
+    ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set %s timeout failed!\n", device_name);
+        return RT_ERROR;
+    }
+    /* 鍚姩鐪嬮棬鐙� */
+    ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("start %s failed!\n", device_name);
+        return -RT_ERROR;
+    }
+    /* 璁剧疆绌洪棽绾跨▼鍥炶皟鍑芥暟 */
+    rt_thread_idle_sethook(idle_hook);
+
+    return ret;
+
+}
+#else
+rt_err_t test_wdt(void)
+{
+    return RT_EOK;
+}
+#endif
+
+int test_rtc(void)
+{
+#ifdef BSP_USING_RTD
+    rt_kprintf("Hello Test RTC!\n");
+    uint8_t i;
+    time_t now;
+
+    rt_err_t ret = RT_EOK;
+
+    rt_kprintf("[RTC Test]RTC Test Start...\n");
+    rt_thread_delay(RT_TICK_PER_SECOND);
+    rt_kprintf("[RTC Test]Set RTC 2017-04-01 12:30:46\n\n");
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    ret = set_date(2017, 4, 1);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("[RTC Test]Set RTC Date failed\n");
+        return RT_ERROR;
+    }
+
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    ret = set_time(12, 30, 46);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("[RTC Test]Set RTC Time failed\n");
+        return RT_ERROR;
+    }
+
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    for (i = 0; i < 10; i++)
+    {
+        rt_kprintf("[RTC Test]Read RTC Date and Time: ");
+        now = time(RT_NULL);
+        rt_kprintf("%s", ctime(&now));
+
+        rt_thread_delay(RT_TICK_PER_SECOND);
+    }
+
+    rt_kprintf("\n");
+#endif
+    return RT_EOK;
+}
+
+void test_device(int argc, char**argv)
+{
+    if (0 == strcmp(argv[1],"smp"))
+    {
+        test_cpusmp();
+        return;
+    }
+    if (0 == strcmp(argv[1],"gpio"))
+    {
+        test_gpio();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"i2c"))
+    {
+        test_i2c();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"spi"))
+    {
+        test_spi();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"hwtimer"))
+    {
+        test_hwtimer();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"wdt"))
+    {
+        test_wdt();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"rtc"))
+    {
+        test_rtc();
+        return;
+    }
+    if (0 == strcmp(argv[1],"hdmi"))
+    {
+        test_hdmi();
+        return;
+    }
+    rt_kprintf("param err, please entry test_device <smp|gpio|i2c|spi|hwtimer|wdt|rtc|hdmi>\n");
+}
+MSH_CMD_EXPORT(test_device, sample: test_device <smp|gpio|i2c|spi|hwtimer|wdt|rtc>);

bsp/raspberry-pi/raspi3-32/cpu/armv7.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif

bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "../rtconfig.h"
+.section .text, "ax"
+
+#ifdef RT_USING_SMP
+#define rt_hw_interrupt_disable rt_hw_local_irq_disable
+#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
+#endif
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> to (thread stack)
+ * r1 --> to_thread
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+#ifdef RT_USING_SMP
+    mov     r0, r1
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+    b       rt_hw_context_switch_exit
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.globl vmm_virq_update
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> from (from_thread stack)
+ * r1 --> to (to_thread stack)
+ * r2 --> to_thread
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
+    sub sp, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+#ifdef RT_USING_SMP
+    mov     r0, r2
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+    b       rt_hw_context_switch_exit
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+#ifdef RT_USING_SMP
+    /* r0 :svc_mod context
+     * r1 :addr of from_thread's sp
+     * r2 :addr of to_thread's sp
+     * r3 :to_thread's tcb
+     */
+
+    str     r0, [r1]
+
+    ldr     sp, [r2]
+    mov     r0, r3
+    bl      rt_cpus_lock_status_restore
+
+    b       rt_hw_context_switch_exit
+
+#else /*RT_USING_SMP*/
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
+#endif /*RT_USING_SMP*/
+
+.global rt_hw_context_switch_exit
+rt_hw_context_switch_exit:
+
+#ifdef RT_USING_SMP
+#ifdef RT_USING_SIGNALS
+    mov     r0, sp
+    cps #Mode_IRQ
+    bl      rt_signal_check
+    cps #Mode_SVC
+    mov     sp, r0
+#endif
+#endif
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
+    add     sp, #8
+#endif
+    ldmfd   sp!, {r4}
+    msr     spsr_cxsf, r4        /* original mode */
+    ldmfd   sp!, {r0-r12,lr,pc}^ /* irq return */
+

bsp/raspberry-pi/raspi3-32/cpu/cp15.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+#include "raspi.h"
+#ifndef __CP15_H__
+#define __CP15_H__
+
+#ifndef   __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
+#endif
+
+#define __WFI()    __asm__ volatile ("wfi":::"memory")
+
+#define __WFE()    __asm__ volatile ("wfe":::"memory")
+
+#define __SEV()    __asm__ volatile ("sev")
+
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+    __asm__ volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+    __asm__ volatile ("dmb 0xF":::"memory");
+}
+
+
+#ifdef RT_USING_SMP
+static inline void send_ipi_msg(int cpu, int ipi_vector)
+{
+    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
+}
+
+static inline void setup_bootstrap_addr(int cpu, int addr)
+{
+	CORE_MAILBOX3_SET(cpu) = addr;
+}
+
+static inline void enable_cpu_ipi_intr(int cpu)
+{
+    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
+}
+
+static inline void enable_cpu_timer_intr(int cpu)
+{
+	CORETIMER_INTCTL(cpu) = 0x8;
+}
+
+static inline void enable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline void disable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 0;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline  void mask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 2;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline void unmask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline rt_uint64_t read_cntvct(void)
+{
+    rt_uint32_t val,val1;
+    asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
+    return (val);
+}
+
+static inline rt_uint64_t read_cntvoff(void)
+{
+
+    rt_uint64_t val;
+    asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
+    return (val);
+}
+
+static inline rt_uint32_t read_cntv_tval(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
+    return val;
+}
+
+
+static inline  void write_cntv_tval(rt_uint32_t val)
+{
+    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
+    return;
+}
+
+static inline rt_uint32_t read_cntfrq(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
+    return val;
+}
+
+
+static inline  rt_uint32_t read_cntctrl(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
+    return val;
+}
+
+static inline uint32_t write_cntctrl(uint32_t val)
+{
+
+    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
+    return val;
+}
+#endif
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+void rt_hw_mmu_init(void);
+void rt_hw_vector_init(void);
+
+void set_timer_counter(unsigned int counter);
+void set_timer_control(unsigned int control);
+#endif

bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    /* clear SCTRL.V to customize the vector address */
+    mrc     p15, #0, r1, c1, c0, #0
+    bic     r1, #(1 << 13)
+    mcr     p15, #0, r1, c1, c0, #0
+    /* set up the vector address */
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl set_timer_counter
+set_timer_counter:
+    mcr     p15, #0, r0, c14, c3, #0  @ write virtual timer timerval register
+    bx      lr
+.globl set_timer_control
+set_timer_control:
+    mcr     p15, #0, r0, c14, c3, #1  @ write virtual timer control register
+    bx      lr
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_cpu_icache_flush
+rt_cpu_icache_flush:
+    mov r0, #0
+    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
+    dsb
+    isb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr

bsp/raspberry-pi/raspi3-32/cpu/cpu.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+#include "cp15.h"
+
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    __asm__ volatile (
+            "mrc p15, 0, %0, c0, c0, 5"
+            :"=r"(cpu_id)
+            );
+    cpu_id &= 0xf;
+    return cpu_id;
+};
+
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) 
+    {
+        __WFE();
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __DMB();
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __DMB();
+    lock->tickets.owner++;
+    __DSB();
+    __SEV();
+}
+#endif /*RT_USING_SMP*/
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/

bsp/raspberry-pi/raspi3-32/cpu/interrupt.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/3       Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "cp15.h"
+#include <board.h>
+
+#define MAX_HANDLERS                72
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+const unsigned int VECTOR_BASE = 0x00;
+extern void rt_cpu_vector_set_base(unsigned int addr);
+extern int system_vectors;
+
+void rt_hw_vector_init(void)
+{
+    rt_cpu_vector_set_base((unsigned int)&system_vectors);
+}
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+extern int system_vectors;
+
+static void default_isr_handler(int vector, void *param)
+{
+#ifdef RT_USING_SMP
+    rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
+#else
+    rt_kprintf("unhandled irq: %d\n",vector);
+#endif
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t index;
+
+    /* mask all of interrupts */
+    IRQ_DISABLE_BASIC = 0x000000ff;
+    IRQ_DISABLE1      = 0xffffffff;
+    IRQ_DISABLE2      = 0xffffffff;
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        isr_table[index].handler = default_isr_handler;
+        isr_table[index].param = NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
+        isr_table[index].counter = 0;
+#endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+
+    if (vector < 32)
+    {
+        IRQ_DISABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_DISABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_DISABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    if (vector < 32)
+    {
+        IRQ_ENABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_ENABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_ENABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+    __DSB();
+    if (cpu_mask & 0x1)
+    {
+        send_ipi_msg(0, ipi_vector);
+    }
+    if (cpu_mask & 0x2)
+    {
+    	send_ipi_msg(1, ipi_vector);
+    }
+    if (cpu_mask & 0x4)
+    {
+    	send_ipi_msg(2, ipi_vector);
+    }
+    if (cpu_mask & 0x8)
+    {
+    	send_ipi_msg(3, ipi_vector);
+    }
+    __DSB();
+}
+#endif
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    /* note: ipi_vector maybe different with irq_vector */
+    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif

bsp/raspberry-pi/raspi3-32/cpu/interrupt.h

+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif

bsp/raspberry-pi/raspi3-32/cpu/mmu.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "mmu.h"
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for (i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_init_mmu_table()
+{
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
+}
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr)
+{
+    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
+#ifndef RT_USING_SMP
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+#endif
+}
+
+
+void rt_hw_mmu_init(void)
+{
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+

bsp/raspberry-pi/raspi3-32/cpu/mmu.h

+#ifndef MMU_H__
+#define MMU_H__
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3 << 2)  //cache_on, write_back
+#define CNB            (2 << 2)  //cache_on, write_through
+#define NCB            (1 << 2)  //cache_off,WR_BUF on
+#define NCNB           (0 << 2)  //cache_off,WR_BUF off
+#define AP_RW          (3 << 10) //supervisor=RW, user=RW
+#define AP_RO          (2 << 10) //supervisor=RW, user=RO
+#define XN             (1 << 4)  // eXecute Never
+#define SHARED         (1 << 16) /* shareable */
+#define SHAREDEVICE    (1 << 2)  /* shared device */
+#define STRONGORDER    (0 << 2)  /* strong ordered */
+#define MEMWBWA        ((1 << 12) | (3 << 2))     /* write back, write allocate */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0 << 5)
+#define DOMAIN1        (0x1 << 5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK << 0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT << 2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW | DOMAIN0 | CB | DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW | DOMAIN0 | CNB | DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW | DOMAIN0 | NCNB | DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW | DOMAIN1 | NCNB | DESC_SEC)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED | SHAREDEVICE | RW_NCNBXN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
+#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
+#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr);
+#endif

bsp/raspberry-pi/raspi3-32/cpu/stack.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+#include <armv7.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+#ifdef RT_USING_LWP
+    *(--stk) = 0;       /* user lr */
+    *(--stk) = 0;       /* user sp*/
+#endif
+#ifdef RT_USING_FPU
+    *(--stk) = 0;       /* not use fpu*/
+#endif
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
+/*@}*/

bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "../rtconfig.h"
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+#ifdef RT_USING_FPU
+.equ UND_Stack_Size,     0x00000400
+#else
+.equ UND_Stack_Size,     0x00000000
+#endif
+.equ SVC_Stack_Size,     0x00000400
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000800
+.equ USR_Stack_Size,     0x00000400
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+
+#ifdef RT_USING_SMP
+.globl stack_start0
+.globl stack_top0
+.globl stack_start1
+.globl stack_top1
+.globl stack_start2
+.globl stack_top2
+.globl stack_start3
+.globl stack_top3
+stack_start0:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top0:
+
+stack_start1:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top1:
+
+stack_start2:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top2:
+
+stack_start3:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top3:
+
+.globl boot_indicate
+boot_indicate:
+.rept 16
+.byte 0
+.endr
+
+#else
+.globl stack_start
+.globl stack_top
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+#endif
+
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+
+    /* Disable IRQ & FIQ */
+    cpsid if
+
+    /* Check for HYP mode */
+    mrs r0, cpsr_all
+    and r0, r0, #0x1F
+    mov r8, #0x1A
+    cmp r0, r8
+    beq overHyped
+    b continue
+
+overHyped: /* Get out of HYP mode */
+    ldr r1, =continue
+    msr ELR_hyp, r1
+    mrs r1, cpsr_all
+    and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
+    orr r1, r1, #0x13    ;@ CPSR_MODE_SUPERVISOR
+    msr SPSR_hyp, r1
+    eret
+
+continue:
+
+    /* disable mmu */
+    bl      rt_cpu_mmu_disable
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+#ifdef RT_USING_SMP
+    mrc     p15, 0, r0, c0, c0, 5
+    ubfx    r0, r0, #0, #2
+    cmp     r0, #0
+    beq     1f
+    /* write boot indicate */
+    ldr     r5, = boot_indicate
+    str     r0, [r5, r0, lsl #2]
+    bl secondary_cpu_start
+    b .
+1:
+#endif
+    /* setup stack */
+#ifdef RT_USING_SMP
+    ldr     r0, =stack_top0
+#else
+    ldr     r0, =stack_top
+#endif
+    bl      stack_setup
+      
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+    bl rt_hw_init_mmu_table
+    bl init_mbox_mmu_map
+    bl rt_hw_mmu_init
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+.text
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+.globl      vmm_thread
+.globl      vmm_virq_check
+
+    .align  5
+.globl vector_irq
+vector_irq:
+#ifdef RT_USING_SMP
+    clrex
+      
+    stmfd   sp!, {r0, r1}
+    cps     #Mode_SVC
+    mov     r0, sp          /* svc_sp */
+    mov     r1, lr          /* svc_lr */
+
+    cps     #Mode_IRQ
+    sub     lr, lr, #4
+    stmfd   r0!, {r1, lr}       /* svc_lr, svc_pc */
+    stmfd   r0!, {r2 - r12}
+    ldmfd   sp!, {r1, r2}     /* original r0, r1 */
+    stmfd   r0!, {r1 - r2}
+    mrs     r1,  spsr         /* original mode */
+    stmfd   r0!, {r1}
+
+#ifdef RT_USING_LWP
+    stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
+    sub   r0, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb r0!, {d0-d15}
+    vstmdb r0!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd r0!, {r5}
+1:
+    stmfd r0!, {r6}
+#endif
+    mov     r8, r0
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+    
+    cps     #Mode_SVC
+    mov     sp, r8
+    mov     r0, r8
+    
+    bl      rt_scheduler_do_irq_switch
+
+    b       rt_hw_context_switch_exit
+
+#else
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
+    sub sp, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
+    add sp, #8
+#endif
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+#endif
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl  vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl  vector_undef
+vector_undef:
+    push_svc_reg
+    cps #Mode_UND
+    bl      rt_hw_trap_undef
+#ifdef RT_USING_FPU
+    ldr     lr, [sp, #15*4]
+    ldmia   sp, {r0 - r12}
+    add     sp, sp, #17 * 4
+    movs    pc, lr
+#endif
+    b       .
+
+    .align  5
+    .globl  vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl  vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl  vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
+
+#ifdef RT_USING_SMP
+
+.global secondary_cpu_start
+secondary_cpu_start:
+    /* set vector base */
+    mrc p15, 0, r0, c1, c0, 0        
+    bic r0, #(1<<13)
+    mcr p15, 0, r0, c1, c0, 0
+    
+    /* setup stack */
+    mrc p15, 0, r0, c0, c0, 5
+    ubfx    r0, r0, #0, #2
+    ldr r1, =stack_top0
+    ldr r2, =ISR_Stack_Size
+    mul r3, r2, r0
+    add r0, r1, r3
+    bl  stack_setup
+    /* initialize the mmu table and enable mmu */
+    bl  rt_hw_mmu_init
+    b   secondary_cpu_c_start
+
+#endif
+
+;@ void arm_smp_enable(void);
+.globl arm_smp_enable
+arm_smp_enable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
+    orr r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+/*
+    mrrc p15, 1, r0, r1, c15
+    orr r0, r0, #0x40
+    mcrr p15, 1, r0, r1, c15
+    dsb
+    isb
+    bx lr
+*/
+.text
+;@ void arm_smp_disable(void);
+.globl arm_smp_disable
+
+arm_smp_disable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
+    bic r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+/*
+    mrrc p15, 1, r0, r1, c15
+    bic r0, r0, #0x40
+    mcrr p15, 1, r0, r1, c15
+    bx lr
+*/
+

bsp/raspberry-pi/raspi3-32/cpu/trap.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <board.h>
+#include <rtthread.h>
+
+#include "armv7.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    uint32_t irq;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+    uint32_t value = 0;
+    value = IRQ_PEND_BASIC & 0x3ff;
+#ifdef RT_USING_SMP
+    uint32_t mailbox_data;
+    uint32_t cpu_id = rt_hw_cpu_id();
+    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
+    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
+    if (int_source & 0x0f)
+    {
+        if (int_source & 0x08)
+        {
+            isr_func = isr_table[IRQ_ARM_TIMER].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_TIMER].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_TIMER].param;
+                isr_func(IRQ_ARM_TIMER, param);
+            }
+        }
+    }
+    if (int_source & 0xf0)
+    {
+        /*it's a ipi interrupt*/
+        if (mailbox_data & 0x1)
+        {
+            /* clear mailbox */
+            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
+            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_MAILBOX].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_MAILBOX].param;
+                isr_func(IRQ_ARM_MAILBOX, param);
+            }
+        }
+        else 
+            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
+    }
+#endif
+    /* local interrupt*/
+    if (value)
+    {
+        if (value & (1 << 8))
+        {
+            value = IRQ_PEND1;
+            irq = __rt_ffs(value) - 1;
+        }
+        else if (value & (1 << 9))
+        {
+            value = IRQ_PEND2;
+            irq = __rt_ffs(value) + 31;
+        }
+        else
+        {
+            value &= 0x0f;
+            irq = __rt_ffs(value) + 63;
+        }
+
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+
+}

bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef

bsp/raspberry-pi/raspi3-32/driver/Kconfig

+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+
+                config RT_USING_UART1
+                    bool "Enabel UART 1"
+                    default n
+            endif
+         
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select RT_USING_HWTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C"
+            select RT_USING_I2C
+            default n
+
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default n
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+        endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI"
+            select RT_USING_SPI
+            default n
+        
+        if BSP_USING_SPI   
+            config BSP_USING_SPI0_BUS
+                bool "Enable SPI0 BUS"
+                default n
+            config BSP_USING_SPI0_DEVICE0
+                bool "Enable SPI0 DEVICE0"
+                select BSP_USING_SPI0_BUS
+                default n
+            config BSP_USING_SPI0_DEVICE1
+                bool "Enable SPI0 DEVICE1"
+                select BSP_USING_SPI0_BUS
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            select BSP_USING_SPI
+            default n
+    endmenu
+endmenu

bsp/raspberry-pi/raspi3-32/driver/SConscript

+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+drv_uart.c
+mbox.c
+''')
+CPPPATH = [cwd]
+
+if GetDepend('BSP_USING_SYSTIMER'):
+    src += ['drv_timer.c']
+if GetDepend('BSP_USING_PIN'):
+    src += ['drv_gpio.c']
+if GetDepend('BSP_USING_I2C'):
+    src += ['drv_i2c.c']
+if GetDepend('BSP_USING_WDT'):
+    src += ['drv_wdt.c']
+if GetDepend('BSP_USING_SPI'):
+    src += ['drv_spi.c']
+if GetDepend('BSP_USING_SDIO'):
+    src += ['drv_sdio.c']
+if GetDepend('BSP_USING_RTC'):
+    src += ['drv_rtc.c']
+if GetDepend('BSP_USING_HDMI'):
+    src += ['drv_fb.c']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/raspberry-pi/raspi3-32/driver/board.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_timer.h"
+
+#include "cp15.h"
+
+#ifdef RT_USING_SMP
+unsigned int cntfrq;
+#endif
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    rt_tick_increase();
+#ifndef RT_USING_SMP
+    ARM_TIMER_IRQCLR = 0;
+#else
+    mask_cntv();
+    __DSB();
+    write_cntv_tval(cntfrq);
+    __DSB();
+    unmask_cntv();
+    __DSB();
+#endif
+}
+
+int rt_hw_timer_init()
+{
+#ifndef RT_USING_SMP
+    /* timer_clock = apb_clock/(pre_divider + 1) */
+    ARM_TIMER_PREDIV = (250 - 1);
+
+    ARM_TIMER_RELOAD = 0;
+    ARM_TIMER_LOAD   = 0;
+    ARM_TIMER_IRQCLR = 0;
+    ARM_TIMER_CTRL   = 0;
+
+    ARM_TIMER_RELOAD = 10000;
+    ARM_TIMER_LOAD   = 10000;
+
+    /* 23-bit counter, enable interrupt, enable timer */
+    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+#else
+    __DSB();
+    cntfrq = 35000;
+    write_cntv_tval(cntfrq);
+    enable_cntv();
+    __DSB();
+    enable_cpu_timer_intr(rt_hw_cpu_id());
+#endif
+
+    rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IRQ_ARM_TIMER);
+    return 0;
+}
+#ifdef RT_USING_SMP
+extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
+
+void ipi_handler()
+{
+    rt_scheduler_ipi_handler(0,RT_NULL);
+}
+#endif
+void vector_copy(void)
+{
+    rt_memcpy((void*)0x0, (void*)0x8000, 64);
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+void rt_hw_board_init(void)
+{
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+    vector_copy();
+    rt_hw_vector_init();
+    /* initialize uart */
+    rt_hw_uart_init();
+    /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_SMP
+    /* install IPI handle */
+    rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, ipi_handler);
+    rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
+    enable_cpu_ipi_intr(0);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+}
+
+
+void _reset(void);
+void secondary_cpu_start(void);
+
+#ifdef RT_USING_SMP
+void rt_hw_secondary_cpu_up(void)
+{
+    int i;
+    int retry,val;
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    /*TODO maybe, there is some bug */
+    for (i = RT_CPUS_NR - 1; i>0; i-- )
+    {
+        rt_kprintf("boot cpu:%d\n", i);
+        setup_bootstrap_addr(i, (int)_reset);
+        __SEV();
+        __DSB();
+        __ISB();
+        retry = 10;
+        rt_thread_delay(RT_TICK_PER_SECOND/1000);
+        do
+        {
+            val = CORE_MAILBOX3_CLEAR(i);
+            if (val == 0)
+            {
+                rt_kprintf("start OK: CPU %d \n",i);
+                break;
+            }
+            rt_thread_delay(RT_TICK_PER_SECOND);
+
+            retry --;
+            if (retry <= 0)
+            {
+                rt_kprintf("can't start for CPU %d \n",i);
+                break;
+            }
+        } while (1);
+    }
+    __DSB();
+    __SEV();
+}
+
+void secondary_cpu_c_start(void)
+{
+    uint32_t id;
+    id = rt_hw_cpu_id();
+    rt_kprintf("cpu = 0x%08x\n",id);
+    rt_hw_timer_init();
+    rt_kprintf("cpu %d startup.\n",id);
+    rt_hw_vector_init();
+    enable_cpu_ipi_intr(id);
+    rt_hw_spin_lock(&_cpus_lock);
+    rt_system_scheduler_start();
+}
+
+void rt_hw_secondary_cpu_idle_exec(void)
+{
+    __WFE();
+}
+
+#endif
+
+

bsp/raspberry-pi/raspi3-32/driver/board.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+#include <rthw.h>
+#include  "raspi.h"
+
+#define __REG32 HWREG32
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/raspberry-pi/raspi3-32/driver/drv_fb.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "mbox.h"
+#include "drv_fb.h"
+#include "mmu.h"
+
+#define CHAR_W          8
+#define CHAR_H          12
+
+#define COLOR_DELTA     0.05
+static struct rt_hdmi_fb_device _hdmi;
+
+// https://github.com/xinu-os/xinu/blob/1789b7a50b5b73c2ea76ebd764c54a034097d04d/device/framebuffer_rpi/font.c
+unsigned char FONT[] = {
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'!'*/
+0x00, 0x14, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'"'*/
+0x00, 0x00, 0x14, 0x14, 0x3e, 0x14, 0x3e, 0x14, 0x14, 0x00, 0x00, 0x00, /*'#'*/
+0x00, 0x00, 0x08, 0x3c, 0x0a, 0x1c, 0x28, 0x1e, 0x08, 0x00, 0x00, 0x00, /*'$'*/
+0x00, 0x00, 0x06, 0x26, 0x10, 0x08, 0x04, 0x32, 0x30, 0x00, 0x00, 0x00, /*'%'*/
+0x00, 0x00, 0x1c, 0x02, 0x02, 0x04, 0x2a, 0x12, 0x2c, 0x00, 0x00, 0x00, /*'&'*/
+0x00, 0x18, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'''*/
+0x20, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x00, /*'('*/
+0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02, 0x00, /*')'*/
+0x00, 0x00, 0x00, 0x08, 0x2a, 0x1c, 0x2a, 0x08, 0x00, 0x00, 0x00, 0x00, /*'*'*/
+0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /*'+'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*','*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'-'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*'.'*/
+0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x00, 0x00, /*'/'*/
+0x00, 0x1c, 0x22, 0x32, 0x2a, 0x26, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'0'*/
+0x00, 0x08, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'1'*/
+0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'2'*/
+0x00, 0x1c, 0x22, 0x20, 0x18, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'3'*/
+0x00, 0x10, 0x18, 0x18, 0x14, 0x14, 0x3e, 0x10, 0x38, 0x00, 0x00, 0x00, /*'4'*/
+0x00, 0x3e, 0x02, 0x02, 0x1e, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'5'*/
+0x00, 0x18, 0x04, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'6'*/
+0x00, 0x3e, 0x22, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x00, 0x00, 0x00, /*'7'*/
+0x00, 0x1c, 0x22, 0x22, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'8'*/
+0x00, 0x1c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x10, 0x0c, 0x00, 0x00, 0x00, /*'9'*/
+0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*':'*/
+0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*';'*/
+0x00, 0x00, 0x00, 0x30, 0x0c, 0x03, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, /*'<'*/
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, /*'='*/
+0x00, 0x00, 0x00, 0x03, 0x0c, 0x30, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, /*'>'*/
+0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'?'*/
+0x00, 0x00, 0x1c, 0x22, 0x3a, 0x3a, 0x1a, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'@'*/
+0x00, 0x00, 0x08, 0x14, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x00, 0x00, 0x00, /*'A'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'B'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x02, 0x02, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'C'*/
+0x00, 0x00, 0x0e, 0x12, 0x22, 0x22, 0x22, 0x12, 0x0e, 0x00, 0x00, 0x00, /*'D'*/
+0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'E'*/
+0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'F'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x32, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'G'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'H'*/
+0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x00, /*'I'*/
+0x00, 0x00, 0x38, 0x20, 0x20, 0x20, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'J'*/
+0x00, 0x00, 0x22, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'K'*/
+0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'L'*/
+0x00, 0x00, 0x22, 0x36, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'M'*/
+0x00, 0x00, 0x22, 0x26, 0x26, 0x2a, 0x32, 0x32, 0x22, 0x00, 0x00, 0x00, /*'N'*/
+0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'O'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'P'*/
+0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x30, 0x00, 0x00, /*'Q'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'R'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x1c, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'S'*/
+0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'T'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'U'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'V'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x2a, 0x2a, 0x36, 0x22, 0x00, 0x00, 0x00, /*'W'*/
+0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x14, 0x22, 0x22, 0x00, 0x00, 0x00, /*'X'*/
+0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'Y'*/
+0x00, 0x00, 0x3e, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'Z'*/
+0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, /*'['*/
+0x02, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x00, 0x00, /*'\'*/
+0x0e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x0e, 0x00, /*']'*/
+0x00, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'^'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, /*'_'*/
+0x00, 0x0c, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'`'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'a'*/
+0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'b'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x02, 0x02, 0x3c, 0x00, 0x00, 0x00, /*'c'*/
+0x00, 0x20, 0x20, 0x20, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'d'*/
+0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x3e, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'e'*/
+0x00, 0x38, 0x04, 0x04, 0x1e, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, /*'f'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'g'*/
+0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'h'*/
+0x00, 0x08, 0x08, 0x00, 0x0c, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'i'*/
+0x00, 0x10, 0x10, 0x00, 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, /*'j'*/
+0x00, 0x02, 0x02, 0x02, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x00, 0x00, 0x00, /*'k'*/
+0x00, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'l'*/
+0x00, 0x00, 0x00, 0x00, 0x16, 0x2a, 0x2a, 0x2a, 0x22, 0x00, 0x00, 0x00, /*'m'*/
+0x00, 0x00, 0x00, 0x00, 0x1a, 0x26, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'n'*/
+0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'o'*/
+0x00, 0x00, 0x00, 0x00, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, /*'p'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x20, /*'q'*/
+0x00, 0x00, 0x00, 0x00, 0x1a, 0x06, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'r'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x1c, 0x20, 0x1e, 0x00, 0x00, 0x00, /*'s'*/
+0x00, 0x08, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x08, 0x30, 0x00, 0x00, 0x00, /*'t'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'u'*/
+0x00, 0x00, 0x00, 0x00, 0x36, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'v'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x2a, 0x2a, 0x2a, 0x14, 0x00, 0x00, 0x00, /*'w'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x14, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, /*'x'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'y'*/
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x10, 0x08, 0x04, 0x3e, 0x00, 0x00, 0x00, /*'z'*/
+0x20, 0x10, 0x10, 0x10, 0x10, 0x08, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00, /*'{'*/
+0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, /*'|'*/
+0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x04, 0x04, 0x04, 0x02, 0x00, /*'}'*/
+0x00, 0x04, 0x2a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'~'*/
+0x00, 0x00, 0x00, 0x08, 0x08, 0x14, 0x14, 0x22, 0x3e, 0x00, 0x00, 0x00, /*DEL*/
+};
+
+void newline(fb_t* fb)
+{
+    uint8_t* to;
+    uint8_t* from;
+    int i;
+    fb->y++;
+    fb->x = 0;
+
+    if (fb->y == (fb->height / CHAR_H))
+    {
+
+        to = (uint8_t*) fb->addr;
+        from = to + (CHAR_H * fb->pitch);
+
+        for (i = 0; i < ((fb->height - CHAR_H) * fb->pitch); i++)
+        {
+            *to++ = *from++;
+        }
+
+        uint32_t *addr = (uint32_t*) (fb->addr) + (fb->height - CHAR_H) * fb->width;
+
+        for (i = 0; i < (CHAR_H * fb->width); i++)
+        {
+            *addr++ = fb->back;
+        }
+
+        fb->y--;
+    }
+}
+
+void clear_line(fb_t *fb, const int line)
+{
+    int i;
+    uint32_t* addr;
+    if (line > fb->height / CHAR_H)
+    {
+        fb->y = 0;
+    }
+    else
+    {
+        fb->y = line;
+    }
+
+    fb->x = 0;
+
+    addr = (uint32_t*) (fb->addr + (line * CHAR_H * fb->depth * fb->width));
+    for (i = 0; i < (CHAR_H * fb->width); i++)
+    {
+        *addr++ = fb->back;
+    }
+
+}
+
+void clear(fb_t *fb, const uint32_t color)
+{
+
+    uint32_t *addr = (uint32_t*) fb->addr;
+    uint32_t i;
+    for (i = 0; i < (fb->height * fb->width); i++)
+    {
+        *addr++ = color;
+    }
+    fb->x = 0;
+    fb->y = 0;
+
+}
+
+void fb_draw_char(fb_t *fb, char s)
+{
+    unsigned char* addr = (unsigned char*) fb->addr;
+    unsigned char *glyph = (unsigned char*) FONT + (s) * 12;
+    // calculate the offset on screen
+    int offs = (fb->y * CHAR_H * fb->pitch) + (fb->x * (CHAR_W + 1) * 4);
+    // variables
+    int i, j, line, mask, bytesperline = (CHAR_W + 7) / 8;
+    // display a character
+    for (j = 0; j < CHAR_H; j++)
+    {
+        // display one row
+        line = offs;
+        mask = 1;
+        for (i = 0; i < CHAR_W; i++)
+        {
+            // if bit set, we use white color, otherwise black
+            *((unsigned int*) (addr + line)) = ((int) *glyph) & mask ? fb->fore : fb->back;
+            mask <<= 1;
+            line += 4;
+        }
+        // adjust to next line
+        glyph += bytesperline;
+        offs += fb->pitch;
+    }
+}
+
+void fb_print(fb_t *fb, char *s)
+{
+
+    // draw next character if it's not zero
+    while (*s)
+    {
+        // handle carrige return
+        if (*s == '\r')
+        {
+            fb->x = 0;
+        }
+        else if (*s == '\n')
+        {
+            newline(fb);
+        }
+        else if (*s == '\t')
+        {
+            fb->x = ((fb->x + 4) >> 2) << 2;
+        }
+        else if (*s == '\b')
+        {
+            if (fb->x)
+            {
+                fb->x--;
+                fb_draw_char(fb, ' ');
+            }
+        }
+        else
+        {
+            fb_draw_char(fb, *s);
+            fb->x++;
+        }
+        // next character
+        if (fb->x == fb->width / CHAR_W)
+        {
+            newline(fb);
+        }
+        s++;
+    }
+}
+
+rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+rt_err_t hdmi_fb_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
+{
+    return 0;
+}
+
+rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    fb_print(&_hdmi.fb, (char *) buffer);
+#ifdef BSP_USING_HDMI_DISPLAY
+    rt_device_t uart = rt_device_find("uart1");
+    int old_flag = uart->open_flag;
+    uart->open_flag |= RT_DEVICE_FLAG_STREAM;
+    rt_device_write(uart, 0, buffer, size);
+    uart->open_flag = old_flag;
+#endif
+    return size;
+}
+
+rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
+{
+    return RT_EOK;
+}
+
+const static struct rt_device_ops hdmi_fb_ops = 
+{
+    RT_NULL,
+    hdmi_fb_open,
+    hdmi_fb_close,
+    hdmi_fb_read,
+    hdmi_fb_write,
+    hdmi_fb_control
+};
+
+static struct rt_device_graphic_info _hdmi_info;
+
+static void hdmi_draw_rect(const char* pixel, int x1, int y1, int x2, int y2)
+{
+    int i, j;
+    int line;
+    for (j = y1; j <= y2; j++)
+    {
+        line = (j * _hdmi.fb.pitch) + (x1 * 4);
+        for (i = x1; i <= x2; i++)
+        {
+            // if bit set, we use white color, otherwise black
+            *((unsigned int*) (_hdmi_info.framebuffer + line)) = *(unsigned int*) pixel;
+            line += 4;
+        }
+    }
+
+}
+
+static void hdmi_set_pixel(const char* pixel, int x, int y)
+{
+    *(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) = *(uint32_t *) pixel;
+}
+
+static void hdmi_get_pixel(char* pixel, int x, int y)
+{
+    uint32_t ret = 0;
+    ret = (*(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) & 0x00FFFFFF);
+    *pixel = ret;
+}
+
+static void hdmi_draw_hline(const char* pixel, int x1, int x2, int y)
+{
+    hdmi_draw_rect(pixel, x1, y, x2, y);
+}
+
+static void hdmi_draw_vline(const char* pixel, int x, int y1, int y2)
+{
+    hdmi_draw_rect(pixel, x, y1, x, y2);
+}
+
+static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size)
+{
+    int i = 0;
+    uint32_t *pixel_base = (uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4));
+    uint32_t *colors = (uint32_t *) pixels;
+    for (i = 0; i < size; i++)
+    {
+        pixel_base[i] = colors[i];
+    }
+}
+
+static struct rt_device_graphic_ops hdmi_ops = 
+{
+    hdmi_set_pixel,
+    hdmi_get_pixel,
+    hdmi_draw_hline,
+    hdmi_draw_vline,
+    hdmi_blit_line
+};
+
+rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name)
+{
+    struct rt_device *device;
+    RT_ASSERT(hdmi_fb != RT_NULL);
+
+    device = &hdmi_fb->parent;
+    device->user_data = &hdmi_ops;
+
+    /* set device type */
+    device->type = RT_Device_Class_Graphic;
+    /* initialize device interface */
+#ifdef RT_USING_DEVICE_OPS
+    device->ops = &hdmi_fb_ops;
+#else
+    device->init = RT_NULL;
+    device->open = hdmi_fb_open;
+    device->close = hdmi_fb_close;
+    device->read = hdmi_fb_read;
+    device->write = hdmi_fb_write;
+    device->control = hdmi_fb_control;
+#endif
+
+    /* register to device manager */
+    rt_device_register(device, name, RT_DEVICE_FLAG_RDWR);
+
+    return RT_EOK;
+}
+
+/**
+ * Show a picture
+ */
+void print_fb_info()
+{
+    rt_kprintf("FrameBuffer Info: \n \t width %x\t height %x\t depth %x\t addr %x\t size %x\t \n", fb_info.width,
+            fb_info.height, fb_info.depth, fb_info.addr, fb_info.size);
+    rt_kprintf("call mbox:%x,%x,%x,%x,%x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4]);
+}
+
+void hdmi_fb_init()
+{
+    unsigned int *mbox = (unsigned int*) MBOX_ADDR;
+    mbox[0] = 35 * 4;
+    mbox[1] = MBOX_REQUEST;
+
+    mbox[2] = 0x48003;  //set phy wh
+    mbox[3] = 8;
+    mbox[4] = 8;
+    mbox[5] = 640;         //FrameBufferInfo.width
+    mbox[6] = 480;          //FrameBufferInfo.height
+
+    mbox[7] = 0x48004;  //set virt wh
+    mbox[8] = 8;
+    mbox[9] = 8;
+    mbox[10] = 640;        //FrameBufferInfo.virtual_width
+    mbox[11] = 480;         //FrameBufferInfo.virtual_height
+
+    mbox[12] = 0x48009; //set virt offset
+    mbox[13] = 8;
+    mbox[14] = 8;
+    mbox[15] = 0;           //FrameBufferInfo.x_offset
+    mbox[16] = 0;           //FrameBufferInfo.y.offset
+
+    mbox[17] = 0x48005; //set depth
+    mbox[18] = 4;
+    mbox[19] = 4;
+    mbox[20] = 32;          //FrameBufferInfo.depth
+
+    mbox[21] = 0x48006; //set pixel order
+    mbox[22] = 4;
+    mbox[23] = 4;
+    mbox[24] = 1;           //RGB, not BGR preferably
+
+    mbox[25] = 0x40001; //get framebuffer, gets alignment on request
+    mbox[26] = 8;
+    mbox[27] = 8;
+    mbox[28] = 4096;        //FrameBufferInfo.pointer
+    mbox[29] = 0;           //FrameBufferInfo.size
+
+    mbox[30] = 0x40008; //get pitch
+    mbox[31] = 4;
+    mbox[32] = 4;
+    mbox[33] = 0;           //FrameBufferInfo.pitch
+
+    mbox[34] = MBOX_TAG_LAST;
+    if (mbox_call(MBOX_CH_PROP, MMU_DISABLE) && mbox[20] == 32 && mbox[28] != 0)
+    {
+        mbox[28] &= 0x3FFFFFFF;
+        _hdmi.fb.width = mbox[5];
+        _hdmi.fb.height = mbox[6];
+        _hdmi.fb.pitch = mbox[33];
+        //_hdmi.fb.addr = (void*)((unsigned long)mbox[28]);
+        _hdmi.fb.addr = (rt_uint32_t) mbox[28];
+        _hdmi.fb.size = mbox[29];
+        _hdmi.fb.depth = 32;
+        _hdmi.fb.x = 0;
+        _hdmi.fb.y = 0;
+        _hdmi.fb.fore = CONSOLE_WHITE;
+        _hdmi.fb.back = CONSOLE_BLACK;
+        rt_hdmi_fb_device_init(&_hdmi, "hdmi");
+        rt_hw_change_mmu_table(_hdmi.fb.addr, _hdmi.fb.size, _hdmi.fb.addr, DEVICE_MEM);
+        fb_info.width = _hdmi.fb.width;
+        fb_info.height = _hdmi.fb.height;
+        fb_info.addr = _hdmi.fb.addr;
+        fb_info.size = _hdmi.fb.size;
+        fb_info.pitch = _hdmi.fb.pitch;
+        fb_info.depth = _hdmi.fb.depth;
+        _hdmi_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
+        _hdmi_info.bits_per_pixel = _hdmi.fb.depth;
+        _hdmi_info.width = _hdmi.fb.width;
+        _hdmi_info.height = _hdmi.fb.height;
+        _hdmi_info.framebuffer = (rt_uint8_t *) _hdmi.fb.addr;
+    }
+}
+
+INIT_DEVICE_EXPORT(hdmi_fb_init);

bsp/raspberry-pi/raspi3-32/driver/drv_fb.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+#ifndef __DRV_FB_H__
+#define __DRV_FB_H__
+
+#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
+
+#define COLOR_BLACK RGB(0, 0, 0)
+
+#define COLOR_GREEN RGB(0, 255, 0)  
+ 
+#define COLOR_CYAN RGB(0, 255, 255) 
+
+#define COLOR_RED RGB(255, 0, 0)  
+
+#define COLOR_YELLOW RGB(255, 255, 0) 
+
+#define COLOR_WHITE RGB(255, 255, 255)   
+
+#define CONSOLE_WHITE COLOR_WHITE
+#define CONSOLE_BLACK COLOR_BLACK
+#define CONSOLE_GREEN COLOR_GREEN
+#define CONSOLE_CYAN COLOR_CYAN
+#define CONSOLE_RED COLOR_RED
+#define CONSOLE_YELLOW COLOR_YELLOW
+
+typedef struct
+{
+    rt_uint32_t width;
+    rt_uint32_t height;
+    rt_uint32_t vwidth;
+    rt_uint32_t vheight;
+    rt_uint32_t pitch;
+    rt_uint32_t depth;
+    rt_uint32_t fore;
+    rt_uint32_t back;
+    rt_uint32_t x;
+    rt_uint32_t y;
+    rt_uint32_t addr;
+    rt_uint32_t size;
+} fb_t;
+
+struct rt_hdmi_fb_device
+{
+    struct rt_device parent;
+    fb_t fb;
+};
+
+fb_t fb_info;
+void print_fb_info();
+void hdmi_fb_init();
+
+#endif/* __DRV_FB_H__ */

bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+/*
+ * gpio_int[0] for BANK0 (pins 0-27)
+ * gpio_int[1] for BANK1 (pins 28-45)
+ * gpio_int[2] for BANK2 (pins 46-53)
+ */
+static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
+
+void gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud)
+{
+    rt_uint8_t num = pin / 32;
+    rt_uint8_t shift = pin % 32;
+    BCM283X_GPIO_GPPUD = pud;
+    DELAY_MICROS(10);
+    BCM283X_GPIO_GPPUDCLK(num) = 1 << shift;
+    DELAY_MICROS(10);
+    BCM283X_GPIO_GPPUD = BCM283X_GPIO_PUD_OFF;
+    BCM283X_GPIO_GPPUDCLK(num) = 0 << shift;
+}
+
+static void gpio_ack_irq(int irq, bcm_gpio_pin pin)
+{
+    rt_uint32_t data;
+    data = IRQ_PEND2;
+    data &= (0x0 << (irq - 32));
+    IRQ_PEND2 = data;
+
+    data = IRQ_DISABLE2;
+    data |= (0x1 << (irq - 32));
+    IRQ_DISABLE2 = data;
+}
+
+void gpio_irq_disable(rt_uint8_t index, bcm_gpio_pin pin)
+{
+    int irq = 0;
+    rt_uint32_t  reg_value;
+    rt_uint8_t irq_type;
+    irq = IRQ_GPIO0 + index;
+
+    gpio_ack_irq(irq, pin);
+
+    irq_type = _g_gpio_irq_tbl[index].irq_type[pin];
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t mask = 1 << shift;
+
+    switch (irq_type)
+    {
+    case PIN_IRQ_MODE_RISING:
+        reg_value = BCM283X_GPIO_GPREN(pin /32);
+        BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_FALLING:
+        reg_value = BCM283X_GPIO_GPFEN(pin /32);
+        BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_RISING_FALLING:
+        reg_value = BCM283X_GPIO_GPAREN(pin /32);
+        BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        reg_value = BCM283X_GPIO_GPAFEN(pin /32);
+        BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_HIGH_LEVEL:
+        reg_value = BCM283X_GPIO_GPHEN(pin /32);
+        BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_LOW_LEVEL:
+        reg_value = BCM283X_GPIO_GPLEN(pin /32);
+        BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    }
+}
+
+void gpio_irq_enable(rt_uint8_t index, bcm_gpio_pin pin)
+{
+    rt_uint32_t offset;
+    rt_uint32_t data;
+
+    offset = pin;
+    if (index == 0)
+        offset = IRQ_GPIO0 - 32;
+    else if (index == 1)
+        offset = IRQ_GPIO1 - 32;
+    else
+        offset = IRQ_GPIO2 - 32;
+
+    data = IRQ_ENABLE2;
+    data |= 0x1 << offset;
+    IRQ_ENABLE2 = data;
+
+}
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    RT_ASSERT(!(mode & 0x8));
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP);
+        break;
+    case PIN_MODE_INPUT:
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case PIN_MODE_INPUT_PULLUP:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case PIN_MODE_INPUT_PULLDOWN:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case PIN_MODE_OUTPUT_OD:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP);
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    RT_ASSERT(!(value & 0xE));
+
+    if (value)
+        BCM283X_GPIO_GPSET(pin / 32) |= (1 << (pin %32));
+    else
+        BCM283X_GPIO_GPCLR(pin / 32) |= (0 << (pin %32));
+
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+
+    rt_uint8_t index;
+    rt_uint32_t  reg_value;
+    if (pin <= 27)
+        index = 0;
+    else if (pin <= 45)
+        index = 1;
+    else
+        index = 2;
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = hdr;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = args;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = mode;
+
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t mask = 1 << shift;
+
+    switch (mode)
+    {
+    case PIN_IRQ_MODE_RISING:
+        reg_value = BCM283X_GPIO_GPREN(pin /32);
+        BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_FALLING:
+        reg_value = BCM283X_GPIO_GPFEN(pin /32);
+        BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_RISING_FALLING:
+        reg_value = BCM283X_GPIO_GPAREN(pin /32);
+        BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        reg_value = BCM283X_GPIO_GPAFEN(pin /32);
+        BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_HIGH_LEVEL:
+        reg_value = BCM283X_GPIO_GPHEN(pin /32);
+        BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_LOW_LEVEL:
+        reg_value = BCM283X_GPIO_GPLEN(pin /32);
+        BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+
+    rt_uint8_t index;
+    if (pin <= 27)
+        index = 0;
+    else if (pin <= 45)
+        index = 1;
+    else
+        index = 2;
+
+    gpio_irq_disable(index, pin);
+
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = RT_NULL;
+
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+
+    rt_uint8_t index;
+    if (pin <= 27)
+        index = 0;
+    else if (pin <= 45)
+        index = 1;
+    else
+        index = 2;
+
+    if (enabled)
+        gpio_irq_enable(index, pin);
+    else
+        gpio_irq_disable(index, pin);
+
+    return RT_EOK;
+}
+
+static void gpio_irq_handler(int irq, void *param)
+{
+    struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
+    rt_uint32_t pin;
+    rt_uint32_t value;
+    rt_uint32_t tmpvalue;
+
+    if (irq == IRQ_GPIO0)
+    {
+        /* 0~27 */
+
+        value = BCM283X_GPIO_GPEDS(0);
+        value &= 0x0fffffff;
+        pin = 0;
+        BCM283X_GPIO_GPEDS(0) = 0;
+    }
+    else if (irq == IRQ_GPIO1)
+    {
+        /* 28-45 */
+        tmpvalue = BCM283X_GPIO_GPEDS(0);
+        tmpvalue &= (~0x0fffffff);
+
+        value = BCM283X_GPIO_GPEDS(1);
+        value &= 0x3fff;
+        value = (value<<4) | tmpvalue;
+        pin = 28;
+        BCM283X_GPIO_GPEDS(0) = 0;
+        BCM283X_GPIO_GPEDS(1) = 0;
+    }
+    else if (irq == IRQ_GPIO2)
+    {
+        /* 46-53 */
+        value = BCM283X_GPIO_GPEDS(1);
+        value &= (~0x3fff);
+        value &= 0xff600000;
+        pin = 46;
+        BCM283X_GPIO_GPEDS(1) = 0;
+    }
+
+    while (value)
+    {
+        if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
+        {
+            irq_def->irq_cb[pin](irq_def->irq_arg[pin]);
+            gpio_ack_irq(irq,pin);
+        }
+        pin++;
+        value = value >> 1;
+    }
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+
+    /* install ISR */
+    rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO0);
+
+    rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO1);
+
+    rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO2);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);

bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "interrupt.h"
+#include "board.h"
+
+#define GPIO_IRQ_NUM 3
+
+#define IRQ_GPIO0               49
+#define IRQ_GPIO1               50
+#define IRQ_GPIO2               51
+#define IRQ_GPIO3               52
+
+struct gpio_irq_def
+{
+    void  *irq_arg[32];
+    void (*irq_cb[32])(void *param);
+    rt_uint8_t irq_type[32];
+};
+
+enum gpio_irq_clock
+{
+    GPIO_IRQ_LOSC_32KHZ = 0,
+    GPIO_IRQ_HOSC_24MHZ
+};
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */

bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_i2c.h"
+
+//Maybe redefined
+typedef unsigned long                   rt_ubase_t;
+typedef rt_ubase_t                      rt_size_t;
+
+rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
+{
+    rt_uint32_t status;
+    rt_uint32_t remaining = len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
+    /* Clear Status */
+    BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
+    /* Set Data Length */
+    BCM283X_BSC_DLEN(base) = len;
+    if (flag)
+    {
+        /* Start read */
+        BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
+        /* wait for transfer to complete */
+        while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
+        {
+            /* we must empty the FIFO as it is populated and not use any delay */
+            while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
+            {
+                /* Read from FIFO, no barrier */
+                buf[i] = BCM283X_BSC_FIFO(base);
+                i++;
+                remaining--;
+            }
+        }
+        /* transfer has finished - grab any remaining stuff in FIFO */
+        while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
+        {
+            /* Read from FIFO, no barrier */
+            buf[i] = BCM283X_BSC_FIFO(base);
+            i++;
+            remaining--;
+        }
+    }
+    else
+    {
+        /* pre populate FIFO with max buffer */
+        while (remaining && (i < BSC_FIFO_SIZE))
+        {
+            BCM283X_BSC_FIFO(base) = buf[i];
+            i++;
+            remaining--;
+        }
+
+        /* Enable device and start transfer */
+        BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
+
+        /* Transfer is over when BCM2835_BSC_S_DONE */
+        while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
+        {
+            while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD))
+            {
+                /* Write to FIFO */
+                BCM283X_BSC_FIFO(base) = buf[i];
+                i++;
+                remaining--;
+            }
+        }
+    }
+
+    status = BCM283X_BSC_S(base);
+    if (status & BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+    else if (status & BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+    BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
+
+    return reason;
+}
+
+struct raspi_i2c_hw_config
+{
+    rt_uint8_t bsc_num;
+    rt_uint8_t sdl_pin;
+    rt_uint8_t scl_pin;
+    rt_uint8_t sdl_mode;
+    rt_uint8_t scl_mode;
+};
+
+#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
+
+static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t,
+                                      rt_uint32_t);
+
+static rt_uint32_t i2c_byte_wait_us = 0;
+static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    rt_size_t i;
+    rt_uint8_t reason;
+    RT_ASSERT(bus != RT_NULL);
+
+    volatile rt_uint32_t base = (volatile rt_uint32_t)(bus->parent.user_data);
+
+    if (bus->addr == 0)
+        base = BCM283X_BSC0_BASE;
+    else
+        base = BCM283X_BSC1_BASE;
+
+    BCM283X_BSC_A(base) = msgs->addr;
+
+    for (i = 0; i < num; i++)
+    {
+        if (msgs[i].flags & RT_I2C_RD)
+            reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1);
+        else
+            reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0);
+    }
+    return (reason == 0)? i : 0;
+}
+
+static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    return 0;
+}
+static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t cmd,
+                                      rt_uint32_t arg)
+{
+    return RT_EOK;
+}
+
+static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
+{
+    .master_xfer = raspi_i2c_mst_xfer,
+    .slave_xfer = raspi_i2c_slv_xfer,
+    .i2c_bus_control = raspi_i2c_bus_control,
+};
+
+
+static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
+{
+    RT_ASSERT(cfg != RT_NULL);
+
+    volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE;
+
+    GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */
+    GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */
+
+    /* use 0xFFFE mask to limit a max value and round down any odd number */
+    rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE;
+    BCM283X_BSC_DIV(base) = (rt_uint16_t) divider;
+    i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
+
+    return RT_EOK;
+}
+#endif
+
+#if defined (BSP_USING_I2C0)
+#define I2C0_BUS_NAME    "i2c0"
+static struct raspi_i2c_hw_config hw_device0 =
+{
+    .bsc_num = 0,
+    .sdl_pin = RPI_GPIO_P1_27,
+    .scl_pin = RPI_GPIO_P1_28,
+    .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
+    .scl_mode = BCM283X_GPIO_FSEL_ALT0,
+};
+
+struct rt_i2c_bus_device device0 =
+{
+    .ops = &raspi_i2c_ops,
+    .addr = 0,
+};
+
+#endif
+
+#if defined (BSP_USING_I2C1)
+#define I2C1_BUS_NAME    "i2c1"
+static struct raspi_i2c_hw_config hw_device1 =
+{
+    .bsc_num = 1,
+    .sdl_pin = RPI_GPIO_P1_03,
+    .scl_pin = RPI_GPIO_P1_05,
+    .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
+    .scl_mode = BCM283X_GPIO_FSEL_ALT0,
+};
+struct rt_i2c_bus_device device1 =
+{
+    .ops = &raspi_i2c_ops,
+    .addr = 1,
+};
+
+#endif
+
+int rt_hw_i2c_init(void)
+{
+#if defined(BSP_USING_I2C0)
+    raspi_i2c_configure(&hw_device0);
+    rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
+#endif
+
+#if defined(BSP_USING_I2C1)
+    raspi_i2c_configure(&hw_device1);
+    rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);

bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+struct raspi_master_config_t
+{
+    rt_uint8_t sdl_pin;
+    rt_uint8_t scl_pin;
+    rt_uint8_t sdl_pin_mode;
+    rt_uint8_t scl_pin_mode;
+    rt_uint8_t slave_address;
+    rt_uint32_t bsc_base;
+    rt_uint16_t clk_div;
+};
+
+struct raspi_i2c_bus
+{
+    struct rt_i2c_bus_device device;
+    struct rt_i2c_msg *msg;
+    rt_uint32_t msg_cnt;
+    volatile rt_uint32_t msg_ptr;
+    volatile rt_uint32_t dptr;
+    char *device_name;
+    struct raspi_master_config_t *cfg;
+};
+
+int rt_hw_i2c_init(void);
+
+#endif

bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_rtc.h"
+
+#ifdef BSP_USING_RTC
+
+#define RTC_I2C_BUS_NAME      "i2c0"
+#define RTC_ADDR            0x68
+
+static struct rt_device rtc_device;
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+rt_uint8_t buf[]=
+{
+    0x00, 0x00, 0x43, 0x15, 0x05, 0x01, 0x03, 0x19
+};
+
+
+rt_uint8_t i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len)
+{
+    rt_uint32_t remaining = cmds_len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
+
+    /* Clear Status */
+    BCM283X_BSC_S(BCM283X_BSC0_BASE) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
+
+    /* Set Data Length */
+    BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = cmds_len;
+
+    /* pre populate FIFO with max buffer */
+    while (remaining && (i < BSC_FIFO_SIZE))
+    {
+        BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = cmds[i];
+        i++;
+        remaining--;
+    }
+
+    /* Enable device and start transfer */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) |= BSC_C_I2CEN | BSC_C_ST;
+
+    /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */
+    while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_TA))
+    {
+        /* Linux may cause us to miss entire transfer stage */
+        if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE)
+            break;
+    }
+
+    remaining = buf_len;
+    i = 0;
+
+    /* Send a repeated start with read bit set in address */
+    BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = buf_len;
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_C_I2CEN | BSC_C_ST  | BSC_C_READ;
+
+    /* Wait for write to complete and first byte back. */
+  //  DELAYMICROS(i2c_byte_wait_us * (cmds_len + 1));
+
+    /* wait for transfer to complete */
+    while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE))
+    {
+        /* we must empty the FIFO as it is populated and not use any delay */
+        while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_RXD))
+        {
+        /* Read from FIFO, no barrier */
+        buf[i] = BCM283X_BSC_FIFO(BCM283X_BSC0_BASE);
+        i++;
+        remaining--;
+        }
+    }
+
+    /* transfer has finished - grab any remaining stuff in FIFO */
+    while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_RXD))
+    {
+        /* Read from FIFO */
+        buf[i] = BCM283X_BSC_FIFO(BCM283X_BSC0_BASE);
+        i++;
+        remaining--;
+    }
+
+    /* Received a NACK */
+    if (BCM283X_BSC_S(BCM283X_BSC0_BASE)  & BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is sent */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = (BSC_S_DONE &BSC_S_DONE);
+
+    return reason;
+}
+
+rt_uint8_t i2c_write(rt_uint8_t* buf, rt_uint32_t len)
+{
+    rt_uint32_t remaining = len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE)  |= BSC_C_CLEAR_1 & BSC_C_CLEAR_1;
+    /* Clear Status */
+    BCM283X_BSC_S(BCM283X_BSC0_BASE) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
+    /* Set Data Length */
+    BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = len;
+    /* pre populate FIFO with max buffer */
+    while (remaining && (i < BSC_FIFO_SIZE))
+    {
+        BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = buf[i];
+        i++;
+        remaining--;
+    }
+
+    /* Enable device and start transfer */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_C_I2CEN | BSC_C_ST;
+
+    /* Transfer is over when BCM2835_BSC_S_DONE */
+    while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE))
+    {
+        while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_TXD))
+        {
+        /* Write to FIFO */
+        BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = buf[i];
+        i++;
+        remaining--;
+        }
+    }
+
+    /* Received a NACK */
+    if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is sent */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_S_DONE & BSC_S_DONE;
+    return reason;
+}
+
+
+static time_t raspi_get_timestamp(void)
+{
+    struct tm tm_new = {0};
+    buf[0] = 0;
+
+    i2c_write_read_rs((char*)buf, 1, (char*)buf, 7);
+
+    tm_new.tm_year = ((buf[6] / 16) + 0x30) * 10 + (buf[6] % 16) + 0x30;
+    tm_new.tm_mon  = ((buf[5] & 0x1F) / 16 + 0x30) + (buf[5] & 0x1F) % 16+ 0x30;
+    tm_new.tm_mday = ((buf[4] & 0x3F) / 16 + 0x30) + (buf[4] & 0x3F) % 16+ 0x30;
+    tm_new.tm_hour = ((buf[2] & 0x3F) / 16 + 0x30) + (buf[2] & 0x3F) % 16+ 0x30;
+    tm_new.tm_min  = ((buf[1] & 0x7F) / 16 + 0x30) + (buf[1] & 0x7F) % 16+ 0x30;
+    tm_new.tm_sec  = ((buf[0] & 0x7F) / 16 + 0x30) + (buf[0] & 0x7F) % 16+ 0x30;
+
+    return mktime(&tm_new);
+}
+
+static int raspi_set_timestamp(time_t timestamp)
+{
+    struct tm *tblock;
+    tblock = localtime(&timestamp);
+    buf[0] = 0;
+    buf[1] = tblock->tm_sec;
+    buf[2] = tblock->tm_min;
+    buf[3] = tblock->tm_hour;
+    buf[4] = tblock->tm_wday;
+    buf[5] = tblock->tm_mday;
+    buf[6] = tblock->tm_mon;
+    buf[7] = tblock->tm_year;
+
+    i2c_write(buf, 8);
+
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_init(rt_device_t dev)
+{
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(RTC_I2C_BUS_NAME);
+    raspi_set_timestamp(0);
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    GPIO_FSEL(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */
+    GPIO_FSEL(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_close(rt_device_t dev)
+{
+    GPIO_FSEL(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */
+    GPIO_FSEL(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = raspi_get_timestamp();
+        break;
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        raspi_set_timestamp(*(time_t *)args);
+        break;
+    default:
+        return RT_EINVAL;
+    }
+    return RT_EOK;
+}
+
+static rt_size_t raspi_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer);
+    return size;
+}
+
+static rt_size_t raspi_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer);
+    return size;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops raspi_rtc_ops =
+{
+    .init = raspi_rtc_init,
+    .open = raspi_rtc_open,
+    .close = raspi_rtc_close,
+    .read = raspi_rtc_read,
+    .write = raspi_rtc_write,
+    .control = raspi_rtc_control
+};
+#endif
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    rtc_device.type        = RT_Device_Class_RTC;
+    rtc_device.rx_indicate = RT_NULL;
+    rtc_device.tx_complete = RT_NULL;
+
+#ifdef RT_USING_DEVICE_OPS
+    rtc_device.ops        = &raspi_rtc_ops;
+#else
+    rtc_device.init    = raspi_rtc_init;
+    rtc_device.open    = raspi_rtc_open;
+    rtc_device.close   = raspi_rtc_close;
+    rtc_device.read    = raspi_rtc_read;
+    rtc_device.write   = raspi_rtc_write;
+    rtc_device.control = raspi_rtc_control;
+#endif
+
+    rtc_device.user_data   = RT_NULL;
+
+    /* register a rtc device */
+    ret = rt_device_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif /* BSP_USING_RTC */
+

bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_RTC_H__
+#define __DRV_RTC_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+
+int rt_hw_rtc_init(void);
+
+#endif

bsp/raspberry-pi/raspi3-64/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')