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提交 eb5e940d 编写于 作者: M magicoe@163.com
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added bsp/lpc122x & libcpu/arm/lpc122x 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1234 bbd45198-f89e-11dd-88c7-29a3b14d5316
上级 ba507951
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bsp/lpc122x/FLASH.ini 0 → 100644
浏览文件 @ eb5e940d
/***********************************************************************/
/* This file is part of the ARM Compiler package */
/* Copyright KEIL ELEKTRONIK GmbH 1992-2004 */
/***********************************************************************/
/* */
/* RAM.INI: RAM Initialization File */
/* */
/***********************************************************************/
//*** <<< Use Configuration Wizard in Context Menu >>> ***
FUNC void Pre_Setup (void) {
_WDWORD(0x40048000, 0x00000002); // MEMMAP = 2
}
FUNC void Setup (void) {
SP = _RDWORD(0x00000000);
PC = _RDWORD(0x00000004);
}
Pre_Setup();
LOAD .\Obj\gpiotest.axf INCREMENTAL // Download
Setup(); // Setup for Running
// g, main
bsp/lpc122x/application.c 0 → 100644
浏览文件 @ eb5e940d
/*
* File : app.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*
*/
/**
* @addtogroup LPC122x
*/
/*@{*/
#include <rtthread.h>
#include "tc_comm.h"
/*
* This is an example for delay thread
*/
static struct rt_thread thread;
static char thread_stack[THREAD_STACK_SIZE];
static void thread_entry(void* parameter)
{
rt_tick_t tick;
rt_kprintf("thread inited ok\n");
tick = rt_tick_get();
rt_kprintf("thread tick %d\n", tick);
rt_kprintf("thread delay 10 tick\n");
rt_thread_delay(10);
if (rt_tick_get() - tick > 10)
{
tc_done(TC_STAT_FAILED);
return;
}
tick = rt_tick_get();
rt_kprintf("thread delay 15 tick\n");
rt_thread_delay(15);
if (rt_tick_get() - tick > 15)
{
tc_done(TC_STAT_FAILED);
return;
}
rt_kprintf("thread exit\n");
tc_done(TC_STAT_PASSED);
}
rt_err_t thread_delay_init()
{
rt_err_t result;
result = rt_thread_init(&thread,
"test",
thread_entry, RT_NULL,
&thread_stack[0], sizeof(thread_stack),
THREAD_PRIORITY, 10);
if (result == RT_EOK)
rt_thread_startup(&thread);
else
tc_stat(TC_STAT_END | TC_STAT_FAILED);
return result;
}
int rt_application_init()
{
thread_delay_init();
return 0;
}
/*@}*/
bsp/lpc122x/board.c 0 → 100644
浏览文件 @ eb5e940d
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "uart.h"
#include <CMSIS/LPC122x.h>
#include <CMSIS/core_cm0.h>
#define SYSTICK_DELAY 0x0007A11F
/**
* @addtogroup LPC122x
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler()
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial sam7s64 board.
*/
void rt_hw_board_init()
{
SystemInit();
/* init systick */
SysTick_Config( SYSTICK_DELAY );
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_UART
/* init hardware UART device */
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device("uart0");
#endif
}
/*@}*/
bsp/lpc122x/board.h 0 → 100644
浏览文件 @ eb5e940d
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_init(void);
#endif
bsp/lpc122x/lpc122x.uvopt 0 → 100644
浏览文件 @ eb5e940d
此差异已折叠。
bsp/lpc122x/lpc122x.uvproj 0 → 100644
浏览文件 @ eb5e940d
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>RT-Thread LPC122x</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>Cortex-M0</Device>
<Vendor>ARM</Vendor>
<Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>4803</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\obj\</OutputDirectory>
<OutputName>lpc122x</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\lst\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments></SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments></TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>.\FLASH.ini</InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>5</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>1</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IRAM>
<IROM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x2000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>2</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.;..\..\include;..\..\libcpu\arm\lpc122x;</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x00000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Startup</GroupName>
<Files>
<File>
<FileName>application.c</FileName>
<FileType>1</FileType>
<FilePath>.\application.c</FilePath>
</File>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>.\board.c</FilePath>
</File>
<File>
<FileName>startup.c</FileName>
<FileType>1</FileType>
<FilePath>.\startup.c</FilePath>
</File>
<File>
<FileName>board.h</FileName>
<FileType>5</FileType>
<FilePath>.\board.h</FilePath>
</File>
<File>
<FileName>rtconfig.h</FileName>
<FileType>5</FileType>
<FilePath>.\rtconfig.h</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>.\uart.c</FilePath>
</File>
<File>
<FileName>tc_comm.c</FileName>
<FileType>1</FileType>
<FilePath>.\tc_comm.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\device.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>module.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\module.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\object.c</FilePath>
</File>
<File>
<FileName>rtm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\rtm.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>slab.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\slab.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\thread.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>LPC122x</GroupName>
<Files>
<File>
<FileName>cpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\cpu.c</FilePath>
</File>
<File>
<FileName>fault.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\fault.c</FilePath>
</File>
<File>
<FileName>interrupt.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\interrupt.c</FilePath>
</File>
<File>
<FileName>stack.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\stack.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\context_rvds.S</FilePath>
</File>
<File>
<FileName>fault_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\fault_rvds.S</FilePath>
</File>
<File>
<FileName>start_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\start_rvds.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CMSIS</GroupName>
<Files>
<File>
<FileName>system_LPC122x.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\CMSIS\system_LPC122x.c</FilePath>
</File>
<File>
<FileName>core_cm0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\lpc122x\CMSIS\core_cm0.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>
bsp/lpc122x/lpc122x_RT-Thread LPC122x.dep 0 → 100644
浏览文件 @ eb5e940d
Dependencies for Project 'lpc122x', Target 'RT-Thread LPC122x': (DO NOT MODIFY !)
F (.\application.c)(0x4D1946C4)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\application.o" --omf_browse ".\obj\application.crf" --depend ".\obj\application.d")
F (.\board.c)(0x4D0D98D5)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\board.o" --omf_browse ".\obj\board.crf" --depend ".\obj\board.d")
F (.\startup.c)(0x4D0AFB31)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\startup.o" --omf_browse ".\obj\startup.crf" --depend ".\obj\startup.d")
F (.\board.h)(0x4C68E915)()
F (.\rtconfig.h)(0x4C68E915)()
F (.\uart.c)(0x4D0AFCCD)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\uart.o" --omf_browse ".\obj\uart.crf" --depend ".\obj\uart.d")
F (.\tc_comm.c)(0x4D0B09A8)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\tc_comm.o" --omf_browse ".\obj\tc_comm.crf" --depend ".\obj\tc_comm.d")
F (..\..\src\clock.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\clock.o" --omf_browse ".\obj\clock.crf" --depend ".\obj\clock.d")
F (..\..\src\device.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\device.o" --omf_browse ".\obj\device.crf" --depend ".\obj\device.d")
F (..\..\src\idle.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\idle.o" --omf_browse ".\obj\idle.crf" --depend ".\obj\idle.d")
F (..\..\src\ipc.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\ipc.o" --omf_browse ".\obj\ipc.crf" --depend ".\obj\ipc.d")
F (..\..\src\irq.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\irq.o" --omf_browse ".\obj\irq.crf" --depend ".\obj\irq.d")
F (..\..\src\kservice.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\kservice.o" --omf_browse ".\obj\kservice.crf" --depend ".\obj\kservice.d")
F (..\..\src\mem.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\mem.o" --omf_browse ".\obj\mem.crf" --depend ".\obj\mem.d")
F (..\..\src\mempool.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\mempool.o" --omf_browse ".\obj\mempool.crf" --depend ".\obj\mempool.d")
F (..\..\src\module.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\module.o" --omf_browse ".\obj\module.crf" --depend ".\obj\module.d")
F (..\..\src\object.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\object.o" --omf_browse ".\obj\object.crf" --depend ".\obj\object.d")
F (..\..\src\rtm.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\rtm.o" --omf_browse ".\obj\rtm.crf" --depend ".\obj\rtm.d")
F (..\..\src\scheduler.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\scheduler.o" --omf_browse ".\obj\scheduler.crf" --depend ".\obj\scheduler.d")
F (..\..\src\slab.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\slab.o" --omf_browse ".\obj\slab.crf" --depend ".\obj\slab.d")
F (..\..\src\thread.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\thread.o" --omf_browse ".\obj\thread.crf" --depend ".\obj\thread.d")
F (..\..\src\timer.c)(0x00000000)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\timer.o" --omf_browse ".\obj\timer.crf" --depend ".\obj\timer.d")
F (..\..\libcpu\arm\lpc122x\cpu.c)(0x4C68E9AB)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\cpu.o" --omf_browse ".\obj\cpu.crf" --depend ".\obj\cpu.d")
F (..\..\libcpu\arm\lpc122x\fault.c)(0x4C68E9AB)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\fault.o" --omf_browse ".\obj\fault.crf" --depend ".\obj\fault.d")
F (..\..\libcpu\arm\lpc122x\interrupt.c)(0x4C68E9AB)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\interrupt.o" --omf_browse ".\obj\interrupt.crf" --depend ".\obj\interrupt.d")
F (..\..\libcpu\arm\lpc122x\stack.c)(0x4C68E9AB)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\stack.o" --omf_browse ".\obj\stack.crf" --depend ".\obj\stack.d")
F (..\..\libcpu\arm\lpc122x\context_rvds.S)(0x4C68E9AB)(--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" --list ".\lst\context_rvds.lst" --xref -o ".\obj\context_rvds.o" --depend ".\obj\context_rvds.d")
F (..\..\libcpu\arm\lpc122x\fault_rvds.S)(0x4C68E9AB)(--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" --list ".\lst\fault_rvds.lst" --xref -o ".\obj\fault_rvds.o" --depend ".\obj\fault_rvds.d")
F (..\..\libcpu\arm\lpc122x\start_rvds.S)(0x4D0B0B6D)(--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" --list ".\lst\start_rvds.lst" --xref -o ".\obj\start_rvds.o" --depend ".\obj\start_rvds.d")
F (..\..\libcpu\arm\lpc122x\CMSIS\system_LPC122x.c)(0x4CEE18A0)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\system_lpc122x.o" --omf_browse ".\obj\system_lpc122x.crf" --depend ".\obj\system_lpc122x.d")
F (..\..\libcpu\arm\lpc122x\CMSIS\core_cm0.c)(0x4C68E9AB)(-c --cpu Cortex-M0 -D__MICROLIB --li -g -O1 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\core_cm0.o" --omf_browse ".\obj\core_cm0.crf" --depend ".\obj\core_cm0.d")
bsp/lpc122x/lpc122x_uvopt.bak 0 → 100644
浏览文件 @ eb5e940d
此差异已折叠。
bsp/lpc122x/obj/lpc122x.plg 0 → 100644
浏览文件 @ eb5e940d
<html>
<body>
<pre>
<h1>Vision Build Log</h1>
<h2>Project:</h2>
E:\SVNĿ\rt_thread_lpc1227\bsp\lpc122x\lpc122x.uvproj
Project File Date: 12/17/2010
<h2>Output:</h2>
bsp/lpc122x/obj/lpc122x.sct 0 → 100644
浏览文件 @ eb5e940d
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00008000 { ; load region size_region
ER_IROM1 0x00000000 0x00008000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x10000000 UNINIT 0x00002000 { ; RW data
.ANY (+RW +ZI)
}
}
bsp/lpc122x/obj/lpc122x.tra 0 → 100644
浏览文件 @ eb5e940d
*** Creating Trace Output File '.\obj\lpc122x.tra' Ok.
### Preparing for ADS-LD.
### Creating ADS-LD Command Line
### List of Objects: adding '".\obj\application.o"'
### List of Objects: adding '".\obj\board.o"'
### List of Objects: adding '".\obj\startup.o"'
### List of Objects: adding '".\obj\uart.o"'
### List of Objects: adding '".\obj\tc_comm.o"'
### List of Objects: adding '".\obj\clock.o"'
### List of Objects: adding '".\obj\device.o"'
### List of Objects: adding '".\obj\idle.o"'
### List of Objects: adding '".\obj\ipc.o"'
### List of Objects: adding '".\obj\irq.o"'
### List of Objects: adding '".\obj\kservice.o"'
### List of Objects: adding '".\obj\mem.o"'
### List of Objects: adding '".\obj\mempool.o"'
### List of Objects: adding '".\obj\module.o"'
### List of Objects: adding '".\obj\object.o"'
### List of Objects: adding '".\obj\rtm.o"'
### List of Objects: adding '".\obj\scheduler.o"'
### List of Objects: adding '".\obj\slab.o"'
### List of Objects: adding '".\obj\thread.o"'
### List of Objects: adding '".\obj\timer.o"'
### List of Objects: adding '".\obj\cpu.o"'
### List of Objects: adding '".\obj\fault.o"'
### List of Objects: adding '".\obj\interrupt.o"'
### List of Objects: adding '".\obj\stack.o"'
### List of Objects: adding '".\obj\context_rvds.o"'
### List of Objects: adding '".\obj\fault_rvds.o"'
### List of Objects: adding '".\obj\start_rvds.o"'
### List of Objects: adding '".\obj\system_lpc122x.o"'
### List of Objects: adding '".\obj\core_cm0.o"'
### ADS-LD Command completed:
--cpu Cortex-M0 ".\obj\application.o" ".\obj\board.o" ".\obj\startup.o" ".\obj\uart.o" ".\obj\tc_comm.o" ".\obj\clock.o" ".\obj\device.o" ".\obj\idle.o" ".\obj\ipc.o" ".\obj\irq.o" ".\obj\kservice.o" ".\obj\mem.o" ".\obj\mempool.o" ".\obj\module.o" ".\obj\object.o" ".\obj\rtm.o" ".\obj\scheduler.o" ".\obj\slab.o" ".\obj\thread.o" ".\obj\timer.o" ".\obj\cpu.o" ".\obj\fault.o" ".\obj\interrupt.o" ".\obj\stack.o" ".\obj\context_rvds.o" ".\obj\fault_rvds.o" ".\obj\start_rvds.o" ".\obj\system_lpc122x.o" ".\obj\core_cm0.o" --library_type=microlib --strict --scatter ".\obj\lpc122x.sct"
--autoat --summary_stderr --info summarysizes --map --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\lst\lpc122x.map" -o ".\obj\lpc122x.axf"### Preparing Environment (PrepEnvAds)
### ADS-LD Output File: '.\obj\lpc122x.axf'
### ADS-LD Command File: '.\obj\lpc122x.lnp'
### Checking for dirty Components...
### Creating CmdFile '.\obj\lpc122x.lnp', Handle=0x000002B4
### Writing '.lnp' file
### ADS-LD Command file '.\obj\lpc122x.lnp' is ready.
### ADS-LD: About to start ADS-LD Thread.
### ADS-LD: executed with 0 errors
### Updating obj list
### LDADS_file() completed.
bsp/lpc122x/obj/lpc122x_uart.__i 0 → 100644
浏览文件 @ eb5e940d
-c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork -I. -I..\..\include -I..\..\libcpu\arm\lpc122x -I.\peripheral -I "F:\Program Files\KEIL\ARM\INC" -I "F:\Program Files\KEIL\ARM\INC\ARM" -o ".\obj\lpc122x_uart.o" --omf_browse ".\obj\lpc122x_uart.crf" --depend ".\obj\lpc122x_uart.d" "peripheral\lpc122x_uart.c"
\ No newline at end of file
bsp/lpc122x/obj/lpc122x_uart.d 0 → 100644
浏览文件 @ eb5e940d
.\obj\lpc122x_uart.o: peripheral\lpc122x_uart.c
.\obj\lpc122x_uart.o: ..\..\include\rthw.h
.\obj\lpc122x_uart.o: ..\..\include\rtthread.h
.\obj\lpc122x_uart.o: ..\..\include\rtdef.h
.\obj\lpc122x_uart.o: .\rtconfig.h
.\obj\lpc122x_uart.o: F:\Program Files\KEIL\ARM\RV31\INC\stdarg.h
.\obj\lpc122x_uart.o: ..\..\libcpu\arm\lpc122x\CMSIS/LPC122x.h
.\obj\lpc122x_uart.o: ..\..\libcpu\arm\lpc122x\CMSIS/core_cm0.h
.\obj\lpc122x_uart.o: F:\Program Files\KEIL\ARM\RV31\INC\stdint.h
.\obj\lpc122x_uart.o: ..\..\libcpu\arm\lpc122x\CMSIS/system_LPC122x.h
.\obj\lpc122x_uart.o: peripheral\lpc122x_uart.h
bsp/lpc122x/rtconfig.h 0 → 100644
浏览文件 @ eb5e940d
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 4
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
#define RT_THREAD_PRIORITY_MAX 8
/* Tick per Second*/
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug*/
/* #define RT_THREAD_DEBUG */
/* Using Hook*/
/* #define RT_USING_HOOK */
/* SECTION: IPC */
/* Using Semaphore*/
#define RT_USING_SEMAPHORE
/* Using Mutex*/
/* #define RT_USING_MUTEX */
/* Using Event*/
/* #define RT_USING_EVENT */
/* Using MailBox*/
#define RT_USING_MAILBOX
/* Using Message Queue*/
/* #define RT_USING_MESSAGEQUEUE */
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
/* #define RT_USING_MEMPOOL */
/* Using Dynamic Heap Management*/
/* #define RT_USING_HEAP */
/* Using Small MM*/
#define RT_USING_SMALL_MEM
#define RT_USING_TINY_SIZE
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
/* buffer size for UART reception */
#define RT_UART_RX_BUFFER_SIZE 64
/* Using UART */
#define RT_USING_UART
/* SECTION: Console options */
/* use console for rt_kprintf */
#define RT_USING_CONSOLE
/* the buffer size of console */
#define RT_CONSOLEBUF_SIZE 80
#endif
bsp/lpc122x/startup.c 0 → 100644
浏览文件 @ eb5e940d
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#ifdef RT_USING_UART
#include "uart.h"
#endif
/**
* @addtogroup sam7s
*/
/*@{*/
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#endif
#ifdef __GNUC__
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#endif
extern void rt_hw_interrupt_init(void);
extern int rt_application_init(void);
#ifdef RT_USING_DEVICE
extern rt_err_t rt_hw_serial_init(void);
#endif
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init kernel object */
rt_system_object_init();
/* init board */
rt_hw_board_init();
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_HOOK /* if the hook is used */
/* set idle thread hook */
rt_thread_idle_sethook(rt_hw_led_flash);
#endif
#ifdef RT_USING_DEVICE
/* init all device */
rt_device_init_all();
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main (void)
{
rt_uint32_t UNUSED level;
/* disable interrupt first */
level = rt_hw_interrupt_disable();
/* invoke rtthread_startup */
rtthread_startup();
return 0;
}
/*@}*/
bsp/lpc122x/tc_comm.c 0 → 100644
浏览文件 @ eb5e940d
#include "tc_comm.h"
#ifdef RT_USING_TC
#define TC_PRIORITY 25
#define TC_STACK_SIZE 0x400
static rt_uint8_t _tc_stat;
static struct rt_semaphore _tc_sem;
static struct rt_thread _tc_thread;
static rt_uint8_t _tc_stack[TC_STACK_SIZE];
static char _tc_prefix[64];
static const char* _tc_current;
static void (*_tc_cleanup)(void) = RT_NULL;
static rt_uint32_t _tc_scale = 1;
FINSH_VAR_EXPORT(_tc_scale, finsh_type_int, the testcase timer timeout scale)
void tc_thread_entry(void* parameter)
{
struct finsh_syscall* index;
/* create tc semaphore */
rt_sem_init(&_tc_sem, "tc", 0, RT_IPC_FLAG_FIFO);
while (_tc_stat & TC_STAT_RUNNING)
{
for (index = _syscall_table_begin; index < _syscall_table_end; index ++)
{
/* search testcase */
if (rt_strstr(index->name, _tc_prefix) == index->name)
{
long tick;
_tc_current = index->name + 4;
rt_kprintf("Run TestCase: %s\n", _tc_current);
_tc_stat = TC_STAT_PASSED | TC_STAT_RUNNING;
tick = index->func();
if (tick > 0)
{
rt_sem_take(&_tc_sem, tick * _tc_scale);
if (_tc_cleanup != RT_NULL)
{
/* perform testcase cleanup */
_tc_cleanup();
_tc_cleanup = RT_NULL;
}
if (_tc_stat & TC_STAT_FAILED)
rt_kprintf("TestCase[%s] failed\n", _tc_current);
else
rt_kprintf("TestCase[%s] passed\n", _tc_current);
}
else
{
if (_tc_cleanup != RT_NULL)
{
/* perform testcase cleanup */
_tc_cleanup();
_tc_cleanup = RT_NULL;
}
}
}
}
}
/* detach tc semaphore */
rt_sem_detach(&_tc_sem);
}
void tc_stop()
{
_tc_stat &= ~TC_STAT_RUNNING;
rt_thread_delay(RT_TICK_PER_SECOND/2);
if (_tc_thread.stat != RT_THREAD_INIT)
{
/* lock scheduler */
rt_enter_critical();
/* detach old tc thread */
rt_thread_detach(&_tc_thread);
rt_sem_detach(&_tc_sem);
/* unlock scheduler */
rt_exit_critical();
}
rt_thread_delay(RT_TICK_PER_SECOND/2);
}
FINSH_FUNCTION_EXPORT(tc_stop, stop testcase thread);
void tc_done(rt_uint8_t stat)
{
_tc_stat |= stat;
_tc_stat &= ~TC_STAT_RUNNING;
/* release semaphore */
rt_sem_release(&_tc_sem);
}
void tc_stat(rt_uint8_t stat)
{
if (stat & TC_STAT_FAILED)
{
rt_kprintf("TestCases[%s] failed\n", _tc_current);
}
_tc_stat |= stat;
}
void tc_cleanup(void (*cleanup)())
{
_tc_cleanup = cleanup;
}
void tc_start(const char* tc_prefix)
{
rt_err_t result;
/* tesecase prefix is null */
if (tc_prefix == RT_NULL)
{
rt_kprintf("TestCase Usage: tc_start(prefix)\n\n");
rt_kprintf("list_tc() can list all testcases.\n");
return ;
}
/* init tc thread */
if (_tc_stat & TC_STAT_RUNNING)
{
/* stop old tc thread */
tc_stop();
}
rt_memset(_tc_prefix, 0, sizeof(_tc_prefix));
rt_snprintf(_tc_prefix, sizeof(_tc_prefix),
"_tc_%s", tc_prefix);
result = rt_thread_init(&_tc_thread, "tc",
tc_thread_entry, RT_NULL,
&_tc_stack[0], sizeof(_tc_stack),
TC_PRIORITY - 3, 5);
/* set tc stat */
_tc_stat = TC_STAT_RUNNING | TC_STAT_FAILED;
if (result == RT_EOK)
rt_thread_startup(&_tc_thread);
}
FINSH_FUNCTION_EXPORT(tc_start, start testcase with testcase prefix or name);
void list_tc()
{
struct finsh_syscall* index;
rt_kprintf("TestCases List:\n");
for (index = _syscall_table_begin; index < _syscall_table_end; index ++)
{
/* search testcase */
if (rt_strstr(index->name, "_tc_") == index->name)
{
#ifdef FINSH_USING_DESCRIPTION
rt_kprintf("%-16s -- %s\n", index->name + 4, index->desc);
#else
rt_kprintf("%s\n", index->name + 4);
#endif
}
}
}
FINSH_FUNCTION_EXPORT(list_tc, list all testcases);
#endif
bsp/lpc122x/tc_comm.h 0 → 100644
浏览文件 @ eb5e940d
#ifndef __TC_COMM_H__
#define __TC_COMM_H__
/*
* RT-Thread TestCase
*
*/
#include <rtthread.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
#if RT_THREAD_PRIORITY_MAX == 8
#define THREAD_PRIORITY 6
#elif RT_THREAD_PRIORITY_MAX == 32
#define THREAD_PRIORITY 25
#elif RT_THREAD_PRIORITY_MAX == 256
#define THREAD_PRIORITY 200
#endif
#define THREAD_STACK_SIZE 512
#define THREAD_TIMESLICE 5
#define TC_STAT_END 0x00
#define TC_STAT_RUNNING 0x01
#define TC_STAT_FAILED 0x10
#define TC_STAT_PASSED 0x00
#ifdef RT_USING_TC
void tc_start(const char* tc_prefix);
void tc_stop(void);
void tc_done(rt_uint8_t state);
void tc_stat(rt_uint8_t state);
void tc_cleanup(void (*cleanup)(void));
#else
#define tc_start(x)
#define tc_stop()
#define tc_done(s)
#define tc_stat(s)
#define tc_cleanup(c)
#endif
#endif
bsp/lpc122x/uart.c 0 → 100644
浏览文件 @ eb5e940d
/****************************************************************************
* $Id:: uart.c 3736 2010-06-24 02:07:03Z usb00423 $
* Project: NXP LPC122x UART example
*
* Description:
* This file contains UART code example which include UART
* initialization, UART interrupt handler, and related APIs for
* UART access.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#include <rthw.h>
#include <rtthread.h>
#include <CMSIS/LPC122x.h>
#include "uart.h"
#define IER_RBR 0x01
#define IER_THRE 0x02
#define IER_RLS 0x04
#define IIR_PEND 0x01
#define IIR_RLS 0x03
#define IIR_RDA 0x02
#define IIR_CTI 0x06
#define IIR_THRE 0x01
#define LSR_RDR 0x01
#define LSR_OE 0x02
#define LSR_PE 0x04
#define LSR_FE 0x08
#define LSR_BI 0x10
#define LSR_THRE 0x20
#define LSR_TEMT 0x40
#define LSR_RXFE 0x80
/**
* @addtogroup LPC11xx
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
#define UART_BAUDRATE 115200
struct rt_uart_lpc
{
struct rt_device parent;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
struct rt_uart_lpc* uart = &uart_device;
/* read IIR and clear it */
iir = LPC_UART0->IIR;
iir >>= 0x01; /* skip pending bit in IIR */
iir &= 0x07; /* check bit 1~3, interrupt identification */
if (iir == IIR_RDA) /* Receive Line Status */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
uart->rx_buffer[uart->save_index] = LPC_UART0->RBR;
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
/*****************************************************************************
** Function name: rt_uart_init
** Descriptions:
** parameters: dev
** Returned value: None
*****************************************************************************/
static rt_err_t rt_uart_init(rt_device_t dev)
{
rt_uint32_t Fdiv;
rt_uint32_t regVal;
NVIC_DisableIRQ(UART0_IRQn);
/* Init UART Hardware */
LPC_IOCON->PIO0_1 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_1 |= 0x02; /* UART RXD */
LPC_IOCON->PIO0_2 &= ~0x07;
LPC_IOCON->PIO0_2 |= 0x02; /* UART TXD */
/* Enable UART clock */
LPC_SYSCON->PRESETCTRL |= (0x1<<2);
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<12);
LPC_SYSCON->UART0CLKDIV = 0x1; /* divided by 1 */
LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
regVal = LPC_SYSCON->UART0CLKDIV;
Fdiv = ((SystemAHBFrequency/regVal)/16)/UART_BAUDRATE ; /*baud rate */
LPC_UART0->DLM = Fdiv / 256;
LPC_UART0->DLL = Fdiv % 256;
LPC_UART0->LCR = 0x03; /* DLAB = 0 */
LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
/* Read to clear the line status. */
regVal = LPC_UART0->LSR;
/* Ensure a clean start, no data in either TX or RX FIFO. */
while ( LPC_UART0->LSR & (LSR_THRE|LSR_TEMT) != (LSR_THRE|LSR_TEMT) );
while ( LPC_UART0->LSR & LSR_RDR )
{
regVal = LPC_UART0->RBR; /* Dump data from RX FIFO */
}
/* Enable the UART Interrupt */
NVIC_EnableIRQ(UART0_IRQn);
LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
if(dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
NVIC_EnableIRQ(UART0_IRQn);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
NVIC_DisableIRQ(UART0_IRQn);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
char *ptr;
ptr = (char*)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* THRE status, contain valid data */
while ( !(LPC_UART0->LSR & LSR_THRE) );
/* write data */
LPC_UART0->THR = '\r';
}
/* THRE status, contain valid data */
while ( !(LPC_UART0->LSR & LSR_THRE) );
/* write data */
LPC_UART0->THR = *ptr;
ptr ++;
size --;
}
}
else
{
while ( size != 0 )
{
/* THRE status, contain valid data */
while ( !(LPC_UART0->LSR & LSR_THRE) );
/* write data */
LPC_UART0->THR = *ptr;
ptr++;
size--;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_lpc* uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
}
#endif
/******************************************************************************
** End Of File
******************************************************************************/
bsp/lpc122x/uart.h 0 → 100644
浏览文件 @ eb5e940d
#ifndef __UART_H__
#define __UART_H__
void rt_hw_uart_init(void);
#endif
libcpu/arm/lpc122x/CMSIS/LPC122x.h 0 → 100644
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libcpu/arm/lpc122x/CMSIS/core_cm0.c 0 → 100644
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libcpu/arm/lpc122x/CMSIS/core_cm0.h 0 → 100644
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libcpu/arm/lpc122x/CMSIS/startup_LPC122x.s 0 → 100644
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libcpu/arm/lpc122x/CMSIS/system_LPC122x.c 0 → 100644
浏览文件 @ eb5e940d
/******************************************************************************
* @file: system_LPC122x.c
* @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the NXP LPC122x Device Series
* @version: V1.0
* @date: 26. Nov. 2008
*----------------------------------------------------------------------------
*
* Copyright (C) 2008 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC122x.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Controls and Status Register (SCS)
// <o1.4> OSCRANGE: Main Oscillator Range Select
// <0=> 1 MHz to 20 MHz
// <1=> 15 MHz to 24 MHz
// <e1.5> OSCEN: Main Oscillator Enable
// </e>
// </h>
//
// <h> Clock Source Select Register (CLKSRCSEL)
// <o2.0..1> CLKSRC: PLL Clock Source Selection
// <0=> Internal RC oscillator
// <1=> Main oscillator
// <2=> RTC oscillator
// </h>
//
// <e3> PLL0 Configuration (Main PLL)
// <h> PLL0 Configuration Register (PLL0CFG)
// <i> F_cco0 = (2 * M * F_in) / N
// <i> F_in must be in the range of 32 kHz to 50 MHz
// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
// <o4.0..14> MSEL: PLL Multiplier Selection
// <6-32768><#-1>
// <i> M Value
// <o4.16..23> NSEL: PLL Divider Selection
// <1-256><#-1>
// <i> N Value
// </h>
// </e>
//
//
// <h> CPU Clock Configuration Register (CCLKCFG)
// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
// <0-255>
// <i> Divide is CCLKSEL + 1. Only 0 and odd values are valid.
// </h>
//
//
// </e>
*/
#define CLOCK_SETUP 1
#define SYS_PLL_SETUP 1
#define SYS_PLLSRCSEL_Val 0x00000001
#define SYS_PLL_M_Val 0x00000003
#define SYS_PLL_P_Val 0x00000001
#define MAIN_CLKSRCSEL_Val 0x00000003
#define SYS_AHB_DIV_Val 0x01 /* 1 through 255, 0 will disable the output. */
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (12000000UL) /* Oscillator frequency */
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
#define WDT_OSC ( 250000UL) /* WDT oscillator frequency */
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t ClockSource = IRC_OSC;
uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */
uint32_t SystemAHBFrequency = IRC_OSC;
/**
* Misc. clock generation modules
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
void SystemPLL_Setup ( void )
{
uint32_t regVal;
LPC_SYSCON->PRESETCTRL &= ~0x00008000; /* Disable 1-Cycle Read Mode */
ClockSource = OSC_CLK;
LPC_SYSCON->SYSPLLCLKSEL = SYS_PLLSRCSEL_Val; /* Select system OSC */
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update clock source */
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* toggle Update register once */
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
while ( !(LPC_SYSCON->SYSPLLCLKUEN & 0x01) ); /* Wait until updated */
regVal = LPC_SYSCON->SYSPLLCTRL;
regVal &= ~0x1FF;
LPC_SYSCON->SYSPLLCTRL = (regVal | (SYS_PLL_P_Val<<5) | SYS_PLL_M_Val);
/* Enable main system clock, main system clock bit 7 in PDRUNCFG. */
LPC_SYSCON->PDRUNCFG &= ~(0x1<<7);
while ( !(LPC_SYSCON->SYSPLLSTAT & 0x01) ); /* Wait until it's locked */
LPC_SYSCON->MAINCLKSEL = MAIN_CLKSRCSEL_Val; /* Select PLL clock output */
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK clock source */
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle update register once */
LPC_SYSCON->MAINCLKUEN = 0x01;
while ( !(LPC_SYSCON->MAINCLKUEN & 0x01) ); /* Wait until updated */
LPC_SYSCON->SYSAHBCLKDIV = SYS_AHB_DIV_Val; /* SYS AHB clock, 0 will disable output */
#if SYS_PLL_SETUP
/* If the SYS PLL output is selected as the main clock. Even if SYS PLL is
configured and enabled, it doesn't mean it will be selected as the MAIN clock
source. Be careful with MAINCLKSEL value. If SYS PLL is not selected, System
Frequence should be the same as either IRC, external OSC(SYS), or WDT OSC clock. */
SystemFrequency = ClockSource * (SYS_PLL_M_Val+1);
#else
SystemFrequency = ClockSource;
#endif
SystemAHBFrequency = (uint32_t)(SystemFrequency/SYS_AHB_DIV_Val);
return;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
void SystemInit (void)
{
uint32_t i;
#ifdef __DEBUG_RAM
LPC_SYSCON->SYSMEMREMAP = 0x1; /* remap to internal RAM */
#else
#ifdef __DEBUG_FLASH
LPC_SYSCON->SYSMEMREMAP = 0x2; /* remap to internal flash */
#endif
#endif
#if 1
/* First, below lines are for debugging only. For future release, WDT is
enabled by bootrom, thus, unless a feed to WDT continuously, or WDT timeout
will occur. If it's happen, WDT interrupt will be pending until a INT_CLEAR
is applied. Below logic is to prevent system from going to the WDT interrupt
during debugging.
Second, all the peripheral clocks seem to be enabled by bootrom, it's
not consistent with the UM. In below lines, only SYS, ROM, RAM, FLASHREG,
FLASHARRAY, and I2C are enabled per UM dated July 14th. */
LPC_WDT->MOD = 0x00;
LPC_WDT->FEED = 0xAA; /* Feeding sequence */
LPC_WDT->FEED = 0x55;
NVIC->ICPR[0] |= 0xFFFFFFFF;
LPC_SYSCON->SYSAHBCLKCTRL = 0x00000001F;
#endif
#if (CLOCK_SETUP) /* Clock Setup */
/* bit 0 default is crystal bypass,
bit1 0=0~20Mhz crystal input, 1=15~50Mhz crystal input. */
LPC_SYSCON->SYSOSCCTRL = 0x00;
/* main system OSC run is cleared, bit 5 in PDRUNCFG register */
LPC_SYSCON->PDRUNCFG &= ~(0x1<<5);
/* Wait 200us for OSC to be stablized, no status
indication, dummy wait. */
for ( i = 0; i < 0x100; i++ );
#if (SYS_PLL_SETUP)
SystemPLL_Setup();
#endif
#endif /* endif CLOCK_SETUP */
/* System clock to the IOCON needs to be enabled or
most of the I/O related peripherals won't work. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
return;
}
libcpu/arm/lpc122x/CMSIS/system_LPC122x.h 0 → 100644
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libcpu/arm/lpc122x/context_rvds.S 0 → 100644
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libcpu/arm/lpc122x/cpu.c 0 → 100644
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libcpu/arm/lpc122x/fault.c 0 → 100644
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libcpu/arm/lpc122x/fault_rvds.S 0 → 100644
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libcpu/arm/lpc122x/stack.c 0 → 100644
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libcpu/arm/lpc122x/start_rvds.S 0 → 100644
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