Merge pull request #5280 from liukangcc/u575

[update] add stm32u575-st-nucleo bsp.

.github/workflows/action.yml

@@ -131,6 +131,7 @@ jobs:
          - {RTT_BSP: "stm32/stm32l552-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32u575-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/stm32/README.md

@@ -75,6 +75,8 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32l496-st-nucleo](stm32l496-st-nucleo) | ST 官方 STM32L496-Nucleo 开发板 |
 | **L5 系列** |  |
 | [stm32l552-st-nucleo](stm32l552-st-nucleo) | ST 官方 STM32L552-Nucleo 开发板 |
+| **U5 系列** |  |
+| [stm32u575-st-nucleo](stm32u575-st-nucleo) | ST 官方 STM32U575ZI-Nucleo 开发板 |
 | **MP1 系列** |  |
 | [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
 | [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |

bsp/stm32/libraries/.ignore_format.yml

@@ -17,5 +17,6 @@ dir_path:
 - STM32L4xx_HAL
 - STM32L5xx_HAL
 - STM32MPxx_HAL
+- STM32U5xx_HAL
 - STM32WBxx_HAL
 - STM32WLxx_HAL

bsp/stm32/libraries/HAL_Drivers/config/u5/adc_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/dac_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/dma_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ * 2019-12-01     armink       add DMAMUX support
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_SPI1_RX
+#else /* for L4 */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#else /* for L4 */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#if defined(DMAMUX1) /* for L4+ */
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_USART3_RX
+#else /* for L4 */
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_USART1_TX
+#else /* for L4 */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_SPI2_RX
+#else /* for L4 */
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#else /* for L4 */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA1_Channel5_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA1EN
+#define QSPI_DMA_INSTANCE               DMA1_Channel5
+#if defined(DMAMUX1) /* for L4+ */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_OCTOSPI1
+#else /* for L4 */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_5
+#endif /* DMAMUX1 */
+#define QSPI_DMA_IRQ                    DMA1_Channel5_IRQn
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_SPI2_TX
+#else /* for L4 */
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#if defined(DMAMUX1) /* for L4+ */
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX
+#else /* for L4 */
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler         DMA1_Channel7_IRQHandler
+#define UART2_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE           DMA1_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define UART2_TX_DMA_REQUEST            DMA_REQUEST_USART2_TX
+#else /* for L4 */
+#define UART2_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART2_TX_DMA_IRQ                DMA1_Channel7_IRQn
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART5_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_TX_DMA_INSTANCE           DMA2_Channel1
+#if defined(DMAMUX1) /* for L4+ */
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_UART5_TX
+#else /* for L4 */
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART5_TX_DMA_IRQ                DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
+#define SPI3_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI3_TX_DMA_INSTANCE            DMA2_Channel2
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI3_TX_DMA_REQUEST             DMA_REQUEST_SPI3_TX
+#else /* for L4 */
+#define SPI3_TX_DMA_REQUEST             DMA_REQUEST_3
+#endif /* DMAMUX1 */
+#define SPI3_TX_DMA_IRQ                 DMA2_Channel2_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART5_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_RX_DMA_INSTANCE           DMA2_Channel2
+#if defined(DMAMUX1) /* for L4+ */
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_UART5_RX
+#else /* for L4 */
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART5_RX_DMA_IRQ                DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA2_Channel3_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE            DMA2_Channel3
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_SPI1_RX
+#else /* for L4 */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_4
+#endif /* DMAMUX1 */
+#define SPI1_RX_DMA_IRQ                 DMA2_Channel3_IRQn
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA2_Channel4_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE            DMA2_Channel4
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#else /* for L4 */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_4
+#endif /* DMAMUX1 */
+#define SPI1_TX_DMA_IRQ                 DMA2_Channel4_IRQn
+#endif
+
+/* DMA2 channel5 */
+
+/* DMA2 channel6 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Channel6
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_USART1_TX
+#else /* for L4 */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#else /* for L4 */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA2_Channel7_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE               DMA2_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_OCTOSPI1
+#else /* for L4 */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_3
+#endif /* DMAMUX1 */
+#define QSPI_DMA_IRQ                    DMA2_Channel7_IRQn
+#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA2_Channel7_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHB1ENR_DMA2EN
+#define LPUART1_RX_DMA_INSTANCE         DMA2_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#else /* for L4 */
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_4
+#endif /* DMAMUX1 */
+#define LPUART1_RX_DMA_IRQ              DMA2_Channel7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/pwm_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/qspi_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Request = QSPI_DMA_REQUEST,                      \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/sdio_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32u5xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.request = DMA_REQUEST_7,                 \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel5,                \
+        .dma_tx.request = DMA_REQUEST_7,                 \
+        .dma_tx.dma_irq = DMA2_Channel5_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/u5/spi_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI1,                                   \
+        .bus_name = "spi1",                                 \
+        .irq_type = SPI1_IRQn,                      \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_TX_DMA_RCC,                         \
+        .Instance = SPI1_TX_DMA_INSTANCE,                   \
+        .request = SPI1_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_RX_DMA_RCC,                         \
+        .Instance = SPI1_RX_DMA_INSTANCE,                   \
+        .request = SPI1_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI2,                                   \
+        .bus_name = "spi2",                                 \
+        .irq_type = SPI2_IRQn,                      \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_TX_DMA_RCC,                         \
+        .Instance = SPI2_TX_DMA_INSTANCE,                   \
+        .request = SPI2_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_RX_DMA_RCC,                         \
+        .Instance = SPI2_RX_DMA_INSTANCE,                   \
+        .request = SPI2_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI3,                                   \
+        .bus_name = "spi3",                                 \
+        .irq_type = SPI3_IRQn,                      \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_TX_DMA_RCC,                         \
+        .Instance = SPI3_TX_DMA_INSTANCE,                   \
+        .request = SPI3_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_RX_DMA_RCC,                         \
+        .Instance = SPI3_RX_DMA_INSTANCE,                   \
+        .request = SPI3_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/tim_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-12     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/u5/uart_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .request  = UART1_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/u5/usbd_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_config.h

@@ -124,6 +124,17 @@ extern "C" {
 #include "h7/sdio_config.h"
 #include "h7/pwm_config.h"
 #include "h7/usbd_config.h"
+#elif defined(SOC_SERIES_STM32U5)
+#include "u5/dma_config.h"
+#include "u5/uart_config.h"
+#include "u5/spi_config.h"
+#include "u5/qspi_config.h"
+#include "u5/adc_config.h"
+#include "u5/dac_config.h"
+#include "u5/tim_config.h"
+#include "u5/sdio_config.h"
+#include "u5/pwm_config.h"
+#include "u5/usbd_config.h"
 #elif  defined(SOC_SERIES_STM32MP1)
 #include "mp1/dma_config.h"
 #include "mp1/uart_config.h"

bsp/stm32/libraries/HAL_Drivers/drv_dma.h

@@ -20,7 +20,9 @@ extern "C" {
 #endif
 
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\
-    || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
+    || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
+    || defined(SOC_SERIES_STM32U5)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
     || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)

bsp/stm32/libraries/HAL_Drivers/drv_gpio.c

@@ -84,7 +84,7 @@ static const struct pin_irq_map pin_irq_map[] =
     {GPIO_PIN_13, EXTI4_15_IRQn},
     {GPIO_PIN_14, EXTI4_15_IRQn},
     {GPIO_PIN_15, EXTI4_15_IRQn},
-#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5)
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5)
     {GPIO_PIN_0, EXTI0_IRQn},
     {GPIO_PIN_1, EXTI1_IRQn},
     {GPIO_PIN_2, EXTI2_IRQn},
@@ -567,7 +567,7 @@ void EXTI4_15_IRQHandler(void)
     rt_interrupt_leave();
 }
 
-#elif defined(SOC_STM32MP157A)
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5)
 void EXTI0_IRQHandler(void)
 {
     rt_interrupt_enter();

bsp/stm32/libraries/HAL_Drivers/drv_usart.c

@@ -307,7 +307,8 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
     UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
-    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)  \
+    || defined(SOC_SERIES_STM32U5)
     uart->handle.Instance->TDR = c;
 #else
     uart->handle.Instance->DR = c;
@@ -328,7 +329,8 @@ static int stm32_getc(struct rt_serial_device *serial)
     {
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
-    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
+    || defined(SOC_SERIES_STM32U5)
         ch = uart->handle.Instance->RDR & stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
 #else
         ch = uart->handle.Instance->DR & stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
@@ -432,7 +434,7 @@ static void uart_isr(struct rt_serial_device *serial)
 #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
     && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
     && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
-    && !defined(SOC_SERIES_STM32L5)
+    && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5)
 #ifdef SOC_SERIES_STM32F3
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
         {
@@ -967,7 +969,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
     }
 
-#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5)
     DMA_Handle->Instance                 = dma_config->Instance;
 #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     DMA_Handle->Instance                 = dma_config->Instance;

bsp/stm32/libraries/HAL_Drivers/drv_usart.h

@@ -31,7 +31,7 @@ int rt_hw_usart_init(void);
 
 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \
     || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
-    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5)
 #define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
 #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
     || defined(SOC_SERIES_STM32MP1)

bsp/stm32/libraries/Kconfig

@@ -66,6 +66,11 @@ config SOC_SERIES_STM32H7
     select ARCH_ARM_CORTEX_M7
     select SOC_FAMILY_STM32
 
+config SOC_SERIES_STM32U5
+    bool
+    select ARCH_ARM_CORTEX_M33
+    select SOC_FAMILY_STM32
+
 config SOC_SERIES_STM32MP1
     bool
     select ARCH_ARM_CORTEX_M4

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h

+/**
+  ******************************************************************************
+  * @file    partition_stm32u5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32U5xx Device Header File for Initial Setup for
+  *          Secure / Non-Secure Zones based on CMSIS CORE V5.4.0
+  *
+  *          The file is included in system_stm32u5xx_s.c in secure application.
+  *          It includes the configuration section that allows to select the
+  *          STM32U5xx device partitioning file for system core secure attributes
+  *          and interrupt secure and non-secure assignment.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32u5xx
+  * @{
+  */
+
+#ifndef PARTITION_STM32U5XX_H
+#define PARTITION_STM32U5XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Secure_configuration_section
+  * @{
+  */
+
+#if defined(STM32U575xx)
+  #include "partition_stm32u575xx.h"
+#elif defined(STM32U585xx)
+  #include "partition_stm32u585xx.h"
+#else
+  #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* PARTITION_STM32U5XX_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h

+/**
+  ******************************************************************************
+  * @file    stm32u5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32U5xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32U5xx device used in the target application
+  *              - To use or not the peripherals drivers in application code(i.e.
+  *                code will be based on direct access to peripherals registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32u5xx
+  * @{
+  */
+
+#ifndef STM32U5xx_H
+#define STM32U5xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32U5)
+#define STM32U5
+#endif /* STM32U5 */
+
+/* Uncomment the line below according to the target STM32U5 device used in your
+   application
+  */
+
+#if !defined (STM32U575xx)  && !defined (STM32U585xx)
+  /* #define STM32U575xx  */   /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices  */
+  /* #define STM32U585xx  */   /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices  */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number 1.0.0
+  */
+#define __STM32U5_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32U5_CMSIS_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32U5_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32U5_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32U5_CMSIS_VERSION        ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
+                                       |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
+                                       |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\
+                                       |(__STM32U5_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32U575xx)
+  #include "stm32u575xx.h"
+#elif defined(STM32U585xx)
+  #include "stm32u585xx.h"
+#else
+ #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32u5xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32U5xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h

+/**
+  ******************************************************************************
+  * @file    system_stm32u5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device System Source File for STM32U5xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32u5xx_system
+  * @{
+  */
+
+#ifndef SYSTEM_STM32U5XX_H
+#define SYSTEM_STM32U5XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32U5xx_System_Includes
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32U5xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+   */
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[16];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32U5xx_System_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief Setup the microcontroller system.
+  *
+  * Initialize the System and update the SystemCoreClock variable.
+  */
+extern void SystemInit (void);
+
+
+/**
+  * @brief  Update SystemCoreClock variable.
+  *
+  * Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+  */
+extern void SystemCoreClockUpdate (void);
+
+
+/**
+  * @brief Update SystemCoreClock variable from secure application and return its value
+  *        when security is implemented in the system (Non-secure callable function).
+  *
+  * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
+  */
+extern uint32_t SECURE_SystemCoreClockUpdate(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32U5XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/LICENSE.md

+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright [2021] [name of copyright owner]
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/LICENSE.txt

+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply. 
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/README.md

+# STM32CubeU5 CMSIS Device MCU Component
+
+![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_u5.svg?color=brightgreen)
+
+## Overview
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+   * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+   * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+   * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
+   * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
+
+Two models of publication are proposed for the STM32Cube embedded software:
+   * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+   * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
+   
+## Description
+
+This **cmsis_device_u5** MCU component repo is one element of the STM32CubeU5 MCU embedded software package, providing the **cmsis device** part.
+
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_u5/blob/main/Release_Notes.html).
+
+## Compatibility information
+
+In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
+
+CMSIS Device U5 | CMSIS Core      | Was delivered in the full MCU package
+--------------- | --------------- | -------------------------------------
+Tag v1.0.0      | Tag v5.6.0_cm33 | Tag v1.0.0 (and following, if any, till next CMSIS tag)
+Tag v1.0.1      | Tag v5.6.0_cm33 | Tag v1.0.1 (and following, if any, till next CMSIS tag)
+
+
+The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5).
+
+## Troubleshooting
+
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Release_Notes.html

+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for STM32U5xx CMSIS</title>
+  <style type="text/css">
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
+  <!--[if lt IE 9]>
+    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+  <![endif]-->
+  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<center>
+<h1 id="release-notes-for-stm32u5xx-cmsis">Release Notes for <mark> STM32U5xx CMSIS </mark></h1>
+<p>Copyright © 2021 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+</center>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.0.1 / 01-October-2021</strong></label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define</li>
+<li>Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define</li>
+<li>Add LSI_STARTUP_TIME define</li>
+<li>Fix wrong IRQn name in partition_stm32u5xx.h</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 28-June-2021</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
+</footer>
+</body>
+</html>

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld

+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xx Device from STM32U5 series
+**                      2048Kbytes ROM
+**                      768Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
+  ROM	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM AT> ROM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld

+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xx Device from STM32U5 series
+**                      2048Kbytes ROM
+**                      768Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20040000,	LENGTH = 512K     /* Memory is divided. Actual start is 0x20000000 and actual length is 768K */
+  ROM	(rx)	: ORIGIN = 0x08100000,	LENGTH = 1024K    /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM AT> ROM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld

+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xx Device from STM32U5 series
+**                      2048Kbytes ROM
+**                      768Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x30000000,	LENGTH = 256K     /* Memory is divided. Actual start is 0x30000000 and actual length is 768K */
+  ROM	(rx)	: ORIGIN = 0x0C000000,	LENGTH = 1016K    /* Memory is divided. Actual start is 0x0C000000 and actual length is 2048K */
+  ROM_NSC	(rx)	: ORIGIN = 0x0C0FE000,	LENGTH = 8K   /* Non-Secure Call-able region */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM AT> ROM
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(8);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(8);
+  } >ROM_NSC
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld

+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld (debug in RAM dedicated)
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xx Device from STM32U5 series
+**                      768Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >RAM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >RAM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >RAM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >RAM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >RAM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/_htmresc/Add button.svg

+<?xml version="1.0" encoding="UTF-8"?>
+<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 200 200"><g fill="#13254a"><path d="M100 .212C44.868.212 0 44.889 0 99.788c0 55.132 44.868 100 100 100s100-44.868 100-100C200 44.889 155.132.212 100 .212zm0 181.164c-44.974 0-81.587-36.614-81.587-81.587 0-44.762 36.614-81.164 81.587-81.164 44.995 0 81.587 36.402 81.587 81.164 0 44.973-36.592 81.587-81.587 81.587z" style="fill: #e6007e;"/><path d="M141.1 88.127h-29.439V58.688c0-6.392-5.185-11.598-11.598-11.598-6.413 0-11.619 5.206-11.619 11.598v29.439H58.476c-6.392 0-11.598 5.185-11.598 11.598 0 6.413 5.206 11.619 11.598 11.619h29.968v29.968c0 6.392 5.206 11.598 11.619 11.598 6.413 0 11.598-5.206 11.598-11.598v-29.968H141.1c6.392 0 11.598-5.206 11.598-11.619 0-6.413-5.206-11.598-11.598-11.598z" style="fill: #e6007e;"/></g></svg>

bsp/stm32/libraries/STM32U5xx_HAL/CMSIS/Device/ST/STM32U5xx/_htmresc/Update.svg

+<?xml version="1.0" encoding="UTF-8"?>
+<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 200 200"><g fill="#03234b"><path d="M170.934 64.569l-.04-.055-29.049 40.038-.057.079h14.867a59.366 59.366 0 0 1-1.488 15.615c-1.158 5.318-3.807 13.448-9.848 21.977-2.766 4.118-6.375 7.726-9.208 10.408-3.426 2.857-7.461 6.095-12 8.376-8.121 4.568-17.881 7.138-28.225 7.432-10.907.248-20.201-2.61-26.072-5.052-8.283-3.479-14.111-7.807-16.85-10.078-1.254-.956-2.25-1.907-3.057-2.676a28.662 28.662 0 0 0-1.157-1.069 158.874 158.874 0 0 0-1.479-1.362l-4.435-3.956 3.569 4.81.183.243c.2.263.548.722 1.048 1.389.276.334.579.747.93 1.226l.008.01c.689.939 1.546 2.107 2.664 3.322 3 3.536 8.178 8.801 15.808 13.801 5.969 3.866 15.672 8.901 28.001 10.935a79.05 79.05 0 0 0 12.485.998c7.97 0 15.651-1.228 22.828-3.649 6.366-1.877 12.192-4.981 17.053-7.771 6.16-3.936 10.817-7.586 14.654-11.488 8.084-7.899 14.884-17.913 19.15-28.199 3.259-7.594 5.456-15.727 6.529-24.175l.055-.425.083-.641H200l-29.066-40.063zM58.159 99.232l-12.655.563c-.097-.881-.159-1.986-.227-3.474a59.184 59.184 0 0 1 1.446-16.56c1.157-5.316 3.804-13.444 9.848-21.977 2.168-3.228 5.009-6.44 9.208-10.415 3.41-2.849 7.432-6.08 12.005-8.375 8.114-4.568 17.87-7.138 28.213-7.432 10.9-.25 20.196 2.607 26.072 5.045 8.258 3.473 14.105 7.812 16.857 10.091 1.257.951 2.253 1.904 3.057 2.673l.017.016c.43.411.801.766 1.136 1.051.475.438.841.777 1.091 1.01l.138.128.248.229 4.04 3.613-3.165-4.456c-.058-.083-.312-.417-.73-.971l-.507-.67a28.922 28.922 0 0 1-.901-1.192l-.02-.027c-.69-.945-1.548-2.121-2.677-3.346-3.002-3.537-8.182-8.803-15.813-13.801-5.964-3.865-15.662-8.9-27.997-10.935-8.484-1.363-21.496-2.009-35.313 2.651-6.355 1.88-12.186 4.983-17.054 7.772-6.163 3.944-10.82 7.595-14.654 11.488-8.079 7.894-14.882 17.909-19.155 28.2-3.268 7.624-5.463 15.757-6.523 24.173-.436 3.281-.642 5.421-.664 6.926L0 101.831l30.683 38.727.042.053 27.38-41.298.054-.081z" style="fill: #e6007e;"/></g></svg>