mimxrt/hal: Make flash clock frequency configurable.

Signed-off-by: N"Kwabena W. Agyeman" <kwagyeman@live.com>

ports/mimxrt/Makefile

@@ -397,6 +397,10 @@ CFLAGS += \
 	-DFSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE=1
 endif
 
+ifdef MICROPY_HW_FLASH_CLK
+	CFLAGS += -DMICROPY_HW_FLASH_CLK=$(MICROPY_HW_FLASH_CLK)
+endif
+
 CFLAGS += $(CFLAGS_EXTRA)
 
 MPY_CROSS_FLAGS += -march=armv7m

ports/mimxrt/hal/qspi_hyper_flash_config.c

@@ -22,6 +22,10 @@ __attribute__((section(".boot_hdr.conf")))
 #pragma location = ".boot_hdr.conf"
 #endif
 
+#ifndef MICROPY_HW_FLASH_CLK
+#define MICROPY_HW_FLASH_CLK kFlexSpiSerialClk_133MHz
+#endif
+
 const flexspi_nor_config_t qspiflash_config = {
     .memConfig =
     {
@@ -36,7 +40,7 @@ const flexspi_nor_config_t qspiflash_config = {
             (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
             (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
         .sflashPadType = kSerialFlash_8Pads,
-        .serialClkFreq = kFlexSpiSerialClk_133MHz,
+        .serialClkFreq = MICROPY_HW_FLASH_CLK,
         .sflashA1Size = MICROPY_HW_FLASH_SIZE,
         .dataValidTime = {16u, 16u},
         .lookupTable =

ports/mimxrt/hal/qspi_nor_flash_config.c

@@ -28,6 +28,10 @@ __attribute__((section(".boot_hdr.conf")))
 #define MICROPY_HW_FLASH_DQS kFlexSPIReadSampleClk_LoopbackFromDqsPad
 #endif
 
+#ifndef MICROPY_HW_FLASH_CLK
+#define MICROPY_HW_FLASH_CLK kFlexSpiSerialClk_100MHz
+#endif
+
 const flexspi_nor_config_t qspiflash_config = {
     .memConfig =
     {
@@ -48,7 +52,7 @@ const flexspi_nor_config_t qspiflash_config = {
         // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
         .deviceType = kFlexSpiDeviceType_SerialNOR,
         .sflashPadType = kSerialFlash_4Pads,
-        .serialClkFreq = kFlexSpiSerialClk_100MHz,
+        .serialClkFreq = MICROPY_HW_FLASH_CLK,
         .sflashA1Size = MICROPY_HW_FLASH_SIZE,
         .lookupTable =
         {