[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)

* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c

bsp/allwinner/d1s/.config

@@ -240,7 +240,7 @@ CONFIG_RT_USING_POSIX_TERMIOS=y
 # CONFIG_RT_USING_POSIX_MMAN is not set
 CONFIG_RT_USING_POSIX_DELAY=y
 CONFIG_RT_USING_POSIX_CLOCK=y
-# CONFIG_RT_USING_POSIX_TIMER is not set
+CONFIG_RT_USING_POSIX_TIMER=y
 # CONFIG_RT_USING_PTHREADS is not set
 # CONFIG_RT_USING_MODULE is not set
 

bsp/allwinner/d1s/rtconfig.h

@@ -146,6 +146,7 @@
 #define RT_USING_POSIX_TERMIOS
 #define RT_USING_POSIX_DELAY
 #define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
 
 /* Interprocess Communication (IPC) */
 

bsp/allwinner/libraries/libos/src/os.c

@@ -144,7 +144,7 @@ void awos_arch_mems_clean_dcache_region(unsigned long start, unsigned long len)
 
 void awos_arch_mems_clean_flush_dcache_region(unsigned long start, unsigned long len)
 {
-    rt_hw_cpu_dcache_clean_invalidate((void *)start, len);
+    rt_hw_cpu_dcache_clean_and_invalidate((void *)start, len);
 }
 
 void awos_arch_mems_flush_dcache_region(unsigned long start, unsigned long len)

components/lwp/lwp_syscall.c

@@ -1237,6 +1237,9 @@ struct ksigevent
     int sigev_tid;
 };
 
+/* to protect unsafe implementation in current rt-smart toolchain */
+RT_CTASSERT(sigevent_compatible, offsetof(struct ksigevent, sigev_tid) == offsetof(struct sigevent, sigev_notify_function));
+
 rt_err_t sys_timer_create(clockid_t clockid, struct sigevent *restrict sevp, timer_t *restrict timerid)
 {
     int ret = 0;
@@ -1264,17 +1267,11 @@ rt_err_t sys_timer_create(clockid_t clockid, struct sigevent *restrict sevp, tim
         }
     }
 
-    /* to protect unsafe implementation in current rt-smart toolchain */
-    RT_ASSERT(((struct ksigevent *)sevp)->sigev_tid == *(int *)(&sevp_k.sigev_notify_function));
-
     ret = _SYS_WRAP(timer_create(clockid, &sevp_k, &timerid_k));
 
-    /* ID should not extend 32-bits size for libc */
-    RT_ASSERT((rt_ubase_t)timerid_k < UINT32_MAX);
-    utimer = (rt_ubase_t)timerid_k;
-
     if (ret != -RT_ERROR)
     {
+        utimer = (rt_ubase_t)timerid_k;
         if (!lwp_put_to_user(sevp, (void *)&sevp_k, sizeof(struct ksigevent)) ||
             !lwp_put_to_user(timerid, (void *)&utimer, sizeof(utimer)))
             ret = -EINVAL;
@@ -4546,6 +4543,29 @@ sysret_t sys_mq_close(mqd_t mqd)
     return (ret < 0 ? GET_ERRNO() : ret);
 }
 
+#define ICACHE (1<<0)
+#define DCACHE (1<<1)
+#define BCACHE (ICACHE|DCACHE)
+
+rt_weak sysret_t sys_cacheflush(void *addr, int size, int cache)
+{
+    if (addr < addr + size &&
+        (size_t)addr >= USER_VADDR_START &&
+        (size_t)addr + size < USER_VADDR_TOP)
+    {
+        if ((cache & DCACHE))
+        {
+            rt_hw_cpu_dcache_clean_and_invalidate(addr, size);
+        }
+        if ((cache & ICACHE))
+        {
+            rt_hw_cpu_icache_invalidate(addr, size);
+        }
+        return 0;
+    }
+    return -EFAULT;
+}
+
 const static struct rt_syscall_def func_table[] =
 {
     SYSCALL_SIGN(sys_exit),            /* 01 */

components/mm/mm_page.c

@@ -26,20 +26,11 @@
 #define DBG_LVL DBG_WARNING
 #include <rtdbg.h>
 
+RT_CTASSERT(order_huge_pg, RT_PAGE_MAX_ORDER > ARCH_PAGE_SHIFT - 2);
+RT_CTASSERT(size_width, sizeof(rt_size_t) == sizeof(void *));
+
 #ifdef RT_USING_SMART
 #include "lwp_arch_comm.h"
-
-#define CT_ASSERT(name, x)                                                     \
-    struct assert_##name                                                       \
-    {                                                                          \
-        char ary[2 * (x)-1];                                                   \
-    }
-#ifdef ARCH_CPU_64BIT
-CT_ASSERT(order_huge_pg, RT_PAGE_MAX_ORDER > ARCH_PAGE_SHIFT - 2);
-#else
-CT_ASSERT(size_width, sizeof(rt_size_t) == sizeof(rt_size_t));
-#endif /* ARCH_CPU_64BIT */
-
 #endif /* RT_USING_SMART */
 
 static rt_size_t init_mpr_align_start;

include/rtdef.h

@@ -158,6 +158,9 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
 
 #define RT_UNUSED(x)                   ((void)x)
 
+/* compile time assertion */
+#define RT_CTASSERT(name, expn) typedef char _ct_assert_##name[(expn)?1:-1]
+
 /* Compiler Related Definitions */
 #if defined(__ARMCC_VERSION)           /* ARM Compiler */
 #define rt_section(x)               __attribute__((section(x)))
@@ -188,7 +191,7 @@ typedef __gnuc_va_list              va_list;
 #define va_end(v)                   __builtin_va_end(v)
 #define va_arg(v,l)                 __builtin_va_arg(v,l)
 #endif /* RT_USING_LIBC */
-#define __RT_STRINGIFY(x...)        (#x)
+#define __RT_STRINGIFY(x...)        #x
 #define RT_STRINGIFY(x...)          __RT_STRINGIFY(x)
 #define rt_section(x)               __attribute__((section(x)))
 #define rt_used                     __attribute__((used))

libcpu/aarch64/common/cache.h

@@ -11,6 +11,8 @@
 #ifndef __CACHE_H__
 #define __CACHE_H__
 
+#include <rtdef.h>
+
 void __asm_invalidate_icache_all(void);
 
 void rt_hw_dcache_flush_all(void);
@@ -25,5 +27,7 @@ static inline void rt_hw_icache_invalidate_all(void)
 }
 
 void rt_hw_icache_invalidate_range(unsigned long start_addr, int size);
+void rt_hw_cpu_icache_invalidate(void *addr, rt_size_t size);
+void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, rt_size_t size);
 
 #endif /* __CACHE_H__ */

libcpu/aarch64/common/cache_ops.c

@@ -77,26 +77,3 @@ rt_base_t rt_hw_cpu_dcache_status(void)
 {
     return 0;
 }
-
-#ifdef RT_USING_LWP
-#define ICACHE (1<<0)
-#define DCACHE (1<<1)
-#define BCACHE (ICACHE|DCACHE)
-
-int sys_cacheflush(void *addr, int size, int cache)
-{
-    if ((size_t)addr < KERNEL_VADDR_START && (size_t)addr + size <= KERNEL_VADDR_START)
-    {
-        if ((cache & DCACHE) != 0)
-        {
-            rt_hw_cpu_dcache_clean_and_invalidate(addr, size);
-        }
-        if ((cache & ICACHE) != 0)
-        {
-            rt_hw_cpu_icache_invalidate(addr, size);
-        }
-        return 0;
-    }
-    return -1;
-}
-#endif

libcpu/arm/cortex-a/cache.c

@@ -153,26 +153,3 @@ rt_base_t rt_hw_cpu_dcache_status(void)
 {
     return 0;
 }
-
-#ifdef RT_USING_SMART
-#define ICACHE (1<<0)
-#define DCACHE (1<<1)
-#define BCACHE (ICACHE|DCACHE)
-
-int sys_cacheflush(void *addr, int size, int cache)
-{
-    if ((size_t)addr < KERNEL_VADDR_START && (size_t)addr + size <= KERNEL_VADDR_START)
-    {
-        if ((cache & DCACHE) != 0)
-        {
-            rt_hw_cpu_dcache_clean_and_invalidate(addr, size);
-        }
-        if ((cache & ICACHE) != 0)
-        {
-            rt_hw_cpu_icache_invalidate(addr, size);
-        }
-        return 0;
-    }
-    return -1;
-}
-#endif

libcpu/arm/cortex-a/cache.h

@@ -11,6 +11,9 @@
 #ifndef __CACHE_H__
 #define __CACHE_H__
 
+void rt_hw_cpu_icache_invalidate(void *addr, int size);
+void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
+
 static inline void rt_hw_icache_invalidate_all(void)
 {
     __asm__ volatile("mcr p15, 0, %0, c7, c5, 0"::"r"(0ul));

libcpu/risc-v/t-head/c906/cache.c

@@ -90,7 +90,7 @@ void rt_hw_cpu_dcache_clean_local(void *addr, int size)
     rt_hw_cpu_sync();
 }
 
-void rt_hw_cpu_dcache_clean_invalidate_local(void *addr, int size)
+void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size)
 {
     dcache_wbinv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size));
     rt_hw_cpu_sync();
@@ -127,34 +127,3 @@ void rt_hw_sync_cache_local(void *addr, int size)
     rt_hw_cpu_dcache_clean_local(addr, size);
     rt_hw_cpu_icache_invalidate_local(addr, size);
 }
-
-#ifdef RT_USING_SMART
-#include <lwp_arch.h>
-#define ICACHE (1 << 0)
-#define DCACHE (1 << 1)
-#define BCACHE (ICACHE | DCACHE)
-
-/**
- * TODO moving syscall to kernel
- */
-int sys_cacheflush(void *addr, int size, int cache)
-{
-    /* must in user space */
-    if ((size_t)addr >= USER_VADDR_START && (size_t)addr + size < USER_VADDR_TOP)
-    {
-        /**
-         * we DO NOT check argument 'cache' invalid error
-         */
-        if ((cache & DCACHE) != 0)
-        {
-            rt_hw_cpu_dcache_clean_invalidate_local(addr, size);
-        }
-        if ((cache & ICACHE) != 0)
-        {
-            rt_hw_cpu_icache_invalidate_local(addr, size);
-        }
-        return 0;
-    }
-    return -RT_ERROR;
-}
-#endif

libcpu/risc-v/t-head/c906/cache.h

@@ -31,7 +31,7 @@
 
 void rt_hw_cpu_dcache_clean_local(void *addr, int size);
 void rt_hw_cpu_dcache_invalidate_local(void *addr, int size);
-void rt_hw_cpu_dcache_clean_invalidate_local(void *addr, int size);
+void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size);
 
 void rt_hw_cpu_icache_invalidate_local(void *addr, int size);
 
@@ -49,7 +49,7 @@ ALWAYS_INLINE void rt_hw_cpu_dcache_invalidate_all_local(void)
     rt_hw_cpu_sync();
 }
 
-ALWAYS_INLINE void rt_hw_cpu_dcache_clean_invalidate_all_local(void)
+ALWAYS_INLINE void rt_hw_cpu_dcache_clean_and_invalidate_all_local(void)
 {
     __asm__ volatile(OPC_DCACHE_CIALL ::
                          : "memory");
@@ -76,11 +76,11 @@ ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_all_local(void)
 
 void rt_hw_cpu_dcache_clean(void *addr, int size);
 void rt_hw_cpu_dcache_invalidate(void *addr, int size);
-void rt_hw_cpu_dcache_clean_invalidate(void *addr, int size);
+void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
 
 void rt_hw_cpu_dcache_clean_all(void);
 void rt_hw_cpu_dcache_invalidate_all(void);
-void rt_hw_cpu_dcache_clean_invalidate_all(void);
+void rt_hw_cpu_dcache_clean_and_invalidate_all(void);
 
 void rt_hw_cpu_icache_invalidate(void *addr, int size);
 void rt_hw_cpu_icache_invalidate_all(void);
@@ -89,11 +89,11 @@ void rt_hw_cpu_icache_invalidate_all(void);
 
 #define rt_hw_cpu_dcache_clean rt_hw_cpu_dcache_clean_local
 #define rt_hw_cpu_dcache_invalidate rt_hw_cpu_dcache_invalidate_local
-#define rt_hw_cpu_dcache_clean_invalidate rt_hw_cpu_dcache_clean_invalidate_local
+#define rt_hw_cpu_dcache_clean_and_invalidate rt_hw_cpu_dcache_clean_and_invalidate_local
 
 #define rt_hw_cpu_dcache_clean_all rt_hw_cpu_dcache_clean_all_local
 #define rt_hw_cpu_dcache_invalidate_all rt_hw_cpu_dcache_invalidate_all_local
-#define rt_hw_cpu_dcache_clean_invalidate_all rt_hw_cpu_dcache_clean_invalidate_all_local
+#define rt_hw_cpu_dcache_clean_and_invalidate_all rt_hw_cpu_dcache_clean_and_invalidate_all_local
 
 #define rt_hw_cpu_icache_invalidate rt_hw_cpu_icache_invalidate_local
 #define rt_hw_cpu_icache_invalidate_all rt_hw_cpu_icache_invalidate_all_local

libcpu/risc-v/virt64/cache.c

@@ -57,8 +57,3 @@ rt_base_t rt_hw_cpu_dcache_status()
 void rt_hw_sync_cache_local(void *addr, int size)
 {
 }
-
-int sys_cacheflush(void *addr, int size, int cache)
-{
-    return 0;
-}

libcpu/risc-v/virt64/cache.h

@@ -21,11 +21,11 @@
 
 ALWAYS_INLINE void rt_hw_cpu_dcache_clean_local(void *addr, int size) {}
 ALWAYS_INLINE void rt_hw_cpu_dcache_invalidate_local(void *addr, int size) {}
-ALWAYS_INLINE void rt_hw_cpu_dcache_clean_invalidate_local(void *addr, int size) {}
+ALWAYS_INLINE void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size) {}
 
 ALWAYS_INLINE void rt_hw_cpu_dcache_clean_all_local() {}
 ALWAYS_INLINE void rt_hw_cpu_dcache_invalidate_all_local(void) {}
-ALWAYS_INLINE void rt_hw_cpu_dcache_clean_invalidate_all_local(void) {}
+ALWAYS_INLINE void rt_hw_cpu_dcache_clean_and_invalidate_all_local(void) {}
 
 ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_local(void *addr, int size) {}
 ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_all_local() {}
@@ -36,11 +36,11 @@ ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_all_local() {}
 
 #define rt_hw_cpu_dcache_clean rt_hw_cpu_dcache_clean_local
 #define rt_hw_cpu_dcache_invalidate rt_hw_cpu_dcache_invalidate_local
-#define rt_hw_cpu_dcache_clean_invalidate rt_hw_cpu_dcache_clean_invalidate_local
+#define rt_hw_cpu_dcache_clean_and_invalidate rt_hw_cpu_dcache_clean_and_invalidate_local
 
 #define rt_hw_cpu_dcache_clean_all rt_hw_cpu_dcache_clean_all_local
 #define rt_hw_cpu_dcache_invalidate_all rt_hw_cpu_dcache_invalidate_all_local
-#define rt_hw_cpu_dcache_clean_invalidate_all rt_hw_cpu_dcache_clean_invalidate_all_local
+#define rt_hw_cpu_dcache_clean_and_invalidate_all rt_hw_cpu_dcache_clean_and_invalidate_all_local
 
 #define rt_hw_cpu_icache_invalidate rt_hw_cpu_icache_invalidate_local
 #define rt_hw_cpu_icache_invalidate_all rt_hw_cpu_icache_invalidate_all_local