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体验新版 GitCode,发现更多精彩内容 >>
提交
f6a13de0
编写于
3月 13, 2020
作者:
B
bigmagic
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
add raspi3-64 spi driver
上级
ba482c33
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
268 addition
and
382 deletion
+268
-382
bsp/raspberry-pi/raspi3-64/.config
bsp/raspberry-pi/raspi3-64/.config
+10
-2
bsp/raspberry-pi/raspi3-64/driver/Kconfig
bsp/raspberry-pi/raspi3-64/driver/Kconfig
+10
-5
bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
+163
-328
bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
+81
-47
bsp/raspberry-pi/raspi3-64/rtconfig.h
bsp/raspberry-pi/raspi3-64/rtconfig.h
+4
-0
未找到文件。
bsp/raspberry-pi/raspi3-64/.config
浏览文件 @
f6a13de0
...
...
@@ -166,7 +166,12 @@ CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY
=
22
CONFIG_RT_MMCSD_MAX_PARTITION
=
16
CONFIG_RT_SDIO_DEBUG
=
y
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_SPI
=
y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
CONFIG_RT_USING_WDT
=
y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
...
...
@@ -444,7 +449,10 @@ CONFIG_RT_USING_SYSTIMER3=y
CONFIG_BSP_USING_I2C
=
y
# CONFIG_BSP_USING_I2C0 is not set
CONFIG_BSP_USING_I2C1
=
y
# CONFIG_BSP_USING_SPI is not set
CONFIG_BSP_USING_SPI
=
y
CONFIG_BSP_USING_SPI0_BUS
=
y
CONFIG_BSP_USING_SPI0_DEVICE0
=
y
# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
CONFIG_BSP_USING_WDT
=
y
# CONFIG_BSP_USING_RTC is not set
CONFIG_BSP_USING_SDIO
=
y
...
...
bsp/raspberry-pi/raspi3-64/driver/Kconfig
浏览文件 @
f6a13de0
...
...
@@ -63,12 +63,17 @@ menu "Hardware Drivers Config"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0"
if BSP_USING_SPI
config BSP_USING_SPI0
_BUS
bool "Enable SPI0
BUS
"
default n
config BSP_USING_SPI1
bool "Enable SPI1"
config BSP_USING_SPI0_DEVICE0
bool "Enable SPI0 DEVICE0"
select BSP_USING_SPI0_BUS
default n
config BSP_USING_SPI0_DEVICE1
bool "Enable SPI0 DEVICE1"
select BSP_USING_SPI0_BUS
default n
endif
...
...
bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
浏览文件 @
f6a13de0
...
...
@@ -7,446 +7,281 @@
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include "drv_spi.h"
#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1)
#ifdef RT_USING_SPI
#undef RT_USING_SPI
#endif
#endif
#include "raspi.h"
#ifdef RT_USING_SPI
struct
rpi_pin_index
{
rt_uint8_t
phy_id
;
rt_uint8_t
bcm_id
;
rt_uint8_t
signal_name
;
rt_uint8_t
magic
;
};
//raspi phy id and bcm id
static
struct
rpi_pin_index
phypin_index
[]
=
{
{
0
,
0
,
0
,
0
},
{
1
,
0
,
0
,
0
},
{
2
,
0
,
0
,
0
},
{
3
,
BCM_GPIO_PIN_2
,
RPI_SDA1
,
PIN_MAGIC
},
{
4
,
0
,
0
,
0
},
{
5
,
BCM_GPIO_PIN_3
,
RPI_SCL1
,
PIN_MAGIC
},
{
6
,
0
,
0
,
0
},
{
7
,
BCM_GPIO_PIN_4
,
RPI_GPIO_GCLK
,
PIN_MAGIC
},
{
8
,
BCM_GPIO_PIN_14
,
RPI_TXD0
,
PIN_MAGIC
},
{
9
,
0
,
0
,
0
},
{
10
,
BCM_GPIO_PIN_15
,
RPI_RXD0
,
PIN_MAGIC
},
{
11
,
BCM_GPIO_PIN_17
,
RPI_GPIO_GEN0
,
PIN_MAGIC
},
{
12
,
BCM_GPIO_PIN_18
,
RPI_GPIO_GEN1
,
PIN_MAGIC
},
{
13
,
BCM_GPIO_PIN_27
,
RPI_GPIO_GEN2
,
PIN_MAGIC
},
{
14
,
0
,
0
,
0
},
{
15
,
BCM_GPIO_PIN_22
,
RPI_GPIO_GEN3
,
PIN_MAGIC
},
{
16
,
BCM_GPIO_PIN_23
,
RPI_GPIO_GEN4
,
PIN_MAGIC
},
{
17
,
0
,
0
,
0
},
{
18
,
BCM_GPIO_PIN_24
,
RPI_GPIO_GEN5
,
PIN_MAGIC
},
{
19
,
BCM_GPIO_PIN_10
,
RPI_SPI_MOSI
,
PIN_MAGIC
},
{
20
,
0
,
0
,
0
},
{
21
,
BCM_GPIO_PIN_9
,
RPI_SPI_MISO
,
PIN_MAGIC
},
{
22
,
BCM_GPIO_PIN_25
,
RPI_GPIO_GEN6
,
PIN_MAGIC
},
{
23
,
BCM_GPIO_PIN_11
,
RPI_SPI_SCLK
,
PIN_MAGIC
},
{
24
,
BCM_GPIO_PIN_8
,
RPI_SPI_CE0_N
,
PIN_MAGIC
},
{
25
,
0
,
0
,
0
},
{
26
,
BCM_GPIO_PIN_7
,
RPI_SPI_CE1_N
,
PIN_MAGIC
},
{
27
,
BCM_GPIO_PIN_0
,
RPI_SDA0
,
PIN_MAGIC
},
{
28
,
BCM_GPIO_PIN_1
,
RPI_SCL0
,
PIN_MAGIC
},
{
29
,
BCM_GPIO_PIN_5
,
RPI_CAM_CLK
,
PIN_MAGIC
},
{
30
,
0
,
0
,
0
},
{
31
,
BCM_GPIO_PIN_6
,
RPI_LAN_RUN
,
PIN_MAGIC
},
{
32
,
BCM_GPIO_PIN_12
,
0
,
PIN_MAGIC
},
{
33
,
BCM_GPIO_PIN_13
,
0
,
PIN_MAGIC
},
{
34
,
0
,
0
,
0
},
{
35
,
BCM_GPIO_PIN_19
,
0
,
PIN_MAGIC
},
{
36
,
BCM_GPIO_PIN_16
,
RPI_STATUS_LED_N
,
PIN_MAGIC
},
{
37
,
BCM_GPIO_PIN_26
,
0
,
PIN_MAGIC
},
{
38
,
BCM_GPIO_PIN_20
,
0
,
PIN_MAGIC
},
{
39
,
0
,
0
,
0
},
{
40
,
BCM_GPIO_PIN_21
,
RPI_CAM_GPIO
,
PIN_MAGIC
},
};
static
rt_uint8_t
bcm2835_spi_bit_order
=
BCM283X_SPI_BIT_ORDER_MSBFIRST
;
static
rt_uint8_t
bcm2835_byte_reverse_table
[]
=
{
0x00
,
0x80
,
0x40
,
0xc0
,
0x20
,
0xa0
,
0x60
,
0xe0
,
0x10
,
0x90
,
0x50
,
0xd0
,
0x30
,
0xb0
,
0x70
,
0xf0
,
0x08
,
0x88
,
0x48
,
0xc8
,
0x28
,
0xa8
,
0x68
,
0xe8
,
0x18
,
0x98
,
0x58
,
0xd8
,
0x38
,
0xb8
,
0x78
,
0xf8
,
0x04
,
0x84
,
0x44
,
0xc4
,
0x24
,
0xa4
,
0x64
,
0xe4
,
0x14
,
0x94
,
0x54
,
0xd4
,
0x34
,
0xb4
,
0x74
,
0xf4
,
0x0c
,
0x8c
,
0x4c
,
0xcc
,
0x2c
,
0xac
,
0x6c
,
0xec
,
0x1c
,
0x9c
,
0x5c
,
0xdc
,
0x3c
,
0xbc
,
0x7c
,
0xfc
,
0x02
,
0x82
,
0x42
,
0xc2
,
0x22
,
0xa2
,
0x62
,
0xe2
,
0x12
,
0x92
,
0x52
,
0xd2
,
0x32
,
0xb2
,
0x72
,
0xf2
,
0x0a
,
0x8a
,
0x4a
,
0xca
,
0x2a
,
0xaa
,
0x6a
,
0xea
,
0x1a
,
0x9a
,
0x5a
,
0xda
,
0x3a
,
0xba
,
0x7a
,
0xfa
,
0x06
,
0x86
,
0x46
,
0xc6
,
0x26
,
0xa6
,
0x66
,
0xe6
,
0x16
,
0x96
,
0x56
,
0xd6
,
0x36
,
0xb6
,
0x76
,
0xf6
,
0x0e
,
0x8e
,
0x4e
,
0xce
,
0x2e
,
0xae
,
0x6e
,
0xee
,
0x1e
,
0x9e
,
0x5e
,
0xde
,
0x3e
,
0xbe
,
0x7e
,
0xfe
,
0x01
,
0x81
,
0x41
,
0xc1
,
0x21
,
0xa1
,
0x61
,
0xe1
,
0x11
,
0x91
,
0x51
,
0xd1
,
0x31
,
0xb1
,
0x71
,
0xf1
,
0x09
,
0x89
,
0x49
,
0xc9
,
0x29
,
0xa9
,
0x69
,
0xe9
,
0x19
,
0x99
,
0x59
,
0xd9
,
0x39
,
0xb9
,
0x79
,
0xf9
,
0x05
,
0x85
,
0x45
,
0xc5
,
0x25
,
0xa5
,
0x65
,
0xe5
,
0x15
,
0x95
,
0x55
,
0xd5
,
0x35
,
0xb5
,
0x75
,
0xf5
,
0x0d
,
0x8d
,
0x4d
,
0xcd
,
0x2d
,
0xad
,
0x6d
,
0xed
,
0x1d
,
0x9d
,
0x5d
,
0xdd
,
0x3d
,
0xbd
,
0x7d
,
0xfd
,
0x03
,
0x83
,
0x43
,
0xc3
,
0x23
,
0xa3
,
0x63
,
0xe3
,
0x13
,
0x93
,
0x53
,
0xd3
,
0x33
,
0xb3
,
0x73
,
0xf3
,
0x0b
,
0x8b
,
0x4b
,
0xcb
,
0x2b
,
0xab
,
0x6b
,
0xeb
,
0x1b
,
0x9b
,
0x5b
,
0xdb
,
0x3b
,
0xbb
,
0x7b
,
0xfb
,
0x07
,
0x87
,
0x47
,
0xc7
,
0x27
,
0xa7
,
0x67
,
0xe7
,
0x17
,
0x97
,
0x57
,
0xd7
,
0x37
,
0xb7
,
0x77
,
0xf7
,
0x0f
,
0x8f
,
0x4f
,
0xcf
,
0x2f
,
0xaf
,
0x6f
,
0xef
,
0x1f
,
0x9f
,
0x5f
,
0xdf
,
0x3f
,
0xbf
,
0x7f
,
0xff
};
#define RPI_CORE_CLK_HZ 250000000
#define BSP_SPI_MAX_HZ (30* 1000 *1000)
#define SPITIMEOUT 0x0FFF
struct
rt_spi_hw_config
void
spi_gpio_write
(
rt_uint8_t
pin
,
rt_uint8_t
val
)
{
rt_int8_t
sclk_pin
;
rt_int8_t
sclk_mode
;
rt_int8_t
mosi_pin
;
rt_int8_t
mosi_mode
;
rt_int8_t
miso_pin
;
rt_int8_t
miso_mode
;
rt_int8_t
cs_pin
;
rt_int8_t
cs_mode
;
rt_uint32_t
spi_base
;
rt_uint32_t
clk_div
;
};
if
(
val
)
BCM283X_GPIO_GPSET
((
pin
/
32
))
=
1
<<
(
pin
%
32
);
else
BCM283X_GPIO_GPCLR
((
pin
/
32
))
=
1
<<
(
pin
%
32
);
}
struct
r
t_sw_spi_cs
struct
r
aspi_spi_hw_config
{
rt_uint32_t
pin
;
rt_uint8_t
spi_num
;
raspi_gpio_pin
sclk_pin
;
raspi_pin_select
sclk_mode
;
raspi_gpio_pin
mosi_pin
;
raspi_pin_select
mosi_mode
;
raspi_gpio_pin
miso_pin
;
raspi_pin_select
miso_mode
;
#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0)
raspi_gpio_pin
ce0_pin
;
raspi_pin_select
ce0_mode
;
#endif
#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1)
raspi_gpio_pin
ce1_pin
;
raspi_pin_select
ce1_mode
;
#endif
#if defined (BSP_USING_SPI1_DEVICE2)
raspi_gpio_pin
ce2_pin
;
raspi_pin_select
ce2_mode
;
#endif
};
struct
r
t_spi
struct
r
aspi_spi_device
{
char
*
device_name
;
struct
rt_spi_bus
*
spi_bus
;
struct
rt_spi_
hw_config
*
hwcfg
;
struct
rt_spi_configuration
*
cfg
;
struct
rt_spi_
device
*
spi_device
;
raspi_gpio_pin
cs_pin
;
};
static
rt_err_t
raspi_
hostspi_init
(
struct
rt_spi_configuration
*
cfg
)
static
rt_err_t
raspi_
spi_configure
(
struct
rt_spi_device
*
device
,
struct
rt_spi_configuration
*
cfg
)
{
volatile
rt_uint32_t
addr
=
(
PER_BASE
+
BCM283X_SPI0_BASE
)
+
BCM283X_SPI0_CS
;
//volatile rt_uint32_t fifo = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_FIFO
;
RT_ASSERT
(
cfg
!=
RT_NULL
);
RT_ASSERT
(
device
!=
RT_NULL
)
;
rt_uint16_t
divider
;
// spi clear fifo
bcm283x_peri_set_bits
(
addr
,
BCM283X_SPI0_CS_CLEAR
,
BCM283X_SPI0_CS_CLEAR
);
// /* Set TA = 1 */
// bcm2835_peri_set_bits(addr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA);
/* Mask in the CPO and CPHA bits of CS */
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
BCM283X_SPI0_CS_CLEAR
;
bcm283x_peri_set_bits
(
addr
,
(
rt_uint32_t
)(
cfg
->
mode
<<
2
),
BCM283X_SPI0_CS_CPOL
|
BCM283X_SPI0_CS_CPHA
);
if
(
cfg
->
mode
&
RT_SPI_CPOL
)
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
BCM283X_SPI0_CS_CPOL
;
//chipSelect
bcm283x_peri_set_bits
(
addr
,
BCM283X_SPI_CS0
,
BCM283X_SPI0_CS_CS
)
;
if
(
cfg
->
mode
&
RT_SPI_CPHA
)
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
BCM283X_SPI0_CS_CPHA
;
rt_uint8_t
shift
=
21
+
BCM283X_SPI_CS0
;
/* Mask in the appropriate CSPOLn bit */
bcm283x_peri_set_bits
(
addr
,
LOW
<<
shift
,
1
<<
shift
);
if
(
cfg
->
mode
&
RT_SPI_CS_HIGH
)
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
BCM283X_SPI0_CS_CSPOL
;
if
(
cfg
->
max_hz
>
BSP_SPI_MAX_HZ
)
{
//set clk
if
(
cfg
->
max_hz
>
BSP_SPI_MAX_HZ
)
cfg
->
max_hz
=
BSP_SPI_MAX_HZ
;
}
volatile
rt_uint32_t
clk_addr
=
(
PER_BASE
+
BCM283X_SPI0_BASE
)
+
BCM283X_SPI0_CLK
;
bcm283x_peri_write
(
clk_addr
,
cfg
->
max_hz
)
;
divider
=
(
rt_uint16_t
)
((
rt_uint32_t
)
RPI_CORE_CLK_HZ
/
cfg
->
max_hz
)
;
divider
&=
0xFFFE
;
return
RT_EOK
;
}
static
rt_err_t
raspi_spi_configure
(
struct
rt_spi_device
*
device
,
struct
rt_spi_configuration
*
cfg
)
{
RT_ASSERT
(
cfg
!=
RT_NULL
);
RT_ASSERT
(
device
!=
RT_NULL
);
struct
rt_spi
*
hspi
=
(
struct
rt_spi
*
)
&
device
->
bus
->
parent
;
hspi
->
cfg
=
cfg
;
raspi_hostspi_init
(
cfg
);
BCM283X_SPI0_CLK
(
BCM283X_SPI0_BASE
)
=
divider
;
return
RT_EOK
;
}
rt_uint8_t
correct_order
(
rt_uint8_t
b
)
rt_uint8_t
correct_order
(
rt_uint8_t
b
,
rt_uint8_t
flag
)
{
if
(
bcm2835_spi_bit_order
==
BCM283X_SPI_BIT_ORDER_LSBFIRST
)
return
bcm2835
_byte_reverse_table
[
b
];
if
(
flag
)
return
raspi
_byte_reverse_table
[
b
];
else
return
b
;
}
static
rt_err_t
spi_transfernb
(
rt_uint8_t
*
tbuf
,
rt_uint8_t
*
rbuf
,
rt_uint32_t
len
)
static
rt_err_t
spi_transfernb
(
rt_uint8_t
*
tbuf
,
rt_uint8_t
*
rbuf
,
rt_uint32_t
len
,
rt_uint8_t
flag
)
{
volatile
rt_uint32_t
paddr
=
SPI0_BASE_ADDR
+
BCM283X_SPI0_CS
;
volatile
rt_uint32_t
fifo
=
SPI0_BASE_ADDR
+
BCM283X_SPI0_FIFO
;
rt_uint32_t
TXCnt
=
0
;
rt_uint32_t
RXCnt
=
0
;
/* Clear TX and RX fifos */
bcm283x_peri_set_bits
(
paddr
,
BCM283X_SPI0_CS_CLEAR
,
BCM283X_SPI0_CS_CLEAR
);
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
(
BCM283X_SPI0_CS_CLEAR
&
BCM283X_SPI0_CS_CLEAR
);
/* Set TA = 1 */
bcm283x_peri_set_bits
(
paddr
,
BCM283X_SPI0_CS_TA
,
BCM283X_SPI0_CS_TA
);
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
(
BCM283X_SPI0_CS_TA
&
BCM283X_SPI0_CS_TA
);
/* Use the FIFO's to reduce the interbyte times */
while
((
TXCnt
<
len
)
||
(
RXCnt
<
len
))
{
/* TX fifo not full, so add some more bytes */
while
(((
bcm283x_peri_read
(
paddr
)
&
BCM283X_SPI0_CS_TXD
))
&&
(
TXCnt
<
len
))
while
(((
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
&
BCM283X_SPI0_CS_TXD
))
&&
(
TXCnt
<
len
))
{
bcm283x_peri_write_nb
(
fifo
,
correct_order
(
tbuf
[
TXCnt
])
);
BCM283X_SPI0_FIFO
(
BCM283X_SPI0_BASE
)
=
correct_order
(
tbuf
[
TXCnt
],
flag
);
TXCnt
++
;
}
/* Rx fifo not empty, so get the next received bytes */
while
(((
bcm283x_peri_read
(
paddr
)
&
BCM283X_SPI0_CS_RXD
))
&&
(
RXCnt
<
len
))
while
(((
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
&
BCM283X_SPI0_CS_RXD
))
&&
(
RXCnt
<
len
))
{
rbuf
[
RXCnt
]
=
correct_order
(
bcm283x_peri_read_nb
(
fifo
)
);
rbuf
[
RXCnt
]
=
correct_order
(
BCM283X_SPI0_FIFO
(
BCM283X_SPI0_BASE
),
flag
);
RXCnt
++
;
}
}
/* Wait for DONE to be set */
while
(
!
(
bcm283x_peri_read_nb
(
paddr
)
&
BCM283X_SPI0_CS_DONE
));
while
(
!
(
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
&
BCM283X_SPI0_CS_DONE
));
/* Set TA = 0, and also set the barrier */
bcm283x_peri_set_bits
(
paddr
,
0
,
BCM283X_SPI0_CS_TA
);
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
(
0
&
BCM283X_SPI0_CS_TA
);
return
RT_EOK
;
}
static
rt_uint32_t
raspi_spi_xfer
(
struct
rt_spi_device
*
device
,
struct
rt_spi_message
*
message
)
{
rt_err_t
res
;
RT_ASSERT
(
device
!=
RT_NULL
);
RT_ASSERT
(
device
->
bus
!=
RT_NULL
);
RT_ASSERT
(
device
->
bus
->
parent
.
user_data
!=
RT_NULL
);
RT_ASSERT
(
device
->
parent
.
user_data
!=
RT_NULL
);
RT_ASSERT
(
message
->
send_buf
!=
RT_NULL
||
message
->
recv_buf
!=
RT_NULL
);
struct
rt_spi
*
hspi
=
(
struct
rt_spi
*
)
&
device
->
bus
->
parent
;
/* only send data */
if
(
message
->
recv_buf
==
RT_NULL
)
{
if
(
message
->
cs_take
)
{
bcm283x_gpio_write
(
hspi
->
hwcfg
->
cs_pin
,
0
);
}
res
=
spi_transfernb
((
rt_uint8_t
*
)
message
->
send_buf
,
RT_NULL
,(
rt_int32_t
)
message
->
length
);
if
(
message
->
cs_release
)
{
bcm283x_gpio_write
(
hspi
->
hwcfg
->
cs_pin
,
1
);
}
if
(
res
!=
RT_EOK
)
return
RT_ERROR
;
}
rt_err_t
res
;
rt_uint8_t
flag
;
struct
rt_spi_configuration
config
=
device
->
config
;
raspi_gpio_pin
cs_pin
=
(
raspi_gpio_pin
)
device
->
parent
.
user_data
;
/* only receive data */
if
(
message
->
send_buf
==
RT_NULL
)
{
if
(
message
->
cs_take
)
{
bcm283x_gpio_write
(
hspi
->
hwcfg
->
cs_pin
,
0
);
}
res
=
spi_transfernb
(
RT_NULL
,(
rt_uint8_t
*
)
message
->
recv_buf
,
(
rt_int32_t
)
message
->
length
);
if
(
message
->
cs_release
)
{
bcm283x_gpio_write
(
hspi
->
hwcfg
->
cs_pin
,
1
);
}
if
(
res
!=
RT_EOK
)
return
RT_ERROR
;
}
/* send & receive */
if
(
config
.
mode
&
RT_SPI_MSB
)
flag
=
0
;
else
{
if
(
message
->
cs_take
)
{
bcm283x_gpio_write
(
hspi
->
hwcfg
->
cs_pin
,
0
);
}
res
=
spi_transfernb
((
rt_uint8_t
*
)
message
->
send_buf
,
(
rt_uint8_t
*
)
message
->
recv_buf
,
(
rt_int32_t
)
message
->
length
);
if
(
message
->
cs_release
)
{
bcm283x_gpio_write
(
hspi
->
hwcfg
->
cs_pin
,
1
);
}
if
(
res
!=
RT_EOK
)
return
RT_ERROR
;
}
flag
=
1
;
if
(
message
->
cs_take
);
// (config.mode & RT_SPI_CS_HIGH)?
// spi_gpio_write(cs_pin, 1):
// spi_gpio_write(cs_pin, 0);
/* deal data */
res
=
spi_transfernb
((
rt_uint8_t
*
)
message
->
send_buf
,
(
rt_uint8_t
*
)
message
->
recv_buf
,
(
rt_int32_t
)
message
->
length
,
flag
);
if
(
message
->
cs_release
)
(
config
.
mode
&
RT_SPI_CS_HIGH
)
?
spi_gpio_write
(
cs_pin
,
0
)
:
spi_gpio_write
(
cs_pin
,
1
);
if
(
res
!=
RT_EOK
)
return
RT_ERROR
;
return
message
->
length
;
}
rt_err_t
raspi_spi_bus_attach_device
(
const
char
*
bus_name
,
const
char
*
device_name
,
rt_uint32_t
pin
)
rt_err_t
raspi_spi_bus_attach_device
(
const
char
*
bus_name
,
struct
raspi_spi_device
*
device
)
{
rt_err_t
ret
;
rt_int16_t
gpio_pin
;
struct
rt_spi_device
*
spi_device
;
struct
rt_sw_spi_cs
*
cs_pin
;
gpio_pin
=
phypin_index
[
pin
].
bcm_id
;
spi_device
=
(
struct
rt_spi_device
*
)
rt_malloc
(
sizeof
(
struct
rt_spi_device
));
RT_ASSERT
(
spi_device
!=
RT_NULL
);
cs_pin
=
(
struct
rt_sw_spi_cs
*
)
rt_malloc
(
sizeof
(
struct
rt_sw_spi_cs
));
RT_ASSERT
(
cs_pin
!=
RT_NULL
);
cs_pin
->
pin
=
gpio_pin
;
ret
=
rt_spi_bus_attach_device
(
spi_device
,
device_name
,
bus_name
,
(
void
*
)
cs_pin
);
RT_ASSERT
(
device
!=
RT_NULL
);
ret
=
rt_spi_bus_attach_device
(
device
->
spi_device
,
device
->
device_name
,
bus_name
,
(
void
*
)(
device
->
cs_pin
));
return
ret
;
}
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
rt_uint16_t
spi_clockdivider
(
rt_uint32_t
speed_hz
)
rt_err_t
raspi_spi_hw_init
(
struct
raspi_spi_hw_config
*
hwcfg
)
{
rt_uint16_t
divider
;
GPIO_FSEL
(
hwcfg
->
sclk_pin
,
hwcfg
->
sclk_mode
);
GPIO_FSEL
(
hwcfg
->
miso_pin
,
hwcfg
->
miso_mode
);
GPIO_FSEL
(
hwcfg
->
mosi_pin
,
hwcfg
->
mosi_mode
);
if
(
speed_hz
<
(
rt_uint32_t
)
BCM283X_AUX_SPI_CLOCK_MIN
)
{
speed_hz
=
(
rt_uint32_t
)
BCM283X_AUX_SPI_CLOCK_MIN
;
}
else
if
(
speed_hz
>
(
rt_uint32_t
)
BCM283X_AUX_SPI_CLOCK_MAX
)
{
speed_hz
=
(
rt_uint32_t
)
BCM283X_AUX_SPI_CLOCK_MAX
;
}
divider
=
(
rt_uint16_t
)
DIV_ROUND_UP
(
BCM283X_CORE_CLK_HZ
,
2
*
speed_hz
)
-
1
;
if
(
divider
>
(
rt_uint16_t
)
BCM283X_AUX_SPI_CNTL0_SPEED_MAX
)
{
return
(
rt_uint16_t
)
BCM283X_AUX_SPI_CNTL0_SPEED_MAX
;
}
return
divider
;
}
#if defined (BSP_USING_SPI0_DEVICE0)
GPIO_FSEL
(
hwcfg
->
ce0_pin
,
hwcfg
->
ce0_mode
);
#endif
rt_err_t
raspi_spi_hw_init
(
struct
rt_spi_hw_config
*
hwcfg
)
{
volatile
rt_uint32_t
enable
=
PER_BASE
+
BCM283X_AUX_BASE
+
BCM283X_AUX_ENABLE
;
volatile
rt_uint32_t
cntl0
=
PER_BASE
+
BCM283X_SPI1_BASE
+
BCM283X_AUX_SPI_CNTL0
;
volatile
rt_uint32_t
cntl1
=
PER_BASE
+
BCM283X_SPI1_BASE
+
BCM283X_AUX_SPI_CNTL1
;
#if defined (BSP_USING_SPI0_DEVICE1)
GPIO_FSEL
(
hwcfg
->
ce1_pin
,
hwcfg
->
ce1_mode
);
#endif
bcm283x_gpio_fsel
(
hwcfg
->
sclk_pin
,
hwcfg
->
sclk_mode
);
bcm283x_gpio_fsel
(
hwcfg
->
miso_pin
,
hwcfg
->
miso_mode
);
bcm283x_gpio_fsel
(
hwcfg
->
mosi_pin
,
hwcfg
->
mosi_mode
);
bcm283x_gpio_fsel
(
hwcfg
->
cs_pin
,
hwcfg
->
cs_mode
);
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
=
0
;
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
=
BCM283X_SPI0_CS_CLEAR
;
hwcfg
->
clk_div
=
spi_clockdivider
(
1000000
);
// Default 1MHz SPI
//enable chip select
#if defined (BSP_USING_SPI0_DEVICE0)
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
0
;
#endif
bcm283x_peri_write
(
enable
,
BCM283X_AUX_ENABLE_SPI0
);
bcm283x_peri_write
(
cntl1
,
0
)
;
bcm283x_peri_write
(
cntl0
,
BCM283X_AUX_SPI_CNTL0_CLEARFIFO
);
#if defined (BSP_USING_SPI0_DEVICE1)
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
0x2
;
#endif
#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
BCM283X_SPI0_CS
(
BCM283X_SPI0_BASE
)
|=
BCM283X_SPI0_CS_CS
;
#endif
return
RT_EOK
;
}
const
static
struct
rt_spi_ops
raspi_spi_ops
=
static
struct
rt_spi_ops
raspi_spi_ops
=
{
.
configure
=
raspi_spi_configure
,
.
xfer
=
raspi_spi_xfer
};
#if defined (BSP_USING_SPI0)
#define SPI0BUS_NAME "spi0.0"
struct
rt_spi
spi0
;
struct
rt_spi_bus
raspi_spi0_bus
=
{
.
ops
=
&
raspi_spi_ops
,
.
parent
.
user_data
=
&
spi0
};
#if defined (BSP_USING_SPI0_BUS)
#define SPI0_BUS_NAME "spi0"
#define SPI0_DEVICE0_NAME "spi0.0"
#define SPI0_DEVICE1_NAME "spi0.1"
struct
rt_spi_hw_config
raspi_spi0_hw
=
{
.
sclk_pin
=
BCM_GPIO_PIN_11
,
.
sclk_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
mosi_pin
=
BCM_GPIO_PIN_10
,
.
mosi_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
miso_pin
=
BCM_GPIO_PIN_9
,
.
miso_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
cs_pin
=
BCM_GPIO_PIN_8
,
.
cs_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
spi_base
=
(
PER_BASE
+
BCM283X_SPI0_BASE
),
.
clk_div
=
0
,
};
struct
rt_spi
spi0
=
{
.
device_name
=
SPI0BUS_NAME
,
.
spi_bus
=
&
raspi_spi0_bus
,
.
hwcfg
=
&
raspi_spi0_hw
,
};
struct
rt_spi_bus
spi0_bus
;
#if defined (BSP_USING_SPI0_DEVICE0)
struct
rt_spi_device
spi0_device0
;
#endif
#if defined (BSP_USING_SPI1)
#define SPI1BUS_NAME "spi0.1"
struct
rt_spi
spi1
;
struct
rt_spi_bus
raspi_spi1_bus
=
{
.
ops
=
&
raspi_spi_ops
,
.
parent
.
user_data
=
&
spi1
};
#if defined (BSP_USING_SPI0_DEVICE1)
static
struct
rt_spi_device
spi0_device1
;
#endif
struct
r
t_spi_hw_config
raspi_spi1
_hw
=
struct
r
aspi_spi_hw_config
raspi_spi0
_hw
=
{
.
sclk_pin
=
BCM_GPIO_PIN_11
,
.
spi_num
=
0
,
.
sclk_pin
=
RPI_GPIO_P1_23
,
.
sclk_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
mosi_pin
=
BCM_GPIO_PIN_10
,
.
mosi_pin
=
RPI_GPIO_P1_19
,
.
mosi_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
miso_pin
=
BCM_GPIO_PIN_9
,
.
miso_pin
=
RPI_GPIO_P1_21
,
.
miso_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
cs_pin
=
BCM_GPIO_PIN_7
,
.
cs_mode
=
BCM283X_GPIO_FSEL_ALT0
,
.
spi_base
=
(
PER_BASE
+
BCM283X_SPI0_BASE
),
.
clk_div
=
0
,
};
struct
rt_spi
spi1
=
{
.
device_name
=
SPI1BUS_NAME
,
.
spi_bus
=
&
raspi_spi1_bus
,
.
hwcfg
=
&
raspi_spi1_hw
,
#if defined (BSP_USING_SPI0_DEVICE0)
.
ce0_pin
=
RPI_GPIO_P1_24
,
.
ce0_mode
=
BCM283X_GPIO_FSEL_ALT0
,
#endif
#if defined (BSP_USING_SPI0_DEVICE1)
.
ce1_pin
=
RPI_GPIO_P1_26
,
.
ce1_mode
=
BCM283X_GPIO_FSEL_ALT0
,
#endif
};
#endif
int
rt_hw_spi_
bus_
init
(
void
)
int
rt_hw_spi_init
(
void
)
{
#if defined (BSP_USING_SPI0)
raspi_spi_hw_init
(
spi0
.
hwcfg
);
rt_spi_bus_register
(
spi0
.
spi_bus
,
spi0
.
device_name
,
spi0
.
spi_bus
->
ops
);
#endif
#if defined (BSP_USING_SPI1)
raspi_spi_hw_init
(
spi1
.
hwcfg
);
rt_spi_bus_register
(
spi1
.
spi_bus
,
spi1
.
device_name
,
spi1
.
spi_bus
->
ops
);
#if defined (BSP_USING_SPI0_BUS)
raspi_spi_hw_init
(
&
raspi_spi0_hw
);
rt_spi_bus_register
(
&
spi0_bus
,
SPI0_BUS_NAME
,
&
raspi_spi_ops
);
#if defined (BSP_USING_SPI0_DEVICE0)
struct
raspi_spi_device
raspi_spi0_device0
=
{
.
device_name
=
SPI0_DEVICE0_NAME
,
.
spi_bus
=
&
spi0_bus
,
.
spi_device
=
&
spi0_device0
,
.
cs_pin
=
raspi_spi0_hw
.
ce0_pin
,
};
raspi_spi_bus_attach_device
(
SPI0_BUS_NAME
,
&
raspi_spi0_device0
);
#endif
#if defined (BSP_USING_SPI0_DEVICE1)
struct
raspi_spi_device
raspi_spi0_device1
=
{
.
device_name
=
SPI0_DEVICE1_NAME
,
.
spi_bus
=
&
spi0_bus
,
.
spi_device
=
&
spi0_device1
,
.
cs_pin
=
raspi_spi0_hw
.
ce1_pin
,
};
raspi_spi_bus_attach_device
(
SPI0_BUS_NAME
,
&
raspi_spi0_device1
);
#endif
#endif
return
RT_EOK
;
}
INIT_
PREV_EXPORT
(
rt_hw_spi_bus
_init
);
INIT_
DEVICE_EXPORT
(
rt_hw_spi
_init
);
#endif
bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
浏览文件 @
f6a13de0
...
...
@@ -12,57 +12,91 @@
#define __DRV_SPI_H__
#include <rtthread.h>
#include <rthw.h>
#include "bcm283x.h"
#include <rtdevice.h>
#include <drivers/spi.h>
#include "raspi.h"
//#include <drivers/spi.h>
#include "board.h"
#define SPI0_BASE_ADDR (PER_BASE + BCM283X_SPI0_BASE)
#define SPI_CORE_CLK 250000000U
#define SPI_CS 0x00
#define SPI_CS_LEN_LONG (1 << 25)
#define SPI_CS_DMA_LEN (1 << 24)
#define SPI_CS_CSPOL2 (1 << 23)
#define SPI_CS_CSPOL1 (1 << 22)
#define SPI_CS_CSPOL0 (1 << 21)
#define SPI_CS_RXF (1 << 20)
#define SPI_CS_RXR (1 << 19)
#define SPI_CS_TXD (1 << 18)
#define SPI_CS_RXD (1 << 17)
#define SPI_CS_DONE (1 << 16)
#define SPI_CS_LEN (1 << 13)
#define SPI_CS_REN (1 << 12)
#define SPI_CS_ADCS (1 << 11)
#define SPI_CS_INTR (1 << 10)
#define SPI_CS_INTD (1 << 9)
#define SPI_CS_DMAEN (1 << 8)
#define SPI_CS_TA (1 << 7)
#define SPI_CS_CSPOL (1 << 6)
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
#define SPI_CS_CPOL (1 << 3)
#define SPI_CS_CPHA (1 << 2)
#define SPI_CS_MASK 0x3
#define SPI_FIFO 0x04
#define SPI_CLK 0x08
#define SPI_CLK_MASK 0xffff
#define SPI_DLEN 0x0c
#define SPI_DLEN_MASK 0xffff
#define SPI_LTOH 0x10
#define SPI_LTOH_MASK 0xf
#define SPI_DC 0x14
#define SPI_DC_RPANIC_SHIFT 24
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
#define SPI_DC_RDREQ_SHIFT 16
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
#define SPI_DC_TPANIC_SHIFT 8
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
#define SPI_DC_TDREQ_SHIFT 0
#define SPI_DC_TDREQ_MASK 0xff
static
rt_uint8_t
raspi_byte_reverse_table
[]
=
{
0x00
,
0x80
,
0x40
,
0xc0
,
0x20
,
0xa0
,
0x60
,
0xe0
,
0x10
,
0x90
,
0x50
,
0xd0
,
0x30
,
0xb0
,
0x70
,
0xf0
,
0x08
,
0x88
,
0x48
,
0xc8
,
0x28
,
0xa8
,
0x68
,
0xe8
,
0x18
,
0x98
,
0x58
,
0xd8
,
0x38
,
0xb8
,
0x78
,
0xf8
,
0x04
,
0x84
,
0x44
,
0xc4
,
0x24
,
0xa4
,
0x64
,
0xe4
,
0x14
,
0x94
,
0x54
,
0xd4
,
0x34
,
0xb4
,
0x74
,
0xf4
,
0x0c
,
0x8c
,
0x4c
,
0xcc
,
0x2c
,
0xac
,
0x6c
,
0xec
,
0x1c
,
0x9c
,
0x5c
,
0xdc
,
0x3c
,
0xbc
,
0x7c
,
0xfc
,
0x02
,
0x82
,
0x42
,
0xc2
,
0x22
,
0xa2
,
0x62
,
0xe2
,
0x12
,
0x92
,
0x52
,
0xd2
,
0x32
,
0xb2
,
0x72
,
0xf2
,
0x0a
,
0x8a
,
0x4a
,
0xca
,
0x2a
,
0xaa
,
0x6a
,
0xea
,
0x1a
,
0x9a
,
0x5a
,
0xda
,
0x3a
,
0xba
,
0x7a
,
0xfa
,
0x06
,
0x86
,
0x46
,
0xc6
,
0x26
,
0xa6
,
0x66
,
0xe6
,
0x16
,
0x96
,
0x56
,
0xd6
,
0x36
,
0xb6
,
0x76
,
0xf6
,
0x0e
,
0x8e
,
0x4e
,
0xce
,
0x2e
,
0xae
,
0x6e
,
0xee
,
0x1e
,
0x9e
,
0x5e
,
0xde
,
0x3e
,
0xbe
,
0x7e
,
0xfe
,
0x01
,
0x81
,
0x41
,
0xc1
,
0x21
,
0xa1
,
0x61
,
0xe1
,
0x11
,
0x91
,
0x51
,
0xd1
,
0x31
,
0xb1
,
0x71
,
0xf1
,
0x09
,
0x89
,
0x49
,
0xc9
,
0x29
,
0xa9
,
0x69
,
0xe9
,
0x19
,
0x99
,
0x59
,
0xd9
,
0x39
,
0xb9
,
0x79
,
0xf9
,
0x05
,
0x85
,
0x45
,
0xc5
,
0x25
,
0xa5
,
0x65
,
0xe5
,
0x15
,
0x95
,
0x55
,
0xd5
,
0x35
,
0xb5
,
0x75
,
0xf5
,
0x0d
,
0x8d
,
0x4d
,
0xcd
,
0x2d
,
0xad
,
0x6d
,
0xed
,
0x1d
,
0x9d
,
0x5d
,
0xdd
,
0x3d
,
0xbd
,
0x7d
,
0xfd
,
0x03
,
0x83
,
0x43
,
0xc3
,
0x23
,
0xa3
,
0x63
,
0xe3
,
0x13
,
0x93
,
0x53
,
0xd3
,
0x33
,
0xb3
,
0x73
,
0xf3
,
0x0b
,
0x8b
,
0x4b
,
0xcb
,
0x2b
,
0xab
,
0x6b
,
0xeb
,
0x1b
,
0x9b
,
0x5b
,
0xdb
,
0x3b
,
0xbb
,
0x7b
,
0xfb
,
0x07
,
0x87
,
0x47
,
0xc7
,
0x27
,
0xa7
,
0x67
,
0xe7
,
0x17
,
0x97
,
0x57
,
0xd7
,
0x37
,
0xb7
,
0x77
,
0xf7
,
0x0f
,
0x8f
,
0x4f
,
0xcf
,
0x2f
,
0xaf
,
0x6f
,
0xef
,
0x1f
,
0x9f
,
0x5f
,
0xdf
,
0x3f
,
0xbf
,
0x7f
,
0xff
};
#define SPI_CORE_CLK 250000000U
#define SPI_CS 0x00
#define SPI_CS_LEN_LONG (1 << 25)
#define SPI_CS_DMA_LEN (1 << 24)
#define SPI_CS_CSPOL2 (1 << 23)
#define SPI_CS_CSPOL1 (1 << 22)
#define SPI_CS_CSPOL0 (1 << 21)
#define SPI_CS_RXF (1 << 20)
#define SPI_CS_RXR (1 << 19)
#define SPI_CS_TXD (1 << 18)
#define SPI_CS_RXD (1 << 17)
#define SPI_CS_DONE (1 << 16)
#define SPI_CS_LEN (1 << 13)
#define SPI_CS_REN (1 << 12)
#define SPI_CS_ADCS (1 << 11)
#define SPI_CS_INTR (1 << 10)
#define SPI_CS_INTD (1 << 9)
#define SPI_CS_DMAEN (1 << 8)
#define SPI_CS_TA (1 << 7)
#define SPI_CS_CSPOL (1 << 6)
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
#define SPI_CS_CPOL (1 << 3)
#define SPI_CS_CPHA (1 << 2)
#define SPI_CS_MASK 0x3
#define SPI_FIFO 0x04
#define SPI_CLK 0x08
#define SPI_CLK_MASK 0xffff
#define SPI_DLEN 0x0c
#define SPI_DLEN_MASK 0xffff
#define SPI_LTOH 0x10
#define SPI_LTOH_MASK 0xf
#define SPI_DC 0x14
#define SPI_DC_RPANIC_SHIFT 24
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
#define SPI_DC_RDREQ_SHIFT 16
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
#define SPI_DC_TPANIC_SHIFT 8
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
#define SPI_DC_TDREQ_SHIFT 0
#define SPI_DC_TDREQ_MASK 0xff
int
rt_hw_spi_
bus_
init
(
void
);
int
rt_hw_spi_init
(
void
);
#endif
bsp/raspberry-pi/raspi3-64/rtconfig.h
浏览文件 @
f6a13de0
...
...
@@ -113,6 +113,7 @@
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_SDIO_DEBUG
#define RT_USING_SPI
#define RT_USING_WDT
/* Using USB */
...
...
@@ -197,6 +198,9 @@
#define RT_USING_SYSTIMER3
#define BSP_USING_I2C
#define BSP_USING_I2C1
#define BSP_USING_SPI
#define BSP_USING_SPI0_BUS
#define BSP_USING_SPI0_DEVICE0
#define BSP_USING_WDT
#define BSP_USING_SDIO
#define BSP_USING_SDIO0
...
...
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