Merge pull request #3217 from essemi-yuzr/master

Add essemi/ES32F0271 BSP drivers

bsp/essemi/es32f0271/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40002
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=2048
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_LCD_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_SOC_ES32F0271LT=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+
+#
+# PIN Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# UART Drivers
+#
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+
+#
+# SPI Drivers
+#
+# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_SPI2 is not set
+
+#
+# I2C Drivers
+#
+# CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_I2C2 is not set
+
+#
+# HWtimer Drivers
+#
+# CONFIG_BSP_USING_HWTIMER1 is not set
+
+#
+# PWM Drivers
+#
+# CONFIG_BSP_USING_PWM_GP16C2T1 is not set
+# CONFIG_BSP_USING_PWM_GP16C2T4 is not set
+
+#
+# RTC Drivers
+#
+# CONFIG_BSP_USING_RTC is not set
+
+#
+# ADC Drivers
+#
+# CONFIG_BSP_USING_ADC is not set
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Offboard Peripheral Drivers
+#

bsp/essemi/es32f0271/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ES32F0271LT
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "drivers/Kconfig"

bsp/essemi/es32f0271/README.md

+# ES-PDS-ES32F0271 开发板 BSP 说明
+标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT
+
+## 1. 简介
+
+本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+主要内容如下：
+ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。
+
+ES-PDS-ES32F0271-V1.1
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH
+- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
+- 常用外设
+  - 可调电阻：1个，(PC03)
+  - LED：2个，(PD03/PB08)
+  - 五轴按键：
+- 常用接口：GPIO、UART、SPI、I2C
+- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
+
+外设支持:
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                            |
+| :---------------- | :----------: | :------------------------------------|
+| **片上外设**      | **支持情况** | **备注**                            |
+| GPIO              |     支持     | GPIOs                                |
+| UART              |     支持     | UART1/2/3                            |
+| SPI               |     支持     | SPI1/2                               |
+| I2C               |     支持     | I2C1/2                               |
+| PWM               |     支持     | PWM1/2                               |
+| TIMER             |     支持     | TIMER1                               |
+| RTC               |     支持     | RTC                                  |
+| ADC               |     支持     | ADC                                  |
+
+### 1.2  注意事项
+
+- 本BSP中，SPI2和PWM2不能同时使用
+
+更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
+
+## 2. 快速上手
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+### 硬件连接
+
+使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。
+
+ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1
+
+### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
+
+### 运行结果
+
+下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.2 build Oct 31 2019
+ 2006 - 2019 Copyright by rt-thread team
+msh >
+```
+## 3. 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+## 4. 联系人信息
+
+- [yuzr](https://github.com/essemi-yuzr) 
+
+## 5. 参考
+
+- [ EastSoft 官网](http://www.essemi.com)
+

bsp/essemi/es32f0271/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+objs = []
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/essemi/es32f0271/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/essemi/es32f0271/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/essemi/es32f0271/applications/main.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN 61
+
+int main(void)
+{
+    /* LED pin configuration */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(1000);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(1000);
+    }
+}

bsp/essemi/es32f0271/drivers/Kconfig

+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        menu "PIN Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+        endmenu
+
+        menu "UART Drivers"
+            config BSP_USING_UART1
+                bool "Enable UART1 PB06/PB07(T/R)"
+                select RT_USING_SERIAL
+                default y
+
+            config BSP_USING_UART2
+                bool "Enable UART2 PA02/PA03(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART3
+                bool "Enable UART3 PC06/PC07(T/R)"
+                select RT_USING_SERIAL
+                default n
+        endmenu
+
+        menu "SPI Drivers"
+            config BSP_USING_SPI1
+                bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+
+            config BSP_USING_SPI2
+                bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+                depends on !BSP_USING_PWM_GP16C2T4
+        endmenu
+
+        menu "I2C Drivers"
+            config BSP_USING_I2C1
+                bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)"
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_I2C2
+                bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)"
+                select RT_USING_I2C
+                default n
+        endmenu
+
+        menu "HWtimer Drivers"
+
+            config BSP_USING_HWTIMER1
+                bool "Using timer1"
+                select RT_USING_HWTIMER
+                default n
+        endmenu
+
+        menu "PWM Drivers"
+
+            config BSP_USING_PWM_GP16C2T1
+                bool "Using PWM_1(GP16C2T1) PB01/PB02"
+                select RT_USING_PWM
+                default n
+
+            config BSP_USING_PWM_GP16C2T4
+                bool "Using PWM2(GP16C2T4) PB12/PB14"
+                select RT_USING_PWM
+                default n
+                depends on !BSP_USING_SPI2
+
+        endmenu
+
+        menu "RTC Drivers"
+            config BSP_USING_RTC
+                bool "Using RTC"
+                select RT_USING_RTC
+                default n
+        endmenu
+
+        menu "ADC Drivers"
+            config BSP_USING_ADC
+                bool "Using ADC"
+                select RT_USING_ADC
+                default n
+        endmenu
+
+    endmenu
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "Offboard Peripheral Drivers"
+
+    endmenu
+
+endmenu

bsp/essemi/es32f0271/drivers/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split('''
+board.c
+''')
+
+# add gpio code
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
+    src += ['drv_uart.c']
+
+# add spi driver code
+if  GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'):
+    src += ['drv_spi.c']
+
+# add i2c driver code
+if  GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
+    src += ['drv_i2c.c']
+
+# add pwm driver code
+if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'):
+    src += ['drv_pwm.c']
+
+# add hwtimer driver code
+if GetDepend('BSP_USING_HWTIMER1'):
+    src += ['drv_hwtimer.c']
+
+# add rtc driver code
+if GetDepend(['BSP_USING_RTC']):
+    src += ['drv_rtc.c']
+
+# add adc driver code
+if GetDepend(['BSP_USING_ADC']):
+    src += ['drv_adc.c']
+
+CPPPATH = [cwd]
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/essemi/es32f0271/drivers/board.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+#include "md_gpio.h"
+
+/**
+ * @addtogroup es32f0
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+}
+
+/*******************************************************************************
+ * Function Name  : SystemClock_Configuration
+ * Description    : Configures the System Clock.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SystemClock_Config(void)
+{
+    /*-------------------------Clock Config-------------------------/
+     * Config system clock to 48MHz of which the clock source
+     * is PLL0.
+     */
+    
+    //
+    // Open PLL0/HRC then wait it ready.
+    //
+    SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK);
+    SET_BIT(RCU->CON, RCU_CON_HRCON_MSK);
+
+    /* Wait HRC clock steady. */
+    while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK));
+
+    //
+    // Change system clock source,PLL0,48MHz.
+    //
+    /* Chose PLL0 as system clock. */
+    MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS));
+    /* Config mul of PLL0. */
+    MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS));
+
+    //
+    // Start to change system clock and wait it ready.
+    //
+    /* Config flash read wait time. */
+    MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS));
+    /* Start to change. */
+    SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK);
+
+    /* Wait system clock ready. */
+    while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK));
+
+    //
+    // Remember the system clock.
+    //
+    SystemCoreClock = 48000000;
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    /* ticks = sysclk / RT_TICK_PER_SECOND */
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/*@}*/
+/**
+ * This function will initial ES32F0 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /*System Clock Configuration */
+    SystemClock_Config();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+

bsp/essemi/es32f0271/drivers/board.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "es32f0271.h"
+
+#define ES32F0_SRAM_SIZE    0x2000
+#define ES32F0_SRAM_END     (0x20000000 + ES32F0_SRAM_SIZE)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+
+#define HEAP_END    ES32F0_SRAM_END
+
+void rt_hw_board_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_adc.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_adc.h"
+#include "md_gpio.h"
+#include "md_adc.h"
+#include "md_rcu.h"
+#include "md_syscfg.h"
+
+#ifdef RT_USING_ADC
+
+#define BSP_ADC_CHANNEL_NUM 8
+
+/* define adc instance */
+static struct rt_adc_device _device_adc0;
+
+/* enable or disable adc */
+static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    if (enabled)
+    {
+        md_adc_enable_ssen_ss0en(ADC);
+    }
+    else
+    {
+        md_adc_disable_ssen_ss0en(ADC);
+    }
+
+    return RT_EOK;
+}
+
+static void _adc_channel_config(rt_uint32_t channel)
+{
+    /* select gpio pin as adc function */
+    switch (channel)
+    {
+    case  0:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG);
+        break;
+    case  1:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG);
+        break;
+    case  2:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG);
+        break;
+    case  3:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG);
+        break;
+    case  4:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG);
+        break;
+    case  5:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG);
+        break;
+    case  6:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG);
+        break;
+    case  7:
+        md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG);
+        break;
+    default:
+        break;
+    }
+}
+
+static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM];
+    rt_uint32_t i;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    /* config adc channel */
+    _adc_channel_config(channel);
+
+    md_adc_set_swtri_ss0(ADC);
+
+    while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0);
+
+    for (i=0; i<BSP_ADC_CHANNEL_NUM; i++)
+        chn_data[i] = md_adc_get_ss0_data(ADC);
+
+    *value = chn_data[channel];
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops es32f0_adc_ops =
+{
+    es32f0_adc_enabled,
+    es32f0_get_adc_value,
+};
+
+int rt_hw_adc_init(void)
+{
+    int result = RT_EOK;
+
+    md_rcu_enable_apb2en_adcen(RCU);
+
+    md_syscfg_enable_cfg_currgen(SYSCFG);
+    md_syscfg_enable_cfg_vrefen(SYSCFG);
+    md_syscfg_set_cfg_vlrs(SYSCFG, 7);
+
+    md_adc_set_ss0_con_sel(ADC, MD_ADC_SS_CON_SEL_SW);
+    md_adc_set_ss0_con_type(ADC, MD_ADC_SS_CON_TYPE_EDGE);
+    md_adc_set_frf_ffrst(ADC);
+    md_adc_set_ss0_mux0_mux7(ADC, MD_ADC_SS_MUX_ADIN7);
+    md_adc_set_ss0_mux0_mux6(ADC, MD_ADC_SS_MUX_ADIN6);
+    md_adc_set_ss0_mux0_mux5(ADC, MD_ADC_SS_MUX_ADIN5);
+    md_adc_set_ss0_mux0_mux4(ADC, MD_ADC_SS_MUX_ADIN4);
+    md_adc_set_ss0_mux0_mux3(ADC, MD_ADC_SS_MUX_ADIN3);
+    md_adc_set_ss0_mux0_mux2(ADC, MD_ADC_SS_MUX_ADIN2);
+    md_adc_set_ss0_mux0_mux1(ADC, MD_ADC_SS_MUX_ADIN1);
+    md_adc_set_ss0_mux0_mux0(ADC, MD_ADC_SS_MUX_ADIN0);
+    md_adc_enable_ier_ss0ie(ADC);
+    md_adc_set_ss0_end_end(ADC, 7);
+    md_adc_enable_ss0_end_ie7(ADC);
+    md_adc_set_gainl_ch7pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch6pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch5pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch4pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch3pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch2pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch1pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_gainl_ch0pga(ADC, MD_ADC_GAIN_CHPGA_X2);
+    md_adc_set_srate(ADC, MD_ADC_SRATE_CLKDIV1 | ADC_SRATE_CKEN_MSK);
+
+    rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, ADC);
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_adc_init);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_adc.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_ADC_H__
+#define DRV_ADC_H__
+
+int rt_hw_adc_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_gpio.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, gpio_index}
+#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
+
+/* ES32F0 GPIO driver */
+struct pin_index
+{
+    int index;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+static const struct pin_index pins[] =
+{
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(2, C, 13),
+    __ES32F0_PIN(3, C, 14),
+    __ES32F0_PIN(4, C, 15),
+    __ES32F0_PIN(5, D, 14),
+    __ES32F0_PIN(6, D, 15),
+    __ES32F0_PIN(7, D, 13),
+    __ES32F0_PIN(8, C, 0),
+    __ES32F0_PIN(9, C, 1),
+    __ES32F0_PIN(10, C, 2),
+    __ES32F0_PIN(11, C, 3),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(14, A, 0),
+    __ES32F0_PIN(15, A, 1),
+    __ES32F0_PIN(16, A, 2),
+    __ES32F0_PIN(17, A, 3),
+    __ES32F0_PIN(18, D, 0),
+    __ES32F0_PIN(19, D, 1),
+    __ES32F0_PIN(20, A, 4),
+    __ES32F0_PIN(21, A, 5),
+    __ES32F0_PIN(22, A, 6),
+    __ES32F0_PIN(23, A, 7),
+    __ES32F0_PIN(24, C, 4),
+    __ES32F0_PIN(25, C, 5),
+    __ES32F0_PIN(26, B, 0),
+    __ES32F0_PIN(27, B, 1),
+    __ES32F0_PIN(28, B, 2),
+    __ES32F0_PIN(29, B, 10),
+    __ES32F0_PIN(30, B, 11),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(33, B, 12),
+    __ES32F0_PIN(34, B, 13),
+    __ES32F0_PIN(35, B, 14),
+    __ES32F0_PIN(36, B, 15),
+    __ES32F0_PIN(37, C, 6),
+    __ES32F0_PIN(38, C, 7),
+    __ES32F0_PIN(39, C, 8),
+    __ES32F0_PIN(40, C, 9),
+    __ES32F0_PIN(41, A, 8),
+    __ES32F0_PIN(42, A, 9),
+    __ES32F0_PIN(43, A, 10),
+    __ES32F0_PIN(44, A, 11),
+    __ES32F0_PIN(45, A, 12),
+    __ES32F0_PIN(46, A, 13),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(49, A, 14),
+    __ES32F0_PIN(50, A, 15),
+    __ES32F0_PIN(51, C, 10),
+    __ES32F0_PIN(52, C, 11),
+    __ES32F0_PIN(53, C, 12),
+    __ES32F0_PIN(54, D, 2),
+    __ES32F0_PIN(55, B, 3),
+    __ES32F0_PIN(56, B, 4),
+    __ES32F0_PIN(57, B, 5),
+    __ES32F0_PIN(58, B, 6),
+    __ES32F0_PIN(59, B, 7),
+    __ES32F0_PIN(60, D, 3),
+    __ES32F0_PIN(61, B, 8),
+    __ES32F0_PIN(62, B, 9),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {0, EXTI_0to1_IRQn},
+    {1, EXTI_0to1_IRQn},
+    {2, EXTI_2to3_IRQn},
+    {3, EXTI_2to3_IRQn},
+    {4, EXTI_4to15_IRQn},
+    {5, EXTI_4to15_IRQn},
+    {6, EXTI_4to15_IRQn},
+    {7, EXTI_4to15_IRQn},
+    {8, EXTI_4to15_IRQn},
+    {9, EXTI_4to15_IRQn},
+    {10, EXTI_4to15_IRQn},
+    {11, EXTI_4to15_IRQn},
+    {12, EXTI_4to15_IRQn},
+    {13, EXTI_4to15_IRQn},
+    {14, EXTI_4to15_IRQn},
+    {15, EXTI_4to15_IRQn},
+};
+
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+    return index;
+};
+
+void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Write GPIO */
+    if (value == 0)
+        SET_BIT(index->gpio->BSBR, 0x1<<(index->pin+16));
+    else
+        SET_BIT(index->gpio->BSBR, 0x1<<index->pin);
+}
+
+int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+    value = PIN_LOW;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    /* Read the GPIO value with the spcified index */
+    value = (index->gpio->IDATA & (0x1<<index->pin)) != 0;
+
+    return value;
+}
+
+void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_TypeDef *gpiox;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Get the IO port */
+    gpiox = index->gpio;
+
+    /* Config GPIO */
+    switch(mode)
+    {
+        case PIN_MODE_OUTPUT:
+        {
+            /* pushpull & output & 16mA */
+            MODIFY_REG(gpiox->MOD, (0x3<<(index->pin*2)), (0x1<<(index->pin*2)));
+            CLEAR_BIT(gpiox->OT, (0x1<<index->pin));
+            CLEAR_BIT(gpiox->DS, (0x1<<index->pin));
+            break;
+        }
+        case PIN_MODE_OUTPUT_OD:
+        {
+            /* opendrain & output & 16mA */
+            MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x1<<index->pin));
+            SET_BIT(gpiox->OT, (0x1<<index->pin));
+            CLEAR_BIT(gpiox->DS, (0x1<<index->pin));
+            break;
+        }
+        case PIN_MODE_INPUT:
+        {
+            /* input & no pull & CMOS & filter */
+            MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
+            MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x0<<index->pin));
+            SET_BIT(gpiox->IST, (0x1<<index->pin));
+            SET_BIT(gpiox->FIR, (0x1<<index->pin));
+            break;
+        }
+        case PIN_MODE_INPUT_PULLUP:
+        {
+            /* input & pull up & CMOS & filter */
+            MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
+            MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x1<<index->pin));
+            SET_BIT(gpiox->IST, (0x1<<index->pin));
+            SET_BIT(gpiox->FIR, (0x1<<index->pin));
+            break;
+        }
+        case PIN_MODE_INPUT_PULLDOWN:
+        {
+            /* input & pull down & CMOS & filter */
+            MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
+            MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x2<<index->pin));
+            SET_BIT(gpiox->IST, (0x1<<index->pin));
+            SET_BIT(gpiox->FIR, (0x1<<index->pin));
+            break;
+        }
+        default:
+        {
+            /* output */
+            MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x1<<index->pin));
+        }
+    }
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
+{
+    rt_int32_t mapindex = gpio_pin & 0x00FF;
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                               rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    /* pin no. convert to dec no. */
+    for (irqindex = 0; irqindex < 16; irqindex++)
+    {
+        if ((0x01 << irqindex) == index->pin)
+        {
+            break;
+        }
+    }
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = index->pin & 0x00FF;
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                               rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    GPIO_TypeDef *gpiox;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    /* Get the IO port */
+    gpiox = index->gpio;
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        /* pin no. convert to dec no. */
+        for (irqindex = 0; irqindex < 16; irqindex++)
+        {
+            if ((0x01 << irqindex) == index->pin)
+            {
+                break;
+            }
+        }
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+        level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+        irqmap = &pin_irq_map[irqindex];
+
+        /* Config EXTI */
+        MODIFY_REG(gpiox->MOD, (0x3<<index->pin), (0x0<<index->pin));
+        SET_BIT(gpiox->FIR, index->pin);
+        SET_BIT(gpiox->IST, index->pin);
+        MODIFY_REG(((uint32_t *)(&EXTI->ICFG1))[index->pin/8],
+                    0xF<<(index->pin%8),
+                    (((uint32_t)(index->gpio) - AHB2_BASE)/0x400)<<(index->pin%8));
+        SET_BIT(EXTI->DB, 0x1<<index->pin);
+        
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+            case PIN_IRQ_MODE_RISING:
+            {
+                /* pull down the pin */
+                MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x2<<index->pin));
+                /* Enable EXTI rising interrupt and disable falling interrupt */
+                SET_BIT(EXTI->RTS, (0x1<<index->pin));
+                CLEAR_BIT(EXTI->FTS, (0x1<<index->pin));
+                break;
+            }
+            case PIN_IRQ_MODE_FALLING:
+            {
+                /* pull up the pin */
+                MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x1<<index->pin));
+                /* Enable EXTI falling interrupt and disable rising interrupt */
+                CLEAR_BIT(EXTI->RTS, (0x1<<index->pin));
+                SET_BIT(EXTI->FTS, (0x1<<index->pin));
+                break;
+            }
+            case PIN_IRQ_MODE_RISING_FALLING:
+            {
+                /* pull up the pin */
+                MODIFY_REG(gpiox->PUD, (0x3<<index->pin), (0x1<<index->pin));
+                /* Enable EXTI falling interrupt and enable rising interrupt */
+                SET_BIT(EXTI->RTS, (0x1<<index->pin));
+                SET_BIT(EXTI->FTS, (0x1<<index->pin));
+                break;
+            }
+        }
+
+        /* Enable EXTI interrupt */
+        SET_BIT(EXTI->IER, (0x1<<index->pin));
+        NVIC_EnableIRQ(irqmap->irqno);
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_ENOSYS;
+        }
+        NVIC_DisableIRQ(irqmap->irqno);
+    }
+    else
+    {
+        return RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _es32f0_pin_ops =
+{
+    es32f0_pin_mode,
+    es32f0_pin_write,
+    es32f0_pin_read,
+    es32f0_pin_attach_irq,
+    es32f0_pin_detach_irq,
+    es32f0_pin_irq_enable,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+    
+    /* Open IO clock */
+    SET_BIT(RCU->AHBEN, RCU_AHBEN_GPDEN_MSK|RCU_AHBEN_GPCEN_MSK            \
+                                |RCU_AHBEN_GPBEN_MSK|RCU_AHBEN_GPAEN_MSK);
+
+    /* register IO device */
+    result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
+{
+    uint16_t irqno;
+    /* pin no. convert to dec no. */
+    for (irqno = 0; irqno < 16; irqno++)
+    {
+        if ((0x01 << irqno) == GPIO_Pin)
+        {
+            break;
+        }
+    }
+    if (irqno == 16)
+        return;
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+    /* Read the exti interrupt then clear the flag */
+    if ((EXTI->RIF & (0x1<<GPIO_Pin)) != RESET)
+    {
+        SET_BIT(EXTI->ICR, 0x1<<GPIO_Pin);
+        pin_irq_hdr(GPIO_Pin);
+    }
+}
+
+void EXTI0_1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(0);
+    GPIO_EXTI_Callback(1);
+    rt_interrupt_leave();
+}
+
+void EXTI2_3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(2);
+    GPIO_EXTI_Callback(3);
+    rt_interrupt_leave();
+}
+
+void EXTI4_15_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(4);
+    GPIO_EXTI_Callback(5);
+    GPIO_EXTI_Callback(6);
+    GPIO_EXTI_Callback(7);
+    GPIO_EXTI_Callback(8);
+    GPIO_EXTI_Callback(9);
+    GPIO_EXTI_Callback(10);
+    GPIO_EXTI_Callback(11);
+    GPIO_EXTI_Callback(12);
+    GPIO_EXTI_Callback(13);
+    GPIO_EXTI_Callback(14);
+    GPIO_EXTI_Callback(15);
+    rt_interrupt_leave();
+}
+
+#endif

bsp/essemi/es32f0271/drivers/drv_gpio.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_hwtimer.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_hwtimer.h>
+#include <board.h>
+#include "md_ad16c4t.h"
+#include "md_rcu.h"
+
+#ifdef RT_USING_HWTIMER
+
+/* Defien the hardware timer control struct */
+struct es32f0_hwtimer_dev
+{
+    rt_hwtimer_t parent;
+    AD16C4T_TypeDef *hwtimer_periph;
+    IRQn_Type IRQn;
+};
+
+#ifdef BSP_USING_HWTIMER1
+static struct es32f0_hwtimer_dev hwtimer1;
+
+void BS16T1_IRQHandler(void)
+{
+    /* if BS16T1 IT */
+    if (BS16T1->IFM & AD16C4T_RIF_UI_MSK)
+    {
+        SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK);
+        rt_device_hwtimer_isr(&hwtimer1.parent);
+
+        if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
+        {
+            CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK);
+        }
+    }
+}
+#endif
+
+static struct rt_hwtimer_info es32f0_hwtimer_info =
+{
+    48000000, /* maximum count frequency */
+    1,        /* minimum count frequency */
+    65535,    /* counter maximum value */
+    HWTIMER_CNTMODE_UP
+};
+
+static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    if (1 == state)
+    {
+        /* Set frequency */
+        WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1));
+        /* Enable timer IT */
+        SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK);
+        NVIC_EnableIRQ(hwtimer->IRQn);
+    }
+    else
+    {
+        /* Dsiable timer IT */
+        SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK);
+    }
+}
+
+static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
+                                     rt_uint32_t cnt,
+                                     rt_hwtimer_mode_t mode)
+{
+    struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    WRITE_REG(hwtimer->hwtimer_periph->AR, cnt);
+    SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
+
+    return RT_EOK;
+}
+
+static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
+{
+    struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
+}
+
+static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
+{
+    struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
+    uint32_t hwtimer_count = 0;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT);
+
+    return hwtimer_count;
+}
+
+static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
+                                       rt_uint32_t cmd,
+                                       void *args)
+{
+    rt_err_t ret = RT_EOK;
+    rt_uint32_t freq = 0;
+    struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
+
+    RT_ASSERT(hwtimer != RT_NULL);
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+        freq = *(rt_uint32_t *)args;
+        if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq))
+        {
+            ret = RT_EINVAL;
+        }
+        /* Set frequency */
+        WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1));
+        break;
+
+    case HWTIMER_CTRL_STOP:
+        CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
+        break;
+
+    default:
+        ret = RT_EINVAL;
+        break;
+    }
+
+    return ret;
+}
+
+static struct rt_hwtimer_ops es32f0_hwtimer_ops =
+{
+    es32f0_hwtimer_init,
+    es32f0_hwtimer_start,
+    es32f0_hwtimer_stop,
+    es32f0_hwtimer_count_get,
+    es32f0_hwtimer_control
+};
+
+int rt_hw_hwtimer_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+#ifdef BSP_USING_HWTIMER1
+    /*Open clock*/
+    SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK);
+
+    hwtimer1.hwtimer_periph     = BS16T1;
+    hwtimer1.IRQn               = BS16T1_IRQn;
+    hwtimer1.parent.info        = &es32f0_hwtimer_info;
+    hwtimer1.parent.ops         = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
+#endif
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_hwtimer.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_HWTIMER_H__
+#define DRV_HWTIMER_H__
+
+int rt_hw_hwtimer_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_i2c.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_i2c.h"
+#include "md_i2c.h"
+#include "md_gpio.h"
+
+#ifdef RT_USING_I2C
+
+#define TIMEOUT 0xF
+/* Define I2C hardware SCL timeout */
+#define I2C_TIMING_48MHZ_CLK100KHZ   ((0xBU<<28)|(4<<20)|(2<<16)|(0xF<<8)|(0x13))
+
+/**
+  * @brief:  I2C receive.
+  * @param:  i2cx, pointer to the I2Cx
+  * @param:  addr, address
+  * @param:  buf, send data buffer
+  * @param:  len, the length of buf
+  * @param:  timout, timeout
+  * @retval: rt_err_t
+  */
+static rt_err_t __i2c_master_recv(I2C_TypeDef *i2cx, rt_uint16_t addr,
+                          rt_uint8_t  *buf, rt_uint16_t len, rt_uint32_t timout)
+{
+    rt_uint32_t rt_timout;
+
+    //
+    // Config I2C transfer mode
+    //
+    md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT);
+    /* Config slaver address */
+    md_i2c_set_con2_sadd(i2cx, addr);
+    /* Config data size */
+    md_i2c_set_con2_nbytes(i2cx, len);
+    /* Reset TX FIFO */
+    md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET);
+    /* Config mode */
+    md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_READ);
+    /* Config auto-reload */
+    md_i2c_set_con2_reload(i2cx, MD_I2C_NORELOAD_MODE);
+    /* When NBYTES is matched, the communication will be automatically stop */
+    md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE);
+    /* Start the I2C communication */
+    md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION);
+
+    while (len > 0)
+    {
+        /* Wait Rx FIFO non-empty */
+        rt_timout = timout;
+        while (md_i2c_is_active_stat_rxe(i2cx) && (--rt_timout));
+        if (rt_timout == 0)
+            return RT_ETIMEOUT;
+
+        *buf++ = md_i2c_recv(i2cx);
+        len--;
+    }
+
+    return RT_EOK;
+}
+
+/**
+  * @brief:  I2C send.
+  * @param:  i2cx, pointer to the I2Cx
+  * @param:  addr, address
+  * @param:  buf, send data buffer
+  * @param:  len, the length of buf
+  * @param:  timout, timeout
+  * @retval: rt_err_t
+  */
+static rt_err_t __i2c_master_send(I2C_TypeDef *i2cx, rt_uint16_t addr,
+                          rt_uint8_t  *buf, rt_uint16_t len, rt_uint32_t timout)
+{
+    rt_uint32_t rt_timout;
+    rt_uint8_t index;
+
+    //
+    // Config I2C transfer mode
+    //
+    md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT);
+    /* Config slaver address */
+    md_i2c_set_con2_sadd(i2cx, addr);
+    /* Config data size */
+    md_i2c_set_con2_nbytes(i2cx, len);
+    /* Reset TX FIFO */
+    md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET);
+    /* Config mode */
+    md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_WRITE);
+    /* Enable auto-end */
+    md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE);
+
+    //
+    // Check if the bus is busy
+    //
+    /* Wait bus to be ready */
+    rt_timout   = timout;
+    while ((READ_BIT(i2cx->STAT, I2C_STAT_BUSY_MSK) == I2C_STAT_BUSY_MSK) && (--rt_timout));
+    if (rt_timout == 0)
+        return RT_EBUSY;
+
+    //
+    // Start to send
+    //
+    if (len <= 8)
+    {
+        for (index = 0; index < len; index++)
+            md_i2c_send(i2cx, *buf++);
+
+        len = 0;
+    }
+    else
+    {
+        for (index = 0; index < 8; index++)
+            md_i2c_send(i2cx, *buf++);
+
+        len -= 8;
+    }
+
+    /* Start the I2C communication */
+    md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION);
+
+    while (len > 0)
+    {
+        rt_timout   = timout;
+        while (md_i2c_is_active_stat_txf(i2cx) && (--rt_timout));
+        if (rt_timout == 0)
+            return RT_ETIMEOUT;
+
+        md_i2c_send(i2cx, *buf++);
+        len--;
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    rt_uint32_t i;
+    rt_err_t ret = RT_ERROR;
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        if (msg->flags & RT_I2C_RD)
+        {
+            if (__i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+        else
+        {
+            if (__i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+    }
+
+    ret = i;
+
+out:
+    i2c_dbg("send stop condition\n");
+
+    return ret;
+}
+
+const struct rt_i2c_bus_device_ops es32f0_i2c_ops =
+{
+    es32f0_master_xfer,
+    RT_NULL,
+    RT_NULL,
+};
+
+static void _i2c_init(void)
+{
+    md_i2c_inittypedef I2C_Init =
+    {
+        .Timing     = CLK100kHz48M,
+        .Address1   = 0x55 << 1,
+        .AddrSize   = MD_I2C_ADDRESSINGMODE_7BIT,
+        .DualAddressMode    = MD_I2C_DUALADDRESS_DISABLE,
+        .Address2   = 0xAA,
+        .Address2Masks      = MD_I2C_ADDR2_NOMASK
+    };
+
+#ifdef BSP_USING_I2C1
+    /* Open I2C clock */
+    SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C1EN_MSK);
+
+    /* GPIO configuration */
+    md_gpio_set_pull        (GPIOC, MD_GPIO_PIN_12,  MD_GPIO_PULL_UP);
+    md_gpio_set_pull        (GPIOD, MD_GPIO_PIN_2,   MD_GPIO_PULL_UP);
+    md_gpio_set_output_type (GPIOC, MD_GPIO_PIN_12,  MD_GPIO_OUTPUT_OPENDRAIN);
+    md_gpio_set_output_type (GPIOD, MD_GPIO_PIN_2,   MD_GPIO_OUTPUT_OPENDRAIN);
+    md_gpio_set_mode        (GPIOC, MD_GPIO_PIN_12,  MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOD, MD_GPIO_PIN_2,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function8_15(GPIOC, MD_GPIO_PIN_12,  MD_GPIO_AF1);
+    md_gpio_set_function0_7 (GPIOD, MD_GPIO_PIN_2,   MD_GPIO_AF1);
+
+    //
+    // Config I2C
+    //
+    md_i2c_init(I2C1, &I2C_Init);
+#endif
+
+#ifdef BSP_USING_I2C2
+    /* Open I2C clock */
+    SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C2EN_MSK);
+
+    /* GPIO configuration */
+    md_gpio_set_pull        (GPIOB, MD_GPIO_PIN_10,  MD_GPIO_PULL_UP);
+    md_gpio_set_pull        (GPIOB, MD_GPIO_PIN_11,  MD_GPIO_PULL_UP);
+    md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_10,  MD_GPIO_OUTPUT_OPENDRAIN);
+    md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_11,  MD_GPIO_OUTPUT_OPENDRAIN);
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_10,  MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_11,  MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_10,  MD_GPIO_AF1);
+    md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_11,  MD_GPIO_AF1);
+
+    //
+    // Config I2C
+    //
+    md_i2c_init(I2C2, &I2C_Init);
+#endif
+}
+
+#ifdef BSP_USING_I2C2
+static struct rt_i2c_bus_device i2c_device2;
+#endif
+
+#ifdef BSP_USING_I2C1
+static struct rt_i2c_bus_device i2c_device1;
+#endif
+int rt_hw_i2c_init(void)
+{
+    _i2c_init();
+
+#ifdef BSP_USING_I2C2
+    /* define i2c Instance */
+    rt_memset((void *)&i2c_device2, 0, sizeof(struct rt_i2c_bus_device));
+    i2c_device2.ops = &es32f0_i2c_ops;
+    i2c_device2.priv = I2C2;
+    rt_i2c_bus_device_register(&i2c_device2, "i2c2");
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* define i2c Instance */
+    rt_memset((void *)&i2c_device1, 0, sizeof(struct rt_i2c_bus_device));
+    i2c_device1.ops = &es32f0_i2c_ops;
+    i2c_device1.priv = I2C1;
+    rt_i2c_bus_device_register(&i2c_device1, "i2c1");
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_i2c.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_I2C_H__
+#define DRV_I2C_H__
+
+int rt_hw_i2c_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_pwm.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+#include "md_gpio.h"
+
+/* PWM device control struct */
+struct pwm_dev_ctrl {
+    AD16C4T_TypeDef *timx;
+    rt_uint8_t  chnm;   /* Cannel number */
+    struct rt_pwm_configuration *cfg;
+};
+
+#ifdef BSP_USING_PWM_GP16C2T1
+
+/* Remember channel configuration */
+static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t1[2]  = {
+    [0] = {
+        .channel    = 1,
+        .period     = 0,
+        .pulse      = 0
+    },
+    [1] = {
+        .channel    = 2,
+        .period     = 0,
+        .pulse      = 0
+    }
+};
+
+/* Define static device */
+static struct rt_device_pwm pwm_dev_gp16c2t1;
+static struct pwm_dev_ctrl pwm_dev_gp16c2t1_ctrl;
+#endif
+#ifdef BSP_USING_PWM_GP16C2T4
+
+/* Remember channel configuration */
+static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t4[2]  = {
+    [0] = {
+        .channel    = 1,
+        .period     = 0,
+        .pulse      = 0
+    },
+    [1] = {
+        .channel    = 2,
+        .period     = 0,
+        .pulse      = 0
+    }
+};
+
+/* Define static device */
+static struct rt_device_pwm pwm_dev_gp16c2t4;
+static struct pwm_dev_ctrl pwm_dev_gp16c2t4_ctrl;
+#endif
+
+static void pwm_auto_config_freq(AD16C4T_TypeDef *timerx, uint32_t ns)
+{
+    uint32_t temp_ar;
+    uint32_t temp_pres = timerx->PRES & 0xFFFF;
+    uint32_t err_cnt = 0;
+
+    /* Automatic setting frequency division ratio */
+    while (err_cnt++ < 65536)
+    {
+        temp_ar = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1);
+        if (temp_ar <= 0xFFFF)
+            break;
+        temp_pres++;
+    }
+
+    /* Write back to PRES */
+    timerx->PRES    = (uint16_t)(temp_pres & 0xFFFF);
+    timerx->AR      = temp_ar;
+}
+
+static void pwm_set_duty(AD16C4T_TypeDef *timerx, uint8_t ch, uint32_t ns)
+{
+    uint32_t temp_pres = timerx->PRES & 0xFFFF;
+    uint64_t tmp = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1);
+
+    if (ch == 1)
+        WRITE_REG(timerx->CCVAL1, (uint32_t)tmp);
+    else if (ch == 2)
+        WRITE_REG(timerx->CCVAL2, (uint32_t)tmp);
+}
+
+static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    rt_err_t ret = RT_EOK;
+    struct pwm_dev_ctrl *dev_ctrl
+                    = (struct pwm_dev_ctrl *)device->parent.user_data;
+    struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
+    AD16C4T_TypeDef *timerx = (AD16C4T_TypeDef *)dev_ctrl->timx;
+
+    switch (cmd)
+    {
+        case PWM_CMD_ENABLE:
+        {
+            if (cfg->channel == 1)
+                SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK);
+            else if (cfg->channel == 2)
+                SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK);
+            break;
+        }
+        case PWM_CMD_DISABLE:
+        {
+            if (cfg->channel == 1)
+                CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK);
+            else if (cfg->channel == 2)
+                CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK);
+            break;
+        }
+        case PWM_CMD_SET:
+        {
+            /* count registers max 0xFFFF, auto adjust prescaler */
+            pwm_auto_config_freq(timerx, cfg->period);
+            pwm_set_duty(timerx, cfg->channel, cfg->pulse);
+            /* Remember configuration */
+            dev_ctrl->cfg[cfg->channel-1].period = cfg->period;
+            dev_ctrl->cfg[cfg->channel-1].pulse  = cfg->pulse;
+            break;
+        }
+        case PWM_CMD_GET:
+        {
+            cfg->period = dev_ctrl->cfg[cfg->channel-1].period;
+            cfg->pulse  = dev_ctrl->cfg[cfg->channel-1].pulse;
+            break;
+        }
+
+        default:
+            break;
+    }
+    return ret;
+}
+
+const static struct rt_pwm_ops es32f0_pwm_ops =
+{
+    es32f0_pwm_control
+};
+
+int rt_hw_pwm_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+#ifdef BSP_USING_PWM_GP16C2T1 /* 2 channels */
+    /* Open clock */
+    SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK);
+
+    /* GPIO configuration */
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_1,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_2,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_1,   MD_GPIO_AF5);
+    md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_2,   MD_GPIO_AF5);
+
+    /* Timer configuration */
+    MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, 
+                                (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS));
+    MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, 
+                                (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS));
+    SET_BIT(GP16C2T1->BDCFG, AD16C4T_BDCFG_GOEN_MSK);
+    SET_BIT(GP16C2T1->CON1, AD16C4T_CON1_CNTEN_MSK);
+
+    pwm_dev_gp16c2t1_ctrl.chnm       = 2;
+    pwm_dev_gp16c2t1_ctrl.timx       = GP16C2T1;
+    pwm_dev_gp16c2t1_ctrl.cfg        = pwm_ch_cfg_gp16c2t1;
+    /* Register PWM device */
+    ret = rt_device_pwm_register(&pwm_dev_gp16c2t1,
+                                "pwm1", &es32f0_pwm_ops, &pwm_dev_gp16c2t1_ctrl);
+#endif
+
+#ifdef BSP_USING_PWM_GP16C2T4 /* 2 channels */
+    /* Open clock */
+    SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK);
+
+    /* GPIO configuration */
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_12,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_14,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_12,   MD_GPIO_AF5);
+    md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_14,   MD_GPIO_AF5);
+
+    /* Timer configuration */
+    MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, 
+                                (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS));
+    MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, 
+                                (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS));
+    SET_BIT(GP16C2T4->BDCFG, AD16C4T_BDCFG_GOEN_MSK);
+    SET_BIT(GP16C2T4->CON1, AD16C4T_CON1_CNTEN_MSK);
+
+    pwm_dev_gp16c2t4_ctrl.chnm       = 2;
+    pwm_dev_gp16c2t4_ctrl.timx       = GP16C2T4;
+    pwm_dev_gp16c2t4_ctrl.cfg        = pwm_ch_cfg_gp16c2t4;
+    /* Register PWM device */
+    ret = rt_device_pwm_register(&pwm_dev_gp16c2t4,
+                                "pwm2", &es32f0_pwm_ops, &pwm_dev_gp16c2t4_ctrl);
+#endif
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_pwm_init);

bsp/essemi/es32f0271/drivers/drv_pwm.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_PWM_H__
+#define DRV_PWM_H__
+
+int rt_hw_pwm_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_rtc.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <string.h>
+#include "board.h"
+#include "drv_rtc.h"
+
+#ifdef RT_USING_RTC
+
+/**
+  * @brief Time structure
+  */
+typedef struct
+{
+    uint8_t hour;       /**< Hours */
+    uint8_t minute;     /**< Minutes */
+    uint8_t second;     /**< Seconds */
+    uint16_t sub_sec;   /**< Sub-seconds */
+} rtc_time_t;
+
+/**
+  * @brief Date structure
+  */
+typedef struct
+{
+    uint8_t week;   /**< Weeks */
+    uint8_t day;    /**< days */
+    uint8_t month;  /**< months */
+    uint8_t year;   /**< years */
+} rtc_date_t;
+
+static rt_uint32_t bcd_to_dec(rt_uint32_t bcd)
+{
+    return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10);
+}
+
+static void rtc_get_time(rtc_time_t *time)
+{
+    rt_uint32_t tmp = RTC->TIME;
+
+    time->second = bcd_to_dec(tmp & 0x7F);
+    time->minute = bcd_to_dec((tmp >> 8) & 0x7F);
+    time->hour   = bcd_to_dec((tmp >> 16) & 0x7F);
+
+    return;
+}
+
+static void rtc_get_date(rtc_date_t *date)
+{
+    uint32_t tmp = RTC->CAL;
+
+    date->day   = bcd_to_dec(tmp & 0x3F);
+    date->month = bcd_to_dec((tmp >> 8) & 0x1F);
+    date->year  = bcd_to_dec((tmp >> 16) & 0xFF);
+    date->week  = bcd_to_dec((RTC->TIME >> 24) & 0x7);
+
+    return;
+}
+
+static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    rt_err_t result = RT_EOK;
+
+    struct tm time_temp;
+    struct tm *pNow;
+    rt_uint16_t timout = 0xFFF;
+    rtc_time_t *time = rt_malloc(sizeof(rtc_time_t));
+    rtc_date_t *date = rt_malloc(sizeof(rtc_date_t));
+
+    switch (cmd)
+    {
+        case RT_DEVICE_CTRL_RTC_GET_TIME:
+        {
+            /* Wait RTC data ready then read */
+            while ((--timout)&&((RTC->STAT & RTC_STAT_SYNDONE_MSK) != RTC_STAT_SYNDONE_MSK));
+            if (timout == 0)
+                result = RT_ERROR;
+            /* Read */
+            rtc_get_time(time);
+            rtc_get_date(date);
+
+            time_temp.tm_sec    = time->second;
+            time_temp.tm_min    = time->minute;
+            time_temp.tm_hour   = time->hour;
+            time_temp.tm_wday   = date->week - 1;
+            time_temp.tm_mday   = date->day;
+            time_temp.tm_mon    = date->month - 1;
+            time_temp.tm_year   = date->year - 1900 + 2000;
+            *((time_t *)args) = mktime(&time_temp);
+            break;
+        }
+        case RT_DEVICE_CTRL_RTC_SET_TIME:
+        {
+            rt_enter_critical();
+            /* converts calendar time time into local time. */
+            pNow = localtime((const time_t *)args);
+            /* copy the statically located variable */
+            memcpy(&time_temp, pNow, sizeof(struct tm));
+            /* unlock scheduler. */
+            rt_exit_critical();
+
+            time->hour   = time_temp.tm_hour;
+            time->minute = time_temp.tm_min;
+            time->second = time_temp.tm_sec;
+            date->year   = time_temp.tm_year + 1900 - 2000;
+            date->month  = time_temp.tm_mon + 1;
+            date->day    = time_temp.tm_mday;
+            /* Stop RTC */
+            CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
+            WRITE_REG(RTC->TIME, ((time->hour/10)<<RTC_TIME_HOUR_T_POSS)  /* hour */
+                                |((time->hour%10)<<RTC_TIME_HOUR_U_POSS)
+                                |((time->minute/10)<<RTC_TIME_MIN_T_POSS)   /* minute */
+                                |((time->minute%10)<<RTC_TIME_MIN_U_POSS)
+                                |((time->second/10)<<RTC_TIME_SEC_T_POSS)   /* second */
+                                |((time->second%10)<<RTC_TIME_SEC_U_POSS));
+            WRITE_REG(RTC->CAL,  ((date->year/10)<<RTC_CAL_YEAR_T_POSS)   /* year */
+                                |((date->year%10)<<RTC_CAL_YEAR_U_POSS)
+                                |((date->month/10)<<RTC_CAL_MON_T_POS)     /* month */
+                                |((date->month%10)<<RTC_CAL_MON_U_POSS)
+                                |((date->day/10)<<RTC_CAL_DATE_T_POSS)   /* date */
+                                |((date->day%10)<<RTC_CAL_DATE_U_POSS));
+            /* start RTC */
+            SET_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
+            break;
+        }
+        case RT_DEVICE_CTRL_RTC_GET_ALARM:
+            break;
+
+        case RT_DEVICE_CTRL_RTC_SET_ALARM:
+            break;
+
+        default:
+            break;
+    }
+
+    rt_free(time);
+    rt_free(date);
+
+    return result;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops es32f0_rtc_ops =
+{
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    es32f0_rtc_control
+};
+#endif
+
+static struct rt_device rtc_dev;
+#define RTC_SOURCE_LOSC  0x1
+#define RTC_SOURCE_LRC   0x2
+int rt_hw_rtc_init(void)
+{
+    rt_err_t ret        = RT_EOK;
+    rt_uint16_t timout   = 0xFFFF;
+    rt_uint32_t rtc_clk = 32768-1;
+    rt_uint8_t  rtc_src = RTC_SOURCE_LOSC;
+
+    /*
+     * Config RTC clock
+     * We config the external 32.768K crystal as RTC clock source for the first
+     * choice. If external 32.768K crystal is not ready, we will choose LRC.
+     */
+    /* Enable LOSC then wait it ready */
+    if ((RCU->CON & RCU_CON_LOSCON_MSK) != RCU_CON_LOSCON_MSK)
+        SET_BIT(RCU->CON, RCU_CON_LOSCON_MSK);
+
+    /* Wait external 32.768K crystal ready */
+    while (((RCU->CON & RCU_CON_LOSCRDY_MSK) != RCU_CON_LOSCRDY_MSK)&&(--timout));
+    if (timout == 0)
+    {
+        /* We use LRC if external 32.768K crystal is not ready */
+        if ((RCU->CON & RCU_CON_LRCON_MSK) != RCU_CON_LRCON_MSK)
+            SET_BIT(RCU->CON, RCU_CON_LRCON_MSK);
+        /* Wait LRC ready */
+        timout = 0xFF;
+        while (((RCU->CON & RCU_CON_LRCRDY_MSK) != RCU_CON_LRCRDY_MSK)&&(--timout));
+        rtc_clk = 32000-1;
+        rtc_src = RTC_SOURCE_LRC;
+    }
+
+    /* Open RTC clock */
+    SET_BIT(RCU->AHBEN, RCU_AHBEN_RTCEN_MSK);
+
+    /* Reset RTC */
+    SET_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK);
+    CLEAR_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK);
+    CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
+
+    /* Config RTC clock source */
+    MODIFY_REG(RTC->CON, RTC_CON_CKSEL_MSK, rtc_src<<RTC_CON_CKSEL_POSS);
+    MODIFY_REG(RTC->CON, RTC_CON_PSCALE_MSK|RTC_CON_SCALE_MSK,
+                  ((rtc_clk&0x7F)<<RTC_CON_PSCALE_POSS)|
+                  (((rtc_clk>>7)&0xFF)<<RTC_CON_SCALE_POSS));
+
+    /* Set default time - Wed Oct 30 08:00:00 2019 */
+    WRITE_REG(RTC->TIME, (0x3<<RTC_TIME_WEEK_POSS)    /* week */
+                        |(0x0<<RTC_TIME_HOUR_T_POSS)  /* hour */
+                        |(0x8<<RTC_TIME_HOUR_U_POSS)
+                        |(0x0<<RTC_TIME_MIN_T_POSS)   /* minute */
+                        |(0x0<<RTC_TIME_MIN_U_POSS)
+                        |(0x0<<RTC_TIME_SEC_T_POSS)   /* second */
+                        |(0x0<<RTC_TIME_SEC_U_POSS));
+    WRITE_REG(RTC->CAL,  (0x1<<RTC_CAL_YEAR_T_POSS)   /* year */
+                        |(0x9<<RTC_CAL_YEAR_U_POSS)
+                        |(0x1<<RTC_CAL_MON_T_POS)     /* month */
+                        |(0x0<<RTC_CAL_MON_U_POSS)
+                        |(0x3<<RTC_CAL_DATE_T_POSS)   /* date */
+                        |(0x0<<RTC_CAL_DATE_U_POSS));
+
+    /* RTC start */
+    SET_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
+
+    rtc_dev.type = RT_Device_Class_RTC;
+    rtc_dev.rx_indicate = RT_NULL;
+    rtc_dev.tx_complete = RT_NULL;
+
+#ifdef RT_USING_DEVICE_OPS
+    rtc_dev.ops = &es32f0_rtc_ops;
+#else
+    rtc_dev.init = RT_NULL;
+    rtc_dev.open = RT_NULL;
+    rtc_dev.close = RT_NULL;
+    rtc_dev.read = RT_NULL;
+    rtc_dev.write = RT_NULL;
+    rtc_dev.control = es32f0_rtc_control;
+#endif
+
+    rtc_dev.user_data = RTC;
+
+    ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR);
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_rtc.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_RTC_H__
+#define DRV_RTC_H__
+
+int rt_hw_rtc_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_spi.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <string.h>
+#include <rthw.h>
+#include "board.h"
+#include "drv_spi.h"
+#include "md_spi.h"
+#include "md_gpio.h"
+
+#ifdef RT_USING_SPI
+
+#define SPITIMEOUT 0x0FFF
+
+static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf,
+                                            rt_int32_t len, rt_uint32_t tmout);
+static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf,
+                                            rt_int32_t len, rt_uint32_t tmout);
+static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf,
+                            rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout);
+
+/**
+  * @brief:  SPI single line send.
+  * @param:  device, pointer to the SPI device
+  * @param:  buf, send data buffer
+  * @param:  len, the length of buf
+  * @param:  tmout, timeout
+  * @retval: rt_err_t
+  */
+static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf,
+                                            rt_int32_t len, rt_uint32_t tmout)
+{
+    SPI_TypeDef *hspi;
+    rt_uint32_t rt_timout;
+    rt_uint8_t temp_data;
+
+    /* Get the SPI port */
+    hspi = (SPI_TypeDef *)device->bus->parent.user_data;
+
+    /* Open SPI if it is disabled */
+    if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK)
+        SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK);
+
+    while (len > 0)
+    {
+        /* Confirm that no data is being transmitted */
+        rt_timout   = tmout;
+        while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout));
+        if (rt_timout == 0)
+            return RT_ETIMEOUT;
+
+        /* Send data */
+        if (device->config.data_width == 8)
+        {
+            hspi->DATA  = *(rt_uint8_t *)buf;
+            buf++;
+            len--;
+        }
+        else if (device->config.data_width == 16)
+        {
+            hspi->DATA  = *(rt_uint16_t *)buf;
+            buf        += 2;
+            len        -= 2;
+        }
+        else
+            return RT_EINVAL;
+    }
+
+    /* At here, we have transmitted all the data.
+     * The next step is to clear the IT flag.
+     */
+    for (rt_uint8_t i = 0; i < md_spi_get_stat_rxflv(hspi); i++)
+        temp_data = hspi->DATA;
+    UNUSED(temp_data);
+    hspi->ICR   = hspi->RIF;
+
+    return RT_EOK;
+}
+
+/**
+  * @brief:  SPI single line receive.
+  * @param:  device, pointer to the SPI device
+  * @param:  buf, receive data buffer
+  * @param:  len, the length of buf
+  * @param:  tmout, timeout
+  * @retval: rt_err_t
+  */
+static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf,
+                                            rt_int32_t len, rt_uint32_t tmout)
+{
+    SPI_TypeDef *hspi;
+    rt_uint32_t rt_timout;
+
+    /* Get the SPI port */
+    hspi = (SPI_TypeDef *)device->bus->parent.user_data;
+
+    /* Open SPI if it is disabled */
+    if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK)
+        SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK);
+
+    /* Handle data in __spi_send_recv() function */
+    if (((device->config.mode & RT_SPI_SLAVE) == 0)
+                            && ((device->config.mode & RT_SPI_3WIRE) == 0))
+        __spi_send_recv(device, buf, buf, len, tmout);
+
+    while (len > 0)
+    {
+        /* Waiting for data */
+        rt_timout   = tmout;
+        while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout));
+        if (rt_timout == 0)
+            return RT_ETIMEOUT;
+
+        /* Send data */
+        if (device->config.data_width == 8)
+        {
+             *(rt_uint8_t *)buf = hspi->DATA;
+            buf++;
+            len--;
+        }
+        else if (device->config.data_width == 16)
+        {
+            *(rt_uint16_t *)buf  = hspi->DATA;
+            buf                 += 2;
+            len                 -= 2;
+        }
+        else
+            return RT_EINVAL;
+    }
+
+    /* At here, we have transmitted all the data.
+     * The next step is to clear the IT flag.
+     */
+    hspi->ICR   = hspi->RIF;
+
+    return RT_EOK;
+}
+
+/**
+  * @brief:  SPI two line transmission.
+  * @param:  device, pointer to the SPI device
+  * @param:  tbuf, send data buffer
+  * @param:  rbuf, receive data buffer
+  * @param:  len, the length of buf
+  * @param:  tmout, timeout
+  * @retval: rt_err_t
+  */
+static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf,
+                            rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout)
+{
+    SPI_TypeDef *hspi;
+    rt_uint32_t rt_timout;
+
+    /* Get the SPI port */
+    hspi = (SPI_TypeDef *)device->bus->parent.user_data;
+
+    /* Open SPI if it is disabled */
+    if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK)
+        SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK);
+
+    /* return error if SPI is in 1-line mode */
+    if ((device->config.mode & RT_SPI_3WIRE) == RT_SPI_3WIRE)
+        return RT_ERROR;
+
+    while (len > 0)
+    {
+        /* Confirm that no data is being transmitted */
+        rt_timout   = tmout;
+        while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout));
+        if (rt_timout == 0)
+            return RT_ETIMEOUT;
+
+        /* Send data */
+        if (device->config.data_width == 8)
+        {
+            hspi->DATA  = *(rt_uint8_t *)tbuf;
+            tbuf++;
+            len--;
+        }
+        else if (device->config.data_width == 16)
+        {
+            hspi->DATA  = *(rt_uint16_t *)tbuf;
+            tbuf       += 2;
+            len        -= 2;
+        }
+        else
+            return RT_EINVAL;
+
+        /* Waiting for data */
+        rt_timout   = tmout;
+        while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout));
+        if (rt_timout == 0)
+            return RT_ETIMEOUT;
+
+        /* Send data */
+        if (device->config.data_width == 8)
+        {
+             *(rt_uint8_t *)rbuf = hspi->DATA;
+            rbuf++;
+        }
+        else if (device->config.data_width == 16)
+        {
+            *(rt_uint16_t *)rbuf  = hspi->DATA;
+            rbuf                 += 2;
+        }
+    }
+
+    /* At here, we have transmitted all the data.
+     * The next step is to clear the IT flag.
+     */
+    hspi->ICR   = hspi->RIF;
+
+    return RT_EOK;
+}
+
+rt_err_t spi_configure(struct rt_spi_device *device,
+                       struct rt_spi_configuration *cfg)
+{
+    SPI_TypeDef *hspi;
+    hspi = (SPI_TypeDef *)device->bus->parent.user_data;
+
+    /* Close SPI temporarily  */
+    md_spi_disable_con1_spien(hspi);
+
+    /* config spi mode */
+    if (cfg->mode & RT_SPI_SLAVE)
+        md_spi_set_con1_mstren(hspi, MD_SPI_MODE_SLAVE);
+    else
+        md_spi_set_con1_mstren(hspi, MD_SPI_MODE_MASTER);
+
+    /* Config data mode */
+    if (cfg->mode & RT_SPI_3WIRE)
+        md_spi_set_con1_bidimode(hspi, MD_SPI_HALF_DUPLEX);
+    else
+        md_spi_set_con1_bidimode(hspi, MD_SPI_FULL_DUPLEX);
+
+    /* Config data width */
+    if (cfg->data_width == 8)
+        md_spi_set_con1_flen(hspi, MD_SPI_FRAME_FORMAT_8BIT);
+    else if (cfg->data_width == 16)
+        md_spi_set_con1_flen(hspi, SPI_CON1_FLEN_MSK);
+
+    /* Config phase */
+    if (cfg->mode & RT_SPI_CPHA)
+        md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_2EDGE);
+    else
+        md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_1EDGE);
+
+    /* Config polarity */
+    if (cfg->mode & RT_SPI_CPOL)
+        md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_HIGH);
+    else
+        md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_LOW);
+
+    /* Config if NSS pin is managed by software */
+    md_spi_disable_con1_ssen(hspi);
+
+    /* config spi clock */
+    if (cfg->max_hz >= SystemCoreClock / 2)
+    {
+        /* pclk1 max speed 48MHz, spi master max speed 10MHz */
+        if (SystemCoreClock / 2 <= 10000000)
+            md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV2);
+        else if (SystemCoreClock / 4 <= 10000000)
+            md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4);
+        else
+            md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8);
+    }
+    else if (cfg->max_hz >= SystemCoreClock / 4)
+    {
+        /* pclk1 max speed 48MHz, spi master max speed 10MHz */
+        if (SystemCoreClock / 4 <= 10000000)
+            md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4);
+        else
+            md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8);
+    }
+    else if (cfg->max_hz >= SystemCoreClock / 8)
+        md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8);
+    else if (cfg->max_hz >= SystemCoreClock / 16)
+        md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV16);
+    else if (cfg->max_hz >= SystemCoreClock / 32)
+        md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV32);
+    else if (cfg->max_hz >= SystemCoreClock / 64)
+        md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV64);
+    else if (cfg->max_hz >= SystemCoreClock / 128)
+        md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV128);
+    else
+        md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV256);
+
+    /* Enable SPI */
+    md_spi_enable_con1_spien(hspi);
+
+    return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    rt_err_t res;
+    rt_uint32_t *cs;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
+
+    cs = (rt_uint32_t *)device->parent.user_data;
+
+    /* only send data */
+    if (message->recv_buf == RT_NULL)
+    {
+        if (message->cs_take)
+        {
+            rt_pin_write(*cs, 0);
+        }
+        res = __spi_send(device, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        if (message->cs_release)
+        {
+            rt_pin_write(*cs, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+
+    /* only receive data */
+    if (message->send_buf == RT_NULL)
+    {
+        if (message->cs_take)
+        {
+            rt_pin_write(*cs, 0);
+        }
+        res = __spi_recv(device, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        if (message->cs_release)
+        {
+            rt_pin_write(*cs, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+
+    /* send & receive */
+    else
+    {
+        if (message->cs_take)
+        {
+            rt_pin_write(*cs, 0);
+        }
+        res = __spi_send_recv(device, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                            (rt_int32_t)message->length, SPITIMEOUT);
+        if (message->cs_release)
+        {
+            rt_pin_write(*cs, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+
+    return message->length;
+}
+
+const struct rt_spi_ops es32f0_spi_ops =
+{
+    spi_configure,
+    spixfer,
+};
+
+static struct rt_spi_bus _spi_bus1, _spi_bus2;
+int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
+{
+    struct rt_spi_bus *spi_bus;
+
+    if (SPIx == SPI2)
+    {
+        /* Open GPIO and SPI clock */
+        SET_BIT(RCU->APB1EN, RCU_APB1EN_SPI2EN_MSK);
+        SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK);
+
+        /* Config SPI2 GPIO */
+        md_gpio_set_mode         (GPIOB, MD_GPIO_PIN_13,   MD_GPIO_MODE_FUNCTION);
+        md_gpio_set_mode         (GPIOB, MD_GPIO_PIN_14,   MD_GPIO_MODE_FUNCTION);
+        md_gpio_set_mode         (GPIOB, MD_GPIO_PIN_15,   MD_GPIO_MODE_FUNCTION);
+        md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_13,   MD_GPIO_AF0);
+        md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_14,   MD_GPIO_AF0);
+        md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_15,   MD_GPIO_AF0);
+
+        /* Remember SPI bus2 */
+        spi_bus = &_spi_bus2;
+    }
+    else if (SPIx == SPI1)
+    {
+        /* Open GPIO and SPI clock */
+        SET_BIT(RCU->APB2EN, RCU_APB2EN_SPI1EN_MSK);
+        SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK);
+
+        /* Config SPI1 GPIO */
+        md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_3,   MD_GPIO_MODE_FUNCTION);
+        md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_4,   MD_GPIO_MODE_FUNCTION);
+        md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_5,   MD_GPIO_MODE_FUNCTION);
+        md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_3,   MD_GPIO_AF0);
+        md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_4,   MD_GPIO_AF0);
+        md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_5,   MD_GPIO_AF0);
+
+        /* Remember SPI bus1 */
+        spi_bus = &_spi_bus1;
+    }
+    else
+    {
+        return -1;
+    }
+    spi_bus->parent.user_data = SPIx;
+
+    return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops);
+}
+
+int rt_hw_spi_init(void)
+{
+    int result = 0;
+
+#ifdef BSP_USING_SPI2
+    result = es32f0_spi_register_bus(SPI2, "spi2");
+#endif
+
+#ifdef BSP_USING_SPI1
+    result = es32f0_spi_register_bus(SPI1, "spi1");
+#endif
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_spi.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_SPI_H__
+#define DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+///* cannot be used before completion init */
+//rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name);
+int rt_hw_spi_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_uart.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_uart.h"
+#include "md_gpio.h"
+#include "md_uart.h"
+
+#ifdef RT_USING_SERIAL
+
+/* es32 uart driver */
+struct es32_uart
+{
+    UART_TypeDef *huart;
+    IRQn_Type irq;
+};
+
+static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    /* Close TX/RX temporarily  */
+    md_uart_disable_lcon_txen(uart->huart);
+    md_uart_disable_lcon_rxen(uart->huart);
+
+#ifdef BSP_USING_UART1
+    /* Open UART1 clock */
+    SET_BIT(RCU->APB2EN, RCU_APB2EN_UART1EN_MSK);
+
+    /* Config UART1 GPIO pin */
+    md_gpio_set_pull        (GPIOB, MD_GPIO_PIN_7,   MD_GPIO_PULL_UP);
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_6,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOB, MD_GPIO_PIN_7,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_6,   MD_GPIO_AF2);
+    md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_7,   MD_GPIO_AF2);
+#endif /* uart2 gpio init */
+
+#ifdef BSP_USING_UART2
+    /* Open UART2 clock */
+    SET_BIT(RCU->APB1EN, RCU_APB1EN_UART2EN_MSK);
+
+    /* Config UART2 GPIO pin */
+    md_gpio_set_pull        (GPIOA, MD_GPIO_PIN_3,   MD_GPIO_PULL_UP);
+    md_gpio_set_mode        (GPIOA, MD_GPIO_PIN_2,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOA, MD_GPIO_PIN_3,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_2,   MD_GPIO_AF2);
+    md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_3,   MD_GPIO_AF2);
+#endif /* uart1 gpio init */
+
+#ifdef BSP_USING_UART3
+    /* Open UART3 clock */
+    SET_BIT(RCU->APB1EN, RCU_APB1EN_UART3EN_MSK);
+
+    /* Config UART3 GPIO pin */
+    md_gpio_set_pull        (GPIOC, MD_GPIO_PIN_7,   MD_GPIO_PULL_UP);
+    md_gpio_set_mode        (GPIOC, MD_GPIO_PIN_6,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_mode        (GPIOC, MD_GPIO_PIN_7,   MD_GPIO_MODE_FUNCTION);
+    md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_6,   MD_GPIO_AF2);
+    md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_7,   MD_GPIO_AF2);
+#endif /* uart3 gpio init */
+
+    if (cfg->bit_order == BIT_ORDER_MSB)
+    {
+        md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_MSB_FIRST);
+    }
+    else
+    {
+        md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_LSB_FIRST);
+    }
+
+    if (cfg->invert == NRZ_INVERTED)
+    {
+        md_uart_enable_lcon_datainv(uart->huart);
+    }
+    else
+    {
+        md_uart_disable_lcon_datainv(uart->huart);
+    }
+
+    /* Config buadrate */
+    md_uart_set_brr(uart->huart, SystemCoreClock/cfg->baud_rate);
+    /* Config data width */
+    md_uart_set_lcon_dls(uart->huart, 8-cfg->data_bits);
+    /* Config stop bits */
+    md_uart_set_lcon_stop(uart->huart, cfg->stop_bits);
+    /* Config parity */
+    if (cfg->parity > PARITY_NONE)
+    {
+        md_uart_set_lcon_ps(uart->huart, cfg->parity-1);
+        md_uart_enable_lcon_pe(uart->huart);
+    }
+    else
+        md_uart_disable_lcon_pe(uart->huart);
+
+    /* enable rx int */
+    md_uart_set_fcon_rxth(uart->huart, MD_UART_FCON_RXTH_1);
+    md_uart_enable_ier_rfth(uart->huart);
+    md_uart_enable_lcon_txen(uart->huart);
+    md_uart_enable_lcon_rxen(uart->huart);
+
+    return RT_EOK;
+}
+
+static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct es32_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irq);
+        /* disable interrupt */
+        md_uart_disable_idr_rfth(uart->huart);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irq);
+        /* enable interrupt */
+        md_uart_enable_ier_rfth(uart->huart);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int es32f0x_putc(struct rt_serial_device *serial, char c)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    while (uart->huart->STAT & UART_STAT_TSBUSY_MSK);
+    WRITE_REG(uart->huart->TXBUF, c);
+
+    return 1;
+}
+
+static int es32f0x_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct es32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    if (uart->huart->STAT & UART_STAT_RFTH_MSK)
+    {
+        ch = (uint8_t)(uart->huart->RXBUF & 0xFF);
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops es32f0x_uart_ops =
+{
+    es32f0x_configure,
+    es32f0x_control,
+    es32f0x_putc,
+    es32f0x_getc,
+};
+
+#ifdef BSP_USING_UART1
+/* UART1 device driver structure */
+struct es32_uart uart1 =
+{
+    UART1,
+    UART1_IRQn
+};
+
+struct rt_serial_device serial1;
+
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (md_uart_is_active_flag_rif_rfth(UART1) == 1)
+    {
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+        md_uart_clear_flag_rfth(UART1);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+/* UART2 device driver structure */
+struct es32_uart uart2 =
+{
+    UART2,
+    UART2_IRQn
+};
+
+struct rt_serial_device serial2;
+
+void UART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (md_uart_is_active_flag_rif_rfth(UART2) == 1)
+    {
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
+        md_uart_clear_flag_rfth(UART2);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+/* UART3 device driver structure */
+struct es32_uart uart3 =
+{
+    UART3,
+    UART3_IRQn
+};
+
+struct rt_serial_device serial3;
+
+void UART3_AES_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (md_uart_is_active_flag_rif_rfth(UART3) == 1)
+    {
+        rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
+        md_uart_clear_flag_rfth(UART3);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+int rt_hw_uart_init(void)
+{
+    struct es32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART1
+    uart = &uart1;
+    serial1.ops = &es32f0x_uart_ops;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+    uart = &uart2;
+    serial2.ops = &es32f0x_uart_ops;
+    serial2.config = config;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+    uart = &uart3;
+    serial3.ops = &es32f0x_uart_ops;
+    serial3.config = config;
+
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3, "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART3 */
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif

bsp/essemi/es32f0271/drivers/drv_uart.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-10-23     yuzrain       the first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/essemi/es32f0271/drivers/linker_scripts/link.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x10000 {    ; load region size_region
+  ER_IROM1 0x00000000 0x10000 {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x2000{  ; RW data
+   .ANY (+RW +ZI)
+  }
+}

bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h

+/**
+  **************************************************************************************
+  * @file    REG_HDIV.h
+  * @brief   HDIV Head File
+  *
+  * @version V0.01
+  * @data    12/3/2018
+  * @author  Eastsoft MCU Software Team
+  * @note
+  *
+  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
+  *
+  **************************************************************************************
+  */
+
+#ifndef __hdiv_H__
+#define __hdiv_H__
+
+
+/******************************************************************************/
+/*                              设备特殊寄存器结构定义                        */
+/******************************************************************************/
+
+/*   允许匿名结构和匿名联合    */
+/* #pragma anon_unions */
+
+/****************** Bit definition for HDIV_DIVDR register ************************/
+
+#define  HDIV_DIVDR_DIVS_POSS  0U 
+#define  HDIV_DIVDR_DIVS_POSE  31U 
+#define  HDIV_DIVDR_DIVD_MSK  BITS(HDIV_DIVDR_DIVD_POSS,HDIV_DIVDR_DIVD_POSE)
+
+/****************** Bit definition for HDIV_DIVSR register ************************/
+
+#define  HDIV_DIVSR_DIVS_POSS  0U 
+#define  HDIV_DIVSR_DIVS_POSE  31U 
+#define  HDIV_DIVSR_DIVS_MSK  BITS(HDIV_DIVSR_DIVS_POSS,HDIV_DIVSR_DIVS_POSE)
+
+/****************** Bit definition for HDIV_DIVQR register ************************/
+
+#define  HDIV_DIVQR_DIVQ_POSS  0U 
+#define  HDIV_DIVQR_DIVQ_POSE  31U 
+#define  HDIV_DIVQR_DIVQ_MSK  BITS(HDIV_DIVQR_DIVQ_POSS,HDIV_DIVQR_DIVQ_POSE)
+
+/****************** Bit definition for HDIV_DIVRR register ************************/
+
+#define  HDIV_DIVRR_DIVR_POSS  0U 
+#define  HDIV_DIVRR_DIVR_POSE  31U 
+#define  HDIV_DIVRR_DIVR_MSK  BITS(HDIV_DIVRR_DIVR_POSS,HDIV_DIVRR_DIVR_POSE)
+
+/****************** Bit definition for HDIV_DIVSTAT register ************************/
+
+#define  HDIV_DIVSTAT_SIGN_POS  2U 
+#define  HDIV_DIVSTAT_SIGN_MSK  BIT(HDIV_DIVSTAT_SIGN_POS)
+
+#define  HDIV_DIVSTAT_DIV0_POS  1U 
+#define  HDIV_DIVSTAT_DIV0_MSK  BIT(HDIV_DIVSTAT_DIV0_POS)
+
+#define  HDIV_DIVSTAT_BUSY_POS  0U 
+#define  HDIV_DIVSTAT_BUSY_MSK  BIT(HDIV_DIVSTAT_BUSY_POS)
+
+typedef struct
+{
+  __IO uint32_t DIVDR;
+  __IO uint32_t DIVSR;
+  __I uint32_t DIVQR;
+  __I uint32_t DIVRR;
+  __I uint32_t DIVSTAT;
+} HDIV_TypeDef;
+
+
+
+
+
+#endif