MT7621 disable switch EEE (#3963)

* revert: ramips: gsw_mt7621: disable PORT 5 MAC RX/TX flow control

revert: ramips: gsw_mt7621: disable PORT 5 MAC RX/TX flow control by default
This revert c8f8e59
The TX/RX flow control is not the cause of the TX timeouts issue
Signed-off-by: NChen Minqiang <ptpt52@gmail.com>

* ramips: net/mediatek fix logical error

ramips: net/mediatek fix logical error

fe_empty_txd() should return `tx_ring_size - 1` on ring empty, and
return 0 on ring full.

* ramips: net/mediatek disable eee

ramips: net/mediatek disable eee

This disable eee for mt7530 ports, it causes the link down/up
issue, which happens when connecting to 100Mbit switch

Fixes: FS#1449
Signed-off-by: NChen Minqiang <ptpt52@gmail.com>

target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c

@@ -98,9 +98,15 @@ static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
 	mt7530_mdio_w32(gsw, 0x7000, 0x3);
 	usleep_range(10, 20);
 
-	/* (GE1, Force 1000M/FD, FC OFF, MAX_RX_LENGTH 1536) */
-	mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
-	mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
+	if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
+		/* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
+		mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
+		mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
+	} else {
+		/* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
+		mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
+		mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
+	}
 
 	/* (GE2, Link down) */
 	mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
@@ -180,6 +186,22 @@ static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
 	mt7530_mdio_w32(gsw, 0x7a74, 0x44);
 	mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
 
+	/* Disable EEE */
+	for (i = 0; i <= 4; i++) {
+		_mt7620_mii_write(gsw, i, 13, 0x7);
+		_mt7620_mii_write(gsw, i, 14, 0x3C);
+		_mt7620_mii_write(gsw, i, 13, 0x4007);
+		_mt7620_mii_write(gsw, i, 14, 0x0);
+	}
+
+	/* Disable EEE 10Base-Te */
+	for (i = 0; i <= 4; i++) {
+		_mt7620_mii_write(gsw, i, 13, 0x1f);
+		_mt7620_mii_write(gsw, i, 14, 0x027b);
+		_mt7620_mii_write(gsw, i, 13, 0x401f);
+		_mt7620_mii_write(gsw, i, 14, 0x1177);
+	}
+
 	/* turn on all PHYs */
 	for (i = 0; i <= 4; i++) {
 		val = _mt7620_mii_read(gsw, i, 0);

target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c

@@ -565,7 +565,7 @@ static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
 	barrier();
 	return (u32)(ring->tx_ring_size -
 			((ring->tx_next_idx - ring->tx_free_idx) &
-			 (ring->tx_ring_size - 1)));
+			 (ring->tx_ring_size - 1)) - 1);
 }
 
 struct fe_map_state {