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提交 c7c02dfa 编写于 作者: C coolsnowwolf
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rockchip: add support for NanoPi R2S arm64 router board

上级 9c8da887
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Showing with 7302 addition and 21 deletion
package/boot/arm-trusted-firmware-rockchip/Makefile
浏览文件 @ c7c02dfa
......@@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-rockchip
PKG_VERSION:=2.3-rc0
PKG_VERSION:=2.3
PKG_RELEASE:=1
PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz?
PKG_HASH:=8d0a2bd18adf54f9cf6fe923d10f21c1d21f42a15067757333ff8989b25f100a
PKG_HASH:=bf352298743aed594cf2958dd588e06ab6713fc514bb6f809bf55a85a87134c1
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=license.md
......@@ -40,7 +40,7 @@ endef
define Build/InstallDev
$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/rk3399_bl31.elf $(STAGING_DIR_IMAGE)/bl31.elf
$(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/
endef
define Package/arm-trusted-firmware-rockchip/install
......
package/boot/uboot-rockchip/Makefile
浏览文件 @ c7c02dfa
......@@ -13,6 +13,7 @@ PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
define U-Boot/Default
BUILD_TARGET:=rockchip
......@@ -20,27 +21,43 @@ define U-Boot/Default
HIDDEN:=1
endef
define U-Boot/nanopi-r2s-rk3328
BUILD_SUBTARGET:=armv8
NAME:=NanoPi R2S
BUILD_DEVICES:= \
friendlyarm_nanopi-r2s
BL31=$(STAGING_DIR_IMAGE)/rk3328_bl31.elf
endef
define U-Boot/rock-pi-e-rk3328
BUILD_SUBTARGET:=armv8
NAME:=Rock Pi E
BUILD_DEVICES:= \
radxa_rock-pi-e
BL31=$(STAGING_DIR_IMAGE)/rk3328_bl31.elf
endef
define U-Boot/rockpro64-rk3399
BUILD_SUBTARGET:=armv8
NAME:=RockPro64
BUILD_DEVICES:= \
pine64_rockpro64
DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
BL31=$(STAGING_DIR_IMAGE)/rk3399_bl31.elf
endef
UBOOT_TARGETS := \
nanopi-r2s-rk3328 \
rock-pi-e-rk3328 \
rockpro64-rk3399
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_MAKE_FLAGS += \
BL31=$(STAGING_DIR_IMAGE)/bl31.elf
BL31=$(BL31)
define Build/Configure
$(SED) s/subdir.*pylibfdt//g $(PKG_BUILD_DIR)/scripts/dtc/Makefile
echo CONFIG_CMD_SETEXPR=y >> $(PKG_BUILD_DIR)/configs/$(UBOOT_CONFIG)_defconfig
$(call Build/Configure/U-Boot)
$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
endef
......
package/boot/uboot-rockchip/patches/001-rockchip-Avoid-using-libfdt-with-of-platdata.diff 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index a89e2ecc4a..e86c17e6d6 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -672,6 +672,10 @@ static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
+ /* FIXME: Device tree should be read in ofdata_to_platdata() */
+ if (CONFIG_IS_ENABLED(OF_PLATDATA))
+ return -EDEADLK;
+
/*
* Otherwise, we need to check the clock-output-names of the
* requested parent to see if the requested id is "gmac_clkin".
@@ -709,6 +713,10 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
+ /* FIXME: Device tree should be read in ofdata_to_platdata() */
+ if (CONFIG_IS_ENABLED(OF_PLATDATA))
+ return -EDEADLK;
+
/*
* Otherwise, we need to check the clock-output-names of the
* requested parent to see if the requested id is "gmac_clkin".
@@ -765,9 +773,11 @@ static int rk3328_clk_probe(struct udevice *dev)
static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
{
- struct rk3328_clk_priv *priv = dev_get_priv(dev);
+ if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ struct rk3328_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index 80dc431d20..dccc54e95f 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -383,8 +383,8 @@ static int rockchip_pinconf_prop_name_to_param(const char *property,
return -EPERM;
}
-static int rockchip_pinctrl_set_state(struct udevice *dev,
- struct udevice *config)
+static int __maybe_unused rockchip_pinctrl_set_state(struct udevice *dev,
+ struct udevice *config)
{
struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
@@ -474,7 +474,9 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
}
const struct pinctrl_ops rockchip_pinctrl_ops = {
+#if !CONFIG_IS_ENABLED(PLATDATA)
.set_state = rockchip_pinctrl_set_state,
+#endif
.get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
};
package/boot/uboot-rockchip/patches/002-dm-core-Don-t-include-ofnode-functions-with-of-platdata.diff 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index bce7467da1..b9e4a2aab1 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
ifndef CONFIG_DM_DEV_READ_INLINE
obj-$(CONFIG_OF_CONTROL) += read.o
endif
-obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+ifdef CONFIG_$(SPL_TPL_)OF_LIBFDT
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+endif
ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG
diff --git a/include/dm/read.h b/include/dm/read.h
index d37fcb504d..4f02d07d00 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -43,8 +43,7 @@ static inline bool dev_of_valid(struct udevice *dev)
return ofnode_valid(dev_ofnode(dev));
}
-#ifndef CONFIG_DM_DEV_READ_INLINE
-
+#if !defined(CONFIG_DM_DEV_READ_INLINE) || CONFIG_IS_ENABLED(OF_PLATDATA)
/**
* dev_read_u32() - read a 32-bit integer from a device's DT property
*
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 3bd98b01ad..e3bfcdb6cc 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -467,7 +467,7 @@ static int eth_pre_unbind(struct udevice *dev)
static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN])
{
-#if IS_ENABLED(CONFIG_OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
const uint8_t *p;
p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN);
package/boot/uboot-rockchip/patches/003-spl-Allow-SPL-TPL-to-use-of-platdata-without-libfdt.diff 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/lib/Kconfig b/lib/Kconfig
index b8a8509d72..1cae2d5cc8 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -496,7 +496,7 @@ config OF_LIBFDT_OVERLAY
config SPL_OF_LIBFDT
bool "Enable the FDT library for SPL"
- default y if SPL_OF_CONTROL
+ default y if SPL_OF_CONTROL && !SPL_OF_PLATDATA
help
This enables the FDT library (libfdt). It provides functions for
accessing binary device tree images in memory, such as adding and
@@ -517,7 +517,7 @@ config SPL_OF_LIBFDT_ASSUME_MASK
config TPL_OF_LIBFDT
bool "Enable the FDT library for TPL"
- default y if TPL_OF_CONTROL
+ default y if TPL_OF_CONTROL && !TPL_OF_PLATDATA
help
This enables the FDT library (libfdt). It provides functions for
accessing binary device tree images in memory, such as adding and
package/boot/uboot-rockchip/patches/005-add-rock-pi-e-support-dts.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c6af87cf5e..61afe94a05 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
- rk3328-rock64.dtb
+ rk3328-rock64.dtb \
+ rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-lion.dtb \
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
new file mode 100644
index 0000000000..bf5b1f3adc
--- /dev/null
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Radxa
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc5v0_host_xhci>;
+ status = "okay";
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts
new file mode 100644
index 0000000000..4b9f9a8248
--- /dev/null
+++ b/arch/arm/dts/rk3328-rock-pi-e.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Radxa
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Radxa Rock Pi E";
+ compatible = "radxa,rock-pi-e", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc5v0_host_xhci";
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_io>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,force_thresh_dma_mode;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ status = "okay";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ max-frequency = <150000000>;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
package/boot/uboot-rockchip/patches/005-add-support-nanopi-r2s.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0127a91a..c5beaa85 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -104,7 +104,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-nanopi-r2s.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
diff --git a/arch/arm/dts/rk3328-nanopi-r2-common.dtsi b/arch/arm/dts/rk3328-nanopi-r2-common.dtsi
new file mode 100644
index 00000000..bc924346
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2-common.dtsi
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+/*#include "rk3328-dram-default-timing.dtsi"*/
+#include "rk3328.dtsi"
+
+/ {
+ model = "FriendlyARM boards based on Rockchip RK3328";
+ compatible = "friendlyarm,nanopi-r2", "rockchip,rk3328";
+
+ aliases {
+/* ethernet1 = &r8153;*/
+ };
+
+ chosen {
+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "disabled";
+
+ status {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:red:status";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk805 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+
+/* sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };*/
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ startup-delay-us = <2000>;
+ regulator-settling-time-us = <5000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ dfi: dfi@ff790000 {
+ reg = <0x00 0xff790000 0x00 0x400>;
+ compatible = "rockchip,rk3328-dfi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+/* dmc: dmc {
+ compatible = "rockchip,rk3328-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ auto-min-freq = <786000>;
+ auto-freq-en = <0>;
+ #cooling-cells = <2>;
+ status = "disabled";
+
+ ddr_power_model: ddr_power_model {
+ compatible = "ddr_power_model";
+ dynamic-power-coefficient = <120>;
+ static-power-coefficient = <200>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "ddr_leakage";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000>;
+ opp-microvolt-L0 = <1100000>;
+ opp-microvolt-L1 = <1075000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000>;
+ opp-microvolt-L0 = <1175000>;
+ opp-microvolt-L1 = <1150000>;
+ };
+ };
+*/};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+/*&dmc {
+ center-supply = <&vdd_logic>;
+ status = "okay";
+};*/
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "disabled";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ phy-handle = <&rtl8211e>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_phy>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,aal;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@0 {
+ reg = <0>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_18>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA5 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA6 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA7 3 &pcfg_pull_up_2ma>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_4ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_4ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_4ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+/*&sdmmc_ext {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ rockchip,default-sample-phase = <120>;
+ supports-sdio;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};*/
+
+/*&tsadc {
+ status = "okay";
+};*/
+
+&uart2 {
+ status = "okay";
+};
+
+/*&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ r8153: device@2 {
+ compatible = "usbbda:8153";
+ reg = <2>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};*/
diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts
new file mode 100644
index 00000000..c3313bdc
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3328-nanopi-r2-common.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R2S";
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key1>;
+
+ reset {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc_rtl8153: vcc-rtl8153-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_en_drv>;
+ regulator-always-on;
+ regulator-name = "vcc_rtl8153";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ off-on-delay-us = <5000>;
+ enable-active-high;
+ };
+};
+
+&emmc {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+
+ lan {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:lan";
+ };
+
+ wan {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:wan";
+ };
+};
+
+&leds_gpio {
+ rockchip,pins =
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+/*&pwm2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&pwm2_sleep_pin>;
+ status = "okay";
+};*/
+
+&rk805 {
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&vccio_sd {
+ status = "okay";
+};
+
+&io_domains {
+ vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+ vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+/*&sdmmc_ext {
+ status = "disabled";
+};*/
+
+&sdio_pwrseq {
+ status = "disabled";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pwm {
+ pwm2_sleep_pin: pwm2-sleep-pin {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ rockchip-key {
+ gpio_key1: gpio-key1 {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb30_en_drv: usb30-en-drv {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 060c84e6..eac257b0 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -1386,7 +1386,7 @@
};
};
- gmac2phy {
+ gmac2phy: gmac2phy {
fephyled_speed100: fephyled-speed100 {
rockchip,pins =
<0 31 RK_FUNC_1 &pcfg_pull_none>;
package/boot/uboot-rockchip/patches/006-add-rock-pi-e-defconfig.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
new file mode 100644
index 0000000000..759838775f
--- /dev/null
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x4000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SMBIOS_PRODUCT_NAME="rock-pi-e_rk3328"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="radxa"
package/boot/uboot-rockchip/patches/006-add-support-nanopi-r2s-defconfig.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
new file mode 100644
index 00000000..cf3452ea
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+};
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
new file mode 100644
index 00000000..720b5e04
--- /dev/null
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SMBIOS_PRODUCT_NAME="nanopi-r2s_rk3328"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="friendlyarm"
package/boot/uboot-rockchip/patches/007-sdmmc-fifo-mode-in-spl.patch 0 → 100644
浏览文件 @ c7c02dfa
From b0693aeb9ceab57ffc9d9f4ceca610bd82d5ca07 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= <ayufan@ayufan.eu>
Date: Mon, 21 May 2018 02:00:19 +0200
Subject: [PATCH] ayufan: rock64: for SPL build always use fifo-mode
Change-Id: I9ac012ce4aaf03a151f7c5c818829d631efdd7ed
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index fc0f0fad76..d1f26e41fe 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -70,7 +70,11 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
if (priv->fifo_depth < 0)
return -EINVAL;
+#ifdef CONFIG_SPL_BUILD
+ priv->fifo_mode = true; // always force fifo mode
+#else
priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
+#endif
/*
* 'clock-freq-min-max' is deprecated
package/boot/uboot-rockchip/patches/008-set-sdmmc-priority.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 68e1105a..906c22ed 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -14,8 +14,8 @@
/* First try to boot from SD (index 0), then eMMC (index 1) */
#if CONFIG_IS_ENABLED(CMD_MMC)
#define BOOT_TARGET_MMC(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1)
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0)
#else
#define BOOT_TARGET_MMC(func)
#endif
package/boot/uboot-rockchip/patches/009-add-set-eth1-addr.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 6dbb9bde..89f3a918 100644
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -50,6 +50,11 @@ int rockchip_setup_macaddr(void)
mac_addr[0] &= 0xfe; /* clear multicast bit */
mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ /* Make a valid MAC address for eth1 too */
+ mac_addr[5] += 0x20;
+ mac_addr[5] &= 0xff;
+ eth_env_set_enetaddr("eth1addr", mac_addr);
#endif
return 0;
}
target/linux/rockchip/armv8/base-files/etc/board.d/01_leds 0 → 100755
浏览文件 @ c7c02dfa
#!/bin/sh
#
# Copyright © 2017 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
friendlyarm,nanopi-r2s)
ucidef_set_led_netdev "wan" "WAN" "nanopi:green:wan" "eth0"
ucidef_set_led_netdev "lan" "LAN" "nanopi:green:lan" "eth1"
;;
esac
board_config_flush
exit 0
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
浏览文件 @ c7c02dfa
......@@ -5,6 +5,12 @@
board_config_update
case "$(board_name)" in
friendlyarm,nanopi-r2s)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
radxa,rock-pi-e)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
*)
ucidef_set_interface_lan 'eth0'
;;
......
target/linux/rockchip/armv8/base-files/etc/inittab 0 → 100644
浏览文件 @ c7c02dfa
::sysinit:/etc/init.d/rcS S boot
::shutdown:/etc/init.d/rcS K shutdown
::askconsole:/usr/libexec/login.sh
tts/0::askfirst:/usr/libexec/login.sh
ttyS0::askfirst:/usr/libexec/login.sh
tty1::askfirst:/usr/libexec/login.sh
target/linux/rockchip/armv8/config-5.4
浏览文件 @ c7c02dfa
......@@ -9,6 +9,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_ARC_EMAC_CORE=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CRYPTO=y
# CONFIG_ARM64_ERRATUM_1165522 is not set
# CONFIG_ARM64_ERRATUM_1286807 is not set
# CONFIG_ARM64_ERRATUM_1418040 is not set
......@@ -38,7 +39,9 @@ CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ARM_MHU=y
CONFIG_ARM_PMU=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
# CONFIG_ARM_SCMI_PROTOCOL is not set
CONFIG_ARM_SCPI_CPUFREQ=y
......@@ -50,6 +53,7 @@ CONFIG_ARM_SMMU_V3=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BLK_CGROUP is not set
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
# CONFIG_BLK_DEV_INITRD is not set
......@@ -66,6 +70,15 @@ CONFIG_BRCMSTB_GISB_ARB=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
# CONFIG_CFS_BANDWIDTH is not set
CONFIG_CGROUPS=y
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_PIDS is not set
CONFIG_CGROUP_SCHED=y
CONFIG_CHARGER_GPIO=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CMA=y
......@@ -73,7 +86,7 @@ CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SIZE_MBYTES=5
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
......@@ -90,6 +103,7 @@ CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTIG_ALLOC=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_CPUSETS is not set
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
......@@ -115,15 +129,79 @@ CONFIG_CRC16=y
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC_T10DIF=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_ROCKCHIP=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_NHPOLY1305=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DEVFREQ_THERMAL=y
CONFIG_DEVMEM=y
# CONFIG_DEVPORT is not set
CONFIG_DEVTMPFS=y
......@@ -134,6 +212,11 @@ CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DNOTIFY=y
# CONFIG_DP83640_PHY is not set
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_ROCKCHIP is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DWMAC_DWC_QOS_ETH=y
......@@ -145,7 +228,10 @@ CONFIG_ENERGY_MODEL=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXTCON=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FANOTIFY=y
CONFIG_FB=y
CONFIG_FB_CMDLINE=y
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
# CONFIG_FLATMEM_MANUAL is not set
......@@ -163,13 +249,26 @@ CONFIG_GPIOLIB=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HARDENED_USERCOPY is not set
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_SCHED_AVG_IRQ=y
CONFIG_HAVE_UID16=y
CONFIG_HDMI=y
CONFIG_HID=y
CONFIG_HID_GENERIC=y
CONFIG_HOTPLUG_CPU=y
......@@ -188,9 +287,18 @@ CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_RK3X=y
CONFIG_I2C_SLAVE=y
# CONFIG_I2C_SLAVE_EEPROM is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_INDIRECT_PIO=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
......@@ -198,7 +306,7 @@ CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_MATRIXKMAP=y
# CONFIG_INPUT_MISC is not set
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
......@@ -212,6 +320,8 @@ CONFIG_IOMMU_SUPPORT=y
# CONFIG_IONIC is not set
# CONFIG_IO_STRICT_DEVMEM is not set
CONFIG_IO_URING=y
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_JBD2=y
......@@ -223,11 +333,19 @@ CONFIG_KEXEC_FILE=y
# CONFIG_KEXEC_SIG is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_KSM=y
CONFIG_KVM=y
CONFIG_KVM_ARM_HOST=y
CONFIG_KVM_ARM_PMU=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_KVM_INDIRECT_VECTORS=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_VFIO=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_PANIC=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
......@@ -236,6 +354,10 @@ CONFIG_LEGACY_PTY_COUNT=16
CONFIG_LIBCRC32C=y
CONFIG_LOCALVERSION_AUTO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAILBOX=y
......@@ -248,6 +370,8 @@ CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_GPIO=y
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEMCG is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
CONFIG_MFD_RK808=y
......@@ -270,6 +394,8 @@ CONFIG_MMC_SDHCI_OF_DWCMSHC=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MMU_NOTIFIER=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MQ_IOSCHED_DEADLINE=y
# CONFIG_MTD_CFI is not set
CONFIG_MTD_CMDLINE_PARTS=y
......@@ -277,6 +403,9 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
# CONFIG_NET_CLS_CGROUP is not set
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ_COMMON=y
......@@ -318,41 +447,49 @@ CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_STUB=y
CONFIG_PERF_EVENTS=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PHY_ROCKCHIP_DP=y
# CONFIG_PHY_ROCKCHIP_DP is not set
CONFIG_PHY_ROCKCHIP_EMMC=y
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_RK805 is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PL330_DMA=y
CONFIG_PLATFORM_MHU=y
CONFIG_PLUGIN_HOSTCC=""
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POWER_AVS=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PPS=y
CONFIG_PPS_CLIENT_GPIO=y
CONFIG_PPS_CLIENT_KTIMER=y
CONFIG_PREEMPT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PREEMPT_RCU=y
CONFIG_PRINTK_TIME=y
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_STRIPPED is not set
CONFIG_PROC_VMCORE=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SYSFS=y
......@@ -370,6 +507,7 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_EXPERT is not set
CONFIG_RCU_TRACE=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_IRQ=y
......@@ -377,6 +515,7 @@ CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
CONFIG_RELOCATABLE=y
......@@ -388,15 +527,18 @@ CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_ROCKCHIP_THERMAL is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_RSEQ=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_NVMEM=y
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
CONFIG_SCSI=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
......@@ -423,6 +565,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIO=y
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_SLUB_DEBUG=y
......@@ -443,6 +586,7 @@ CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SRAM=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_STACKPROTECTOR_STRONG=y
# CONFIG_STAGING is not set
CONFIG_STMMAC_ETH=y
......@@ -483,6 +627,8 @@ CONFIG_TYPEC_TCPM=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC2_HOST=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_HOST=y
CONFIG_USB_DWC3_OF_SIMPLE=y
......@@ -504,6 +650,7 @@ CONFIG_USB_XHCI_PLATFORM=y
# CONFIG_USERIO is not set
# CONFIG_VFIO is not set
# CONFIG_VIRTIO_MENU is not set
CONFIG_VIRTUALIZATION=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
......@@ -516,3 +663,5 @@ CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
target/linux/rockchip/image/Makefile
浏览文件 @ c7c02dfa
......@@ -24,10 +24,10 @@ endef
define Build/boot-script
# Make an U-boot image and copy it to the boot partition
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d mmc.bootscript $@.boot/boot.scr
mkimage -A arm -O linux -T script -C lzma -a 0 -e 0 -d mmc.bootscript $@.boot/boot.scr
endef
define Build/pine64-img
define Build/sdcard-img
# Creates the final SD/eMMC images,
# combining boot partition, root partition as well as the u-boot bootloader
......@@ -50,7 +50,7 @@ endef
### Devices ###
define Device/Default
PROFILES := Default
KERNEL := kernel-bin
KERNEL := kernel-bin | lzma
IMAGES := sysupgrade.img.gz
SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
......
target/linux/rockchip/image/armv8.mk
浏览文件 @ c7c02dfa
......@@ -4,11 +4,31 @@
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
define Device/friendlyarm_nanopi-r2s
DEVICE_VENDOR := FriendlyARM
DEVICE_MODEL := NanoPi R2S
SOC := rk3328
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
IMAGE/sysupgrade.img.gz := boot-common | boot-script | sdcard-img | gzip | append-metadata
DEVICE_PACKAGES += kmod-phy-realtek kmod-usb-net kmod-usb-net-rtl8152 kmod-macvlan
endef
TARGET_DEVICES += friendlyarm_nanopi-r2s
define Device/radxa_rock-pi-e
DEVICE_VENDOR := Radxa
DEVICE_MODEL := Rock Pi E
SOC := rk3328
UBOOT_DEVICE_NAME := rock-pi-e-rk3328
IMAGE/sysupgrade.img.gz := boot-common | boot-script | sdcard-img | gzip | append-metadata
DEVICE_PACKAGES += kmod-phy-realtek
endef
TARGET_DEVICES += radxa_rock-pi-e
define Device/pine64_rockpro64
DEVICE_VENDOR := Pine64
DEVICE_MODEL := RockPro64
SOC := rk3399
UBOOT_DEVICE_NAME := rockpro64-rk3399
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
IMAGE/sysupgrade.img.gz := boot-common | boot-script | sdcard-img | gzip | append-metadata
endef
TARGET_DEVICES += pine64_rockpro64
target/linux/rockchip/image/mmc.bootscript
浏览文件 @ c7c02dfa
part uuid mmc ${devnum}:2 uuid
setenv bootargs "console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait"
if test $stdout = 'serial@ff1a0000' ;
then serial_addr=',0xff1a0000';
elif test $stdout = 'serial@ff130000' ;
then serial_addr=',0xff130000';
fi;
setenv bootargs "console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32${serial_addr} swiotlb=1 root=PARTUUID=${uuid} rw rootwait loglevel=9";
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
booti ${kernel_addr_r} - ${fdt_addr_r}
echo "Uncompress lzma kernel into memmory.."
setexpr kernel_addr_dec ${filesize} + ${kernel_addr_r} || kernel_addr_dec=0x03000000
lzmadec ${kernel_addr_r} ${kernel_addr_dec}
booti ${kernel_addr_dec} - ${fdt_addr_r}
target/linux/rockchip/patches-5.4/001-rk3328_fix_wrong_mmc_shift.patch 0 → 100644
浏览文件 @ c7c02dfa
From 6376a1b0e30a1d30c4269083fb5b9a146a944ada Mon Sep 17 00:00:00 2001
From: Ziyuan Xu <xzy.xu@rock-chips.com>
Date: Wed, 28 Nov 2018 17:39:50 +0800
Subject: [PATCH] Revert "clk: rockchip: fix wrong mmc phase shift for rk3328"
This reverts commit 4ef244988993afc8a6447e990a4ccb4a223d3f20.
The description for CRU_EMMC/SDMMC/SDIO_CON[0/1] is jumble on
chapters, make it clear that the correct shift is 1 that from
IC engineer.
Change-Id: I48dce293ec6ef82a5c78db38efc083227776ea99
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3328.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index ac6e6163a232..d77925271198 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
RK3328_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
- RK3328_SDMMC_CON1, 0),
+ RK3328_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
RK3328_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
- RK3328_SDIO_CON1, 0),
+ RK3328_SDIO_CON1, 1),
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
RK3328_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
- RK3328_EMMC_CON1, 0),
+ RK3328_EMMC_CON1, 1),
MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
RK3328_SDMMC_EXT_CON0, 1),
MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
- RK3328_SDMMC_EXT_CON1, 0),
+ RK3328_SDMMC_EXT_CON1, 1),
};
static const char *const rk3328_critical_clocks[] __initconst = {
target/linux/rockchip/patches-5.4/003-add-nanopi-r2s-support.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 92d796a33..24a6c304f 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi
new file mode 100644
index 000000000..36890bb7f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328-dram-default-timing.dtsi"
+#include "rk3328.dtsi"
+
+/ {
+ model = "FriendlyARM boards based on Rockchip RK3328";
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+
+ aliases {
+ ethernet1 = &r8153;
+ };
+
+ chosen {
+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "disabled";
+
+ status {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:red:status";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk805 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ startup-delay-us = <2000>;
+ regulator-settling-time-us = <5000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ dfi: dfi@ff790000 {
+ reg = <0x00 0xff790000 0x00 0x400>;
+ compatible = "rockchip,rk3328-dfi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3328-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ auto-min-freq = <786000>;
+ auto-freq-en = <0>;
+ #cooling-cells = <2>;
+ status = "disabled";
+
+ ddr_power_model: ddr_power_model {
+ compatible = "ddr_power_model";
+ dynamic-power-coefficient = <120>;
+ static-power-coefficient = <200>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "ddr_leakage";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000>;
+ opp-microvolt-L0 = <1100000>;
+ opp-microvolt-L1 = <1075000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000>;
+ opp-microvolt-L0 = <1175000>;
+ opp-microvolt-L1 = <1150000>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "disabled";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ phy-handle = <&rtl8211e>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_phy>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,aal;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@0 {
+ reg = <0>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_18>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
+ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA5 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA6 3 &pcfg_pull_up_2ma>,
+ <3 RK_PA7 3 &pcfg_pull_up_2ma>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_4ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_4ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_4ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_4ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&sdmmc_ext {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ rockchip,default-sample-phase = <120>;
+ supports-sdio;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ r8153: device@2 {
+ compatible = "usbbda:8153";
+ reg = <2>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
new file mode 100644
index 000000000..971397659
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3328-nanopi-r2-common.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R2S";
+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key1>;
+
+ reset {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc_rtl8153: vcc-rtl8153-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_en_drv>;
+ regulator-always-on;
+ regulator-name = "vcc_rtl8153";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ off-on-delay-us = <5000>;
+ enable-active-high;
+ };
+};
+
+&emmc {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+
+ lan {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:lan";
+ };
+
+ wan {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi:green:wan";
+ };
+};
+
+&leds_gpio {
+ rockchip,pins =
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&pwm2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&pwm2_sleep_pin>;
+ status = "okay";
+};
+
+&rk805 {
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&vccio_sd {
+ status = "okay";
+};
+
+&io_domains {
+ vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+ vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc_ext {
+ status = "disabled";
+};
+
+&sdio_pwrseq {
+ status = "disabled";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pwm {
+ pwm2_sleep_pin: pwm2-sleep-pin {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ rockchip-key {
+ gpio_key1: gpio-key1 {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb30_en_drv: usb30-en-drv {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
target/linux/rockchip/patches-5.4/004-rk3328_add_idle_state.patch 0 → 100644
浏览文件 @ c7c02dfa
From 4f279f9fbca54464173240f7e73b145a136dfa1e Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Sun, 29 Dec 2019 20:16:17 +0000
Subject: [PATCH] arm64: dts: rockchip: Add RK3328 idle state
Downstream RK3328 DTBs describe a CPU idle state matching that present
on other SoCs like RK3399. This works with upstream Trusted Firmware-A
too, so let's add it here.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/a8c83e705d387446ea8121516d410e38b2d9c57b.1577640736.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 91306ebed4da..c9ff1188bd7b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -41,6 +41,7 @@
reg = <0x0 0x0>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@@ -53,6 +54,7 @@
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@@ -65,6 +67,7 @@
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@@ -77,12 +80,26 @@
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+ };
+
l2: l2-cache0 {
compatible = "cache";
};
target/linux/rockchip/patches-5.4/004-unlock-1512mhz-rk3328.patch 0 → 100644
浏览文件 @ c7c02dfa
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 8dabc6e29..d58c893a6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -125,6 +125,11 @@
opp-microvolt = <1300000>;
clock-latency-ns = <40000>;
};
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1450000>;
+ clock-latency-ns = <40000>;
+ };
};
amba {
target/linux/rockchip/patches-5.4/005-add_hwmon_support.patch 0 → 100644
浏览文件 @ c7c02dfa
From f895f1f4de0b7252f29e7e5779727b303df9e58d Mon Sep 17 00:00:00 2001
From: schaecsn <schaecsn@gmx.net>
Date: Sun, 17 Nov 2019 21:24:13 -0800
Subject: [PATCH] thermal: rockchip: enable hwmon
Enable hwmon for the soc and gpu temperature sensors.
Signed-off-by: Stefan Schaeckeler <schaecsn@gmx.net>
---
drivers/thermal/rockchip_thermal.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index 343c2f5c5a25..e47c60010259 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -19,6 +19,8 @@
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/consumer.h>
+#include "thermal_hwmon.h"
+
/**
* If the temperature over a period of time High,
* the resulting TSHUT gave CRU module,let it reset the entire chip,
@@ -1321,8 +1323,15 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
thermal->chip->control(thermal->regs, true);
- for (i = 0; i < thermal->chip->chn_num; i++)
+ for (i = 0; i < thermal->chip->chn_num; i++) {
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
+ thermal->sensors[i].tzd->tzp->no_hwmon = false;
+ error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
+ if (error)
+ dev_warn(&pdev->dev,
+ "failed to register sensor %d with hwmon: %d\n",
+ i, error);
+ }
platform_set_drvdata(pdev, thermal);
@@ -1344,6 +1353,7 @@ static int rockchip_thermal_remove(struct platform_device *pdev)
for (i = 0; i < thermal->chip->chn_num; i++) {
struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
+ thermal_remove_hwmon_sysfs(sensor->tzd);
rockchip_thermal_toggle_sensor(sensor, false);
}
From b5bcb54fe763aa9f40bae7af7e0629a3a6b93a52 Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Thu, 28 Nov 2019 20:59:27 +0000
Subject: [PATCH] arm64: dts: rockchip: Add GPU cooling device for RK3399
As for RK3288, now that we have a binding for the GPU we can
hook up the missing cooling device for the thermal zone.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e62ea0e2b657..aa0838adb224 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -827,6 +827,14 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
@@ -1886,6 +1894,7 @@
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "gpu", "job", "mmu";
clocks = <&cru ACLK_GPU>;
+ #cooling-cells = <2>;
power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
target/linux/rockchip/patches-5.4/006-rk3328_add_mmc_reset.patch 0 → 100644
浏览文件 @ c7c02dfa
From 764e6cf1c0ffcfdbac7a259bc3ce4a7c4f221f75 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 29 Dec 2019 22:13:22 +0000
Subject: [PATCH] arm64: dts: rockchip: add mmc reset on rk3328
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 635f68fdc85c..3c50c11c2e5b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -831,6 +831,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
@@ -843,6 +845,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
status = "disabled";
};
@@ -855,6 +859,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
status = "disabled";
};
target/linux/rockchip/patches-5.4/008-mmc_rename.patch 0 → 100644
浏览文件 @ c7c02dfa
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