Merge pull request #1253 from gokemicro/master

[BSP] Add gokemicro gkipc bsp

bsp/gkipc/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=32
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+# CONFIG_RT_THREAD_PRIORITY_32 is not set
+CONFIG_RT_THREAD_PRIORITY_256=y
+CONFIG_RT_THREAD_PRIORITY_MAX=256
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_DEBUG=y
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_DEBUG_INIT=0
+CONFIG_RT_DEBUG_THREAD=0
+CONFIG_RT_USING_HOOK=y
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=10240
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_INTERRUPT_INFO=y
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384
+
+#
+# C++ features
+#
+CONFIG_RT_USING_CPLUSPLUS=y
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=9
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=9
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+CONFIG_RT_DFS_ELM_USE_LFN_0=y
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
+CONFIG_RT_DFS_ELM_USE_LFN=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_NET is not set
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+CONFIG_RT_USING_DFS_JFFS2=y
+CONFIG_RT_USING_DFS_NFS=y
+CONFIG_RT_NFS_HOST_EXPORT="192.168.10.82:/"
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+CONFIG_RT_USING_I2C_BITOPS=y
+CONFIG_RT_USING_PIN=y
+CONFIG_RT_USING_MTD_NOR=y
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_W25QXX is not set
+# CONFIG_RT_USING_GD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+CONFIG_RT_USING_PTHREADS=y
+# CONFIG_RT_USING_POSIX is not set
+
+#
+# Network stack
+#
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+# CONFIG_RT_LWIP_RAW is not set
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=64
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=10
+CONFIG_RT_LWIP_UDP_PCB_NUM=64
+CONFIG_RT_LWIP_TCP_PCB_NUM=8
+CONFIG_RT_LWIP_TCP_SEG_NUM=256
+CONFIG_RT_LWIP_TCP_SND_BUF=12040
+CONFIG_RT_LWIP_TCP_WND=11680
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=100
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=32768
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=126
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32
+CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+CONFIG_LWIP_USING_DHCPD=y
+
+#
+# RT-Thread UI Engine
+#
+# CONFIG_RT_USING_GUIENGINE is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_IPERF is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+
+# CONFIG_SOC_GK7101 is not set
+# CONFIG_SOC_GK7102 is not set
+# CONFIG_SOC_GK7101S is not set
+# CONFIG_SOC_GK7102S is not set
+CONFIG_SOC_GK7102C=y
+CONFIG_BOARD_GK7102C_EVB=y
+CONFIG_SENSOR_TYPE_SC1135=y
+# CONFIG_SENSOR_TYPE_SC1145 is not set
+# CONFIG_SENSOR_TYPE_JXH65 is not set
+# CONFIG_SENSOR_TYPE_OV9750 is not set
+# CONFIG_SENSOR_TYPE_AR0130 is not set
+# CONFIG_SENSOR_TYPE_JXH42 is not set
+CONFIG_TUNNING_TOOL_SUPPORT=y
+CONFIG_RT_USING_DMA_MEM=y
+CONFIG_ARM1176_USE_VFP=y
+CONFIG_RT_USING_VFP=y
+CONFIG_RT_USING_CPU_FFS=y
+
+#
+# Goke Peripheral Device Config
+#
+CONFIG_RT_USING_ADC=y
+CONFIG_RT_USING_GMAC=y
+CONFIG_RT_USING_PWM=y
+CONFIG_RT_USING_GK_DMA=y
+CONFIG_RT_USING_LIBZ=y
+CONFIG_RT_USING_LOGCAPTURE=y
+CONFIG_RT_ALIGN_UC_SIZE=8
+CONFIG_RT_ALIGN_DSP_SIZE=32
+CONFIG_RT_DEBUG_UC_MEM=0
+CONFIG_RT_DEBUG_DSP_MEM=0

bsp/gkipc/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+
+choice
+    prompt "Device type"
+    default GK7102C
+    config SOC_GK7101
+        bool "GK7101"
+    config SOC_GK7102
+        bool "GK7102"
+    config SOC_GK7101S
+        bool "GK7101S"
+    config SOC_GK7102S
+        bool "GK7102S"
+    config SOC_GK7102C
+        bool "GK7102C"
+endchoice
+
+choice
+    prompt "Board type"
+    default GK7102C_EVB
+    config BOARD_GK7101_EVB
+        bool "GK7101_EVB"
+        depends on SOC_GK7101
+    config BOARD_GK7101_EVB
+        bool "GK7101_EVB"
+        depends on SOC_GK7102
+    config BOARD_GK7101S_EVB
+        bool "GK7101S_EVB"
+        depends on SOC_GK7101S
+    config BOARD_GK7101S_EVB
+        bool "GK7101S_EVB"
+        depends on SOC_GK7102S
+    config BOARD_GK7102C_EVB
+        bool "GK7102C_EVB"
+        depends on SOC_GK7102C
+endchoice
+
+choice
+    prompt "Sensor type"
+    default SENSOR_TYPE_SC1135
+    config SENSOR_TYPE_SC1135
+        bool "SC1135"
+    config SENSOR_TYPE_SC1145
+        bool "SC1145"
+    config SENSOR_TYPE_JXH65
+        bool "JXH65"
+    config SENSOR_TYPE_OV9750
+        bool "OV9750"
+    config SENSOR_TYPE_AR0130
+        bool "AR0130"
+    config SENSOR_TYPE_JXH42
+        bool "JXH42"
+endchoice
+
+config TUNNING_TOOL_SUPPORT
+    bool "Using Tuning Tool"
+    default y
+    
+config RT_USING_DMA_MEM
+    bool "Enable DMA Mem"
+    default y  
+
+config ARM1176_USE_VFP
+    bool "Enable ARM1176 VFP"
+    default y  
+    
+config RT_USING_VFP
+    bool "Enable VFP"
+    default y  
+
+config RT_USING_CPU_FFS
+    bool "Enable CPU FFS"
+    default y
+      
+menu "Goke Peripheral Device Config"
+    config RT_USING_ADC
+        bool "Enable ADC"
+        default y    
+ 
+    config RT_USING_GMAC
+        bool "Enable GMAC"
+        default y     
+
+    config RT_USING_PWM
+        bool "Enable PWM"
+        default y    
+  
+    config RT_USING_GK_DMA
+        bool "Enable DMA"
+        default y    
+        
+    config RT_USING_LIBZ
+        bool "Enable Zlib for firmware uncompress"
+        default y  
+        
+    config RT_USING_LOGCAPTURE
+        bool "Enable DSP Logcaputure"
+        default y
+        
+    config RT_ALIGN_UC_SIZE
+        int "Align UC Size"
+        default 8
+    
+    config RT_ALIGN_DSP_SIZE
+        int "Align DSP Size"
+        default 32
+        
+    config RT_DEBUG_UC_MEM
+        int "Debug UC Memory"
+        default 0
+    
+    config RT_DEBUG_DSP_MEM
+        int "Debug DSP Memory"
+        default 0
+endmenu 

bsp/gkipc/README.md

+# gkipc板级支持包
+
+标签： bsp说明文档
+
+---
+
+## 1. 简介
+
+GK7102C是针对高清IP Camera产品开发的一款低功耗高性能 SOC芯片，支持 960@30p多路码流 H.264 编码及高质量的 ISP 处理，内置  3D降噪和动态对比度提升模块，支持主流的多种并口 8bit/10bit/12bit sensor。视频输出支持 RGB 小型 LCD 屏显示接口。 GK7102C 内封 DDR2 DRAM 芯片，内置 Ethernet PHY, Audio codec,USB PHY 等模拟 IP。 GK7102C 拥有
+丰富的外设接口,如 USB2.0,SDIO,PWM,SPI,I2C 等等，支持最多 32 个GPIO，可灵活配置各功能模块的输出管脚，为实现高集成度 IPC提供了高性价比的解决方案。包括如下硬件特性：
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| GK7102C |
+|CPU| ARM1176ZJFS |
+|主频| 432MHz |
+|片内DDR2|  512M bit@800MHz |
+
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/gkipc`目录中，运行以下命令：
+
+    scons
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin可以通过网络加载或者烧写到设备中进行运行。
+
+## 3. 烧写及执行
+
+[需要说明电源连接情况，串口连接情况]
+
+连接好串口，可以使用115200-N-8-1的配置方式连接到设备上。设备使用的串口引脚是：`[GPIO25/GPIO26]`
+
+当正确编译产生出rtthread.bin映像文件后，可以使用tftp的方式来加载到设备中运行。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0/1/2 |
+| clock | 支持 |  |
+| SPI |  | SPI0 |
+| ADC | 支持 |  |
+| DMA | 支持 |  |
+| GMAC | 支持 |  |
+| I2C | 支持 |  |
+| PWM | 支持 |  |
+| SDIO | 支持 | SDIO0/1 |
+| WDT | 支持 |  |
+| MMC | 支持 |  |
+| SSI | 支持 |  |
+
+## 5. 联系人信息
+
+维护人：gokemicro < gokemicro@yeah.net >
+
+[1]: https://www.rt-thread.org/page/download.html
\ No newline at end of file

bsp/gkipc/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+print('------------------------------------------------')
+print('rtt_root:    ' + RTT_ROOT)
+print('current dir: ' + cwd)
+print('------------------------------------------------')
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/gkipc/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = rtconfig.OUTPUT_NAME + rtconfig.TARGET_EXT
+
+# add rtconfig.h path to the assembler
+rtconfig.AFLAGS += ' -I' + str(Dir('#')) +' -I' + str(Dir('#')) + '/bsp'
+
+env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/gkipc/applications/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+CPPPATH = [cwd, cwd + '/../drivers', cwd + '/../libraries/inc']
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/gkipc/applications/main.c

+/*
+ * File      : main.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+#include <rtthread.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#ifdef RT_USING_GMAC
+#include <drv_gmac.h>
+#endif
+
+int main(void)
+{
+#ifdef RT_USING_GMAC
+    rt_app_gk_gmac_init();
+#endif
+
+    printf("Hello\n");
+
+    return 0;
+}

bsp/gkipc/armv6/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+src	= Glob('*.c')
+src += Glob('*.s')
+path = [cwd, cwd + '../../../include', cwd + '/../libraries/inc', cwd + '/../drivers']
+
+group = DefineGroup('armv6', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/gkipc/armv6/arm1176_mmu.gcc.s

+@*******************************************************************************
+@*******************************************************************************
+@**
+@** Filename...: src/arm1176_mmu.gcc.s
+@** Source.....: src/arm1176_mmu.s
+@** Generator..: asm2gas.pl
+@** Note.......: DO NOT MODIFY THIS FILE BY HAND!
+@**
+@*******************************************************************************
+@*******************************************************************************
+
+@*******************************************************************************
+@*******************************************************************************
+@**
+@** ARM1176 Startup, MMU initialization and data cache setup
+@**
+@** This module initialized the MMU in flat memory mode, all addresses are
+@** directly mapped, vitual addresses are equal to physical addresses. The
+@** MMU is required only to enable the cache mode of dedicated memory
+@** regions.
+@**
+@** Version: $Id: arm1176_mmu.gcc.s 9143 2012-04-25 09:33:55Z jrende $
+@**
+@** (C) Copyright 2012-2013 by Goke Microelectronics Shanghai Branch**
+@*******************************************************************************
+@*******************************************************************************
+
+    .text
+    .section ".ARM1176INIT"
+    .align 8
+
+    .extern _start
+    .extern _end_readonly
+    .extern |_start|
+    .extern |ARM1176_MMU_ttb0|
+    .extern |ARM1176_MMU_ttb1|
+	
+    .equ ARM1176_PHYSICAL_TTB0_BASE,      arm1176_mmu_ttb0 
+    .equ ARM1176_PHYSICAL_TTB1_BASE,      arm1176_mmu_ttb1 
+    .equ ARM1176_TTB_ENTRIES,             4096 
+
+    .if CPU_USE_GK710XS==1
+    .equ ARM1176_PHYSICAL_PERI_BASE,       0x90000000 
+    .else
+    .equ ARM1176_PHYSICAL_PERI_BASE,       0x60000000 
+    .endif
+    .equ ARM1176_PHYSICAL_PERI_SIZE,       0x20000000 
+    .equ ARM1176_REMAPPED_PERI_BASE,       ARM1176_PHYSICAL_PERI_BASE 
+
+    .equ ARM1176_PHYSICAL_PPM_BASE,        DDR_MEMORY_PPM_BASE 
+    .equ ARM1176_PHYSICAL_PPM_SIZE,        DDR_MEMORY_PPM_SIZE 
+    .equ ARM1176_REMAPPED_PPM_BASE,        ARM1176_PHYSICAL_PPM_BASE
+	
+    .equ ARM1176_PHYSICAL_RTOS_BASE,       DDR_MEMORY_OS_BASE 
+    .equ ARM1176_PHYSICAL_RTOS_SIZE,       DDR_MEMORY_OS_SIZE
+    .equ ARM1176_REMAPPED_RTOS_BASE,       ARM1176_PHYSICAL_RTOS_BASE
+
+@  use mmu map bsb address from 0xCxxxxxxx(DDR_MEMORY_BSB_BASE) to 0xD0000000|DDR_MEMORY_BSB_BASE
+    .equ ARM1176_PHYSICAL_BSB_REAMP_BASE,   0xD0000000
+    .equ ARM1176_PHYSICAL_BSB_BASE,        DDR_MEMORY_BSB_BASE
+    .equ ARM1176_PHYSICAL_BSB_SIZE,        DDR_MEMORY_BSB_SIZE 
+    .equ ARM1176_REMAPPED_BSB_BASE,        ARM1176_PHYSICAL_BSB_BASE|ARM1176_PHYSICAL_BSB_REAMP_BASE
+
+@  use mmu remap bsb address 0xCxxxxxxx(DDR_MEMORY_BSB_BASE) to ARM1176_REMAPPED_BSB_BASE+DDR_MEMORY_BSB_SIZE, it resolve bsb data revert.
+    .equ ARM1176_PHYSICAL_BSB_BASE,        DDR_MEMORY_BSB_BASE
+    .equ ARM1176_PHYSICAL_BSB_SIZE,        DDR_MEMORY_BSB_SIZE 
+    .equ ARM1176_REMAPPED_BSB_BASE_EXT,    ARM1176_REMAPPED_BSB_BASE+DDR_MEMORY_BSB_SIZE
+	
+	.equ ARM1176_PHYSICAL_DSP_BASE,        DDR_MEMORY_DSP_BASE 
+    .equ ARM1176_PHYSICAL_DSP_SIZE,        DDR_MEMORY_DSP_SIZE 
+    .equ ARM1176_REMAPPED_DSP_BASE,        ARM1176_PHYSICAL_DSP_BASE 
+	
+    .equ ARM1176_1MB_CACHE_NOBUFFER,      0x00000DEA  @ cachable/non-bufferable
+    .equ ARM1176_1MB_CACHE_BUFFER,        0x00000DEE  @ cachable/bufferable
+    .equ ARM1176_1MB_NOCACHE_NOBUFFER,    0x00000DE2  @ non-cachable/non-bufferable
+    .equ ARM1176_1MB_NORMAL_NOCACHE,      0x00001DE2  @ Normal memory, non-cachable/non-bufferable
+    .equ ARM1176_1MB_CACHE_BUFFER_RO,     0x000011EE  @ cachable/bufferable read-only
+    .equ ARM1176_1MB_NOCACHE_NOBUFFER_RO, 0x000011E2  @ non-cachable/non-bufferable read-only
+
+@*******************************************************************************
+@** Initialise the MMU
+@*******************************************************************************
+
+    .global ARM1176_MmuInitialise
+
+ARM1176_MmuInitialise:
+
+@*******************************************************************************
+@** save link register on r11 as we are using bl commands internally
+@*******************************************************************************
+
+    mov r11,lr
+
+@*******************************************************************************
+@** if MMU/MPU enabled - disable (useful for ARMulator tests)
+@*******************************************************************************
+
+    mrc p15,0,r0,c1,c0,0 @ read CP15 register 1 into r0
+    bic r0,r0,#0x1000    @ disable I-cache
+    bic r0,r0,#0x0004    @ disable D-cache
+    bic r0,r0,#0x0001    @ disable MMU
+    mcr p15,0,r0,c1,c0,0 @ write value back
+
+@*******************************************************************************
+@** MMU Configuration
+@**
+@** Configure system to use extended v6 format pagetables
+@** Set translation table base
+@** Specify v6 format pagetables with no subpages
+@** set bit 23 [XP] in CP15 control register.
+@** ARM1176 supports two translation tables
+@** Configure translation table base (TTB) control register cp15,c2
+@** to a value of all zeros, indicates we are using TTB register 0.
+@*******************************************************************************
+
+    mrc p15,0,r0,c1,c0,0 @ read CP15 register 1 into r0
+    mov r1,#0x800000
+    orr r0,r0,r1	 @ disable Subpage AP bits
+    mcr p15,0,r0,c1,c0,0 @ write value back
+    mov r0,#0x0
+    mcr p15,0,r0,c2,c0,2 @ Write Translation Table Base Control Register to 0, use Register 0
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    mcr p15,0,r0,c2,c0,0 @ Write Translation Table Base Register 0 to ARM1176_PHYSICAL_TTB0_BASE
+
+@*******************************************************************************
+@** PAGE TABLE generation
+@**
+@** Generate the page tables
+@** Build a flat translation table for the whole address space.
+@** ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx
+@**
+@** |31................20|19..18|17|16| 15|14..12|11.10|9|8....5| 4|3.2|1.0|
+@** |section base address| 0   0|nG| S|APX|   TEX|  AP |P|Domain|XN|C B|1 0|
+@**
+@** Bits[31:20] Top 12 bits of VA is pointer into table
+@** nG[17]=0.   Non global, enables matching against ASID in the TLB when set.
+@** S[16]=0.    Indicates normal memory is shared when set.
+@** Access Permissions - configure for full read/write access in all modes
+@** APX[15]=0 and AP[11:10]=11
+@**
+@** Set attributes to normal memory, non cacheable.
+@** TEX[14:12]=001 and CB[3:2]= 00
+@** P[9]=0.     ECC enabled memory (not supported on ARM1136).
+@** Domain[5:8]=1111 = Set all pages to use domain 15
+@** XN[4]:=0    Execute never disabled.
+@** Bits[1:0]   Indicate entry is a 1MB section.
+@**
+@** r0 contains the address of the translation table base
+@** r1 is loop counter
+@** r2 is level1 descriptor (bits 19:0)
+@**
+@** use loop counter to create 4096 individual table entries
+@** this writes from address 0x7FFC down to 0x4000 in word steps (4bytes).
+@**
+@** In this example we will set the cacheable attribute in the first descriptor
+@**  only, so virtual memory from 0 to 1MB will be cacheable (write back mode).
+@** TEX[14:12]=000 and CB[3:2]=11
+@*******************************************************************************
+
+@*******************************************************************************
+@** create empty TTB entries to initialize entries 0..2047
+@** r0 = TTB base address
+@** r1 = unused
+@** r2 = unused
+@** r3 = virtual DDR address, upper 12 bits shifted 20 bits right (virt. index)
+@** r4 = remap size upper 12 bits shifted 20 bits right (table max. index)
+@** r5 = unused
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE       @ set the MMU table base address
+    ldr r1,=0x00000000                      @ 0x00000000 == disable access
+    ldr r2,=0x00000000                      @ remap addresses from 0x00000000..
+    ldr r3,=0x00000000                      @                   to 0x00000000..
+    ldr r4,=0x80000000                      @ fixed remap RAM size (2048MB)
+    bl  arm1176_update_mmu_table            @ update mmu table entries
+
+@*******************************************************************************
+@** set the peri
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_NOCACHE_NOBUFFER
+    ldr r2,=ARM1176_PHYSICAL_PERI_BASE
+    ldr r3,=ARM1176_REMAPPED_PERI_BASE
+    ldr r4,=ARM1176_PHYSICAL_PERI_SIZE
+    bl  arm1176_update_mmu_table
+
+@*******************************************************************************
+@** set the ppm
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_NOCACHE_NOBUFFER
+    ldr r2,=ARM1176_PHYSICAL_PPM_BASE
+    ldr r3,=ARM1176_REMAPPED_PPM_BASE
+    ldr r4,=ARM1176_PHYSICAL_PPM_SIZE
+    bl  arm1176_update_mmu_table
+	
+@*******************************************************************************
+@** set the rtos (nocache_section(1M)/code_heap(RTOSSIZE-1M))
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_NOCACHE_NOBUFFER
+    ldr r2,=ARM1176_PHYSICAL_RTOS_BASE
+    ldr r3,=ARM1176_REMAPPED_RTOS_BASE
+    ldr r4,=0x200000
+    bl  arm1176_update_mmu_table
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_CACHE_BUFFER
+    ldr r2,=ARM1176_PHYSICAL_RTOS_BASE+0x100000
+    ldr r3,=ARM1176_REMAPPED_RTOS_BASE+0x100000
+    ldr r4,=ARM1176_PHYSICAL_RTOS_SIZE-0x100000
+    bl  arm1176_update_mmu_table
+
+@*******************************************************************************
+@** set the bsb
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_CACHE_BUFFER
+    ldr r2,=ARM1176_PHYSICAL_BSB_BASE
+    ldr r3,=ARM1176_REMAPPED_BSB_BASE
+    ldr r4,=ARM1176_PHYSICAL_BSB_SIZE
+    bl  arm1176_update_mmu_table
+
+@*******************************************************************************
+@** set the bsb again for continues address for frame address
+@*******************************************************************************
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_CACHE_BUFFER
+    ldr r2,=ARM1176_PHYSICAL_BSB_BASE
+    ldr r3,=ARM1176_REMAPPED_BSB_BASE_EXT
+    ldr r4,=ARM1176_PHYSICAL_BSB_SIZE
+    bl  arm1176_update_mmu_table
+	
+@*******************************************************************************
+@** set the dsp
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,=ARM1176_1MB_CACHE_BUFFER
+    ldr r2,=ARM1176_PHYSICAL_DSP_BASE
+    ldr r3,=ARM1176_REMAPPED_DSP_BASE
+    ldr r4,=ARM1176_PHYSICAL_DSP_SIZE
+    bl  arm1176_update_mmu_table
+	
+@*******************************************************************************
+@** copy TTB0 into TTB1
+@*******************************************************************************
+
+    ldr r0,ARM1176_PHYSICAL_TTB0_BASE
+    ldr r1,ARM1176_PHYSICAL_TTB1_BASE
+    ldr r2,=ARM1176_TTB_ENTRIES
+    bl arm1176_copy_mmu_table
+
+@*******************************************************************************
+@** Setup domain control register
+@** Enable all domains to client mode
+@*******************************************************************************
+
+    mrc p15,0,r0,c3,c0,0 @ Read Domain Access Control Register
+    ldr r0,=0x55555555   @ Initialise every domain entry to b01 (client)
+    mcr p15,0,r0,c3,c0,0 @ Write Domain Access Control Register
+
+@*******************************************************************************
+@** Now the MMU is enabled, virtual to physical address translations will occur.
+@** This will affect the next instruction fetch.
+@**
+@** The two instructions currently in the ARM pipeline will have been fetched
+@** before the MMU was enabled. This property is useful because the next two
+@** instructions are safe even if new instruction fetches fail - If this
+@** routine was mapped out of the new virtual memory map, the branch to
+@** arm1176_BootLoaderMain would still succeed.
+@*******************************************************************************
+
+    mov r0,#0             @ move 0 into r0
+    mcr p15,0,r0,c7,c5,0  @ invalidate instruction cache
+    mcr p15,0,r0,c7,c6,0  @ invalidate data cache
+    mcr p15,0,r0,c7,c10,4 @ drain write barrier
+    mcr p15,0,r0,c8,c5,0  @ reset intruction TLB entries
+    mcr p15,0,r0,c8,c6,0  @ reset data TLB entries
+    mcr p15,0,r0,c8,c7,0  @ reset unified TLB entries
+
+    mrc p15,0,r0,c1,c0,0  @ read CP15 register c1 into r0
+    orr r0,r0,#0x00001000 @ enable I-cache
+    orr r0,r0,#0x00000004 @ enable D-cache
+    orr r0,r0,#0x00000001 @ enable MMU
+    orr r0,r0,#0x00400000 @ enable unaligned load/store
+    orr r0,r0,#0x00000100 @ system bit enabled
+    bic r0,r0,#0x00000200 @ rom bit disabled
+    mcr p15,0,r0,c1,c0,0  @ write r0 back to CP15 register c1
+    mov lr,r11            @ restore link register
+    bx lr                 @ branch back to caller
+
+@*******************************************************************************
+@** create TTB entries to remap 1MB junks of memory
+@** register arguments:
+@**   r0 = TTB base address
+@**   r1 = access mask, lower 20 bits only
+@**   r2 = physical address, upper 12 bits shifted 20 bits right (phys. index)
+@**   r3 = virtual address, upper 12 bits shifted 20 bits right (virt. index)
+@**   r4 = remap size upper 12 bits shifted 20 bits right (table max. index)
+@** internal used registers:
+@**   r5 = temporary vector to be written into TTB entry
+@*******************************************************************************
+
+arm1176_update_mmu_table:
+    lsr  r2,r2,#20	@ 1M
+    lsr  r3,r3,#20	@ 1M
+    lsr  r4,r4,#20	@ 1M
+    cmp  r4,#0x0
+    bxeq lr
+    add  r4,r4,r3
+arm1176_update_mmu_table_loop: @ update r4 times 1MB entries
+    orr  r5,r1,r2,LSL#20      @ r5 now contains full L1 descriptor to write
+    str  r5,[r0,r3,LSL#2]     @ store table entry at TTB base + loopcount*4
+    add  r3,r3,#1             @ increment virtual address index
+    add  r2,r2,#1             @ increment physical address index
+    cmp  r3,r4                @ check for last entry
+    bne  arm1176_update_mmu_table_loop
+    bx lr
+
+@*******************************************************************************
+@** copy one TTB into another
+@** register arguments:
+@**   r0 = address of 1st TTB
+@**   r1 = address of 2nd TTB
+@**   r2 = table entry count
+@** internal used registers:
+@**   r3 = temporary register holding read/wrrite values
+@*******************************************************************************
+
+arm1176_copy_mmu_table:
+    cmp  r2,#0x0
+    bxeq lr
+arm1176_copy_mmu_table_loop: @ load entry from 1st table
+    ldr  r3,[r0]            @ store entry into 2nd table
+    str  r3,[r1]            @ store table entry at TTB base + loopcount*4
+    add  r0,r0,#4           @ increment 1st table address by 4 byte
+    add  r1,r1,#4           @ increment 2nd table address  by 4 byte
+    sub  r2,r2,#1           @ decrement entry counter by 1
+    cmp  r2,#0x0
+    bne  arm1176_copy_mmu_table_loop
+    bx lr
+
+@*******************************************************************************
+@** local variables containing far addresses
+@*******************************************************************************
+
+    .ltorg
+
+arm1176_image_ro_base:
+    .long _start
+arm1176_image_ro_limit:
+    .long _end_readonly
+arm1176_image_start:
+    .long _start
+arm1176_mmu_ttb0:
+    .long ARM1176_MMU_ttb0
+arm1176_mmu_ttb1:
+    .long ARM1176_MMU_ttb1
+arm1176_mmu_video_cached_ptr:
+    .long arm1176_mmu_video_cached
+arm1176_mmu_video_cached:
+    .long 0x0
+
+    .global arm1176_mmu_video_cached
+    .weak arm1176_mmu_video_cached
+
+@*******************************************************************************
+@** End of file
+@*******************************************************************************
+
+    .end

bsp/gkipc/armv6/arm1176_mmu_ttb.c

+/*
+********************************************************************************
+********************************************************************************
+**
+** \file        ./boot/startup/src/arm1176_mmu_ttb.c
+**
+** \version     $Id: arm1176_mmu_ttb.c 5280 2011-02-21 16:39:28Z wlaris $
+**
+** \brief       ARM1176 MMU page table.
+**
+** This files contains ARM1176 specific MMU page table variables.
+**
+** \attention   THIS SAMPLE CODE IS PROVIDED AS IS. GOKE SEMICONDUCTOR
+**              ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
+**              OMMISSIONS.
+**
+********************************************************************************
+********************************************************************************
+*/
+#include <stdint.h>
+#include "arm1176_mmu_ttb.h"
+
+#define ARM1176_MMU_TTB_ALIGNMENT 14
+#define ARM1176_RVS_ALIGN(bits) __align(1UL<<bits)
+#define ARM1176_GCC_ALIGN(bits) __attribute__((aligned(1UL<<bits)))
+
+#if !defined(__GNUC__)
+#define ARM1176_MMU_ALIGN_PRE ARM1176_RVS_ALIGN(ARM1176_MMU_TTB_ALIGNMENT)
+#endif
+
+#if defined(__GNUC__)
+#define ARM1176_MMU_ALIGN_POST ARM1176_GCC_ALIGN(ARM1176_MMU_TTB_ALIGNMENT)
+#endif
+
+#if defined(__LINT__)
+#undef ARM1176_RVS_ALIGN
+#define ARM1176_RVS_ALIGN(bits)
+#undef ARM1176_GCC_ALIGN
+#define ARM1176_GCC_ALIGN(bits)
+#endif
+
+/*lint -save -e785 */
+
+#if !defined(__GNUC__)
+
+    ARM1176_RVS_ALIGN(ARM1176_MMU_TTB_ALIGNMENT)
+    uint32_t ARM1176_MMU_ttb0[ARM1176_MMU_TTB_ENTRIES] __attribute__ ((section(".nocache_buffer"))) = { 0x000011E2UL };
+
+    ARM1176_RVS_ALIGN(ARM1176_MMU_TTB_ALIGNMENT)
+    uint32_t ARM1176_MMU_ttb1[ARM1176_MMU_TTB_ENTRIES] __attribute__ ((section(".nocache_buffer"))) = { 0x000011E2UL };
+
+#endif
+
+#if defined(__GNUC__)
+
+    uint32_t ARM1176_MMU_ttb0[ARM1176_MMU_TTB_ENTRIES]
+    ARM1176_GCC_ALIGN(ARM1176_MMU_TTB_ALIGNMENT) __attribute__ ((section(".nocache_buffer"))) = { 0x000011E2UL };
+
+    uint32_t ARM1176_MMU_ttb1[ARM1176_MMU_TTB_ENTRIES]
+    ARM1176_GCC_ALIGN(ARM1176_MMU_TTB_ALIGNMENT) __attribute__ ((section(".nocache_buffer"))) = { 0x000011E2UL };
+
+#endif
+
+/*lint -restore */

bsp/gkipc/armv6/arm1176_mmu_ttb.h

+/*
+********************************************************************************
+********************************************************************************
+**
+** \file        ./boot/startup/src/arm1176_mmu_ttb.h
+**
+** \version     $Id: arm1176_mmu_ttb.h 5280 2011-02-21 16:39:28Z wlaris $
+**
+** \brief       ARM1176 MMU page table.
+**
+** This files contains ARM1176 specific MMU page table variables.
+**
+** \attention   THIS SAMPLE CODE IS PROVIDED AS IS. GOKE SEMICONDUCTOR
+**              ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
+**              OMMISSIONS.
+**
+********************************************************************************
+********************************************************************************
+*/
+#ifndef STARTUP_ARM1176_MMU_TTB_H
+#define STARTUP_ARM1176_MMU_TTB_H
+
+#define ARM1176_MMU_TTB_ENTRIES 4096
+
+#define ARM1176_MMU_TTB_NUMS    8
+
+#define ARM1176_1MB_NOCACHE_BUFFER      0x00000DE6  // non-cachable/bufferable
+#define ARM1176_1MB_CACHE_NOBUFFER      0x00000DEA  // cachable/non-bufferable
+#define ARM1176_1MB_CACHE_BUFFER        0x00000DEE  // cachable/bufferable
+#define ARM1176_1MB_NOCACHE_NOBUFFER    0x00000DE2  // non-cachable/non-bufferable
+#define ARM1176_1MB_NORMAL_NOCACHE      0x00001DE2  // Normal memory, non-cachable/non-bufferable
+#define ARM1176_1MB_CACHE_BUFFER_RO     0x000011EE  // cachable/bufferable read-only
+#define ARM1176_1MB_NOCACHE_NOBUFFER_RO 0x000011E2  // non-cachable/non-bufferable read-only
+#endif

bsp/gkipc/armv6/arm1176_vfp_fast_gcc.s

+@*******************************************************************************
+@*******************************************************************************
+@**
+@** ARM1176 Startup, VFP initialization for fast mode
+@**
+@** This module initializes the VFP co-processor unit in fast mode
+@**
+@** Version: $Id: arm1176_vfp_fast.s 5280 2011-02-21 16:39:28Z wlaris $
+@**
+@** (C) Copyright 2006-2010 by Fujitsu Microelectronics Europe GmbH;**
+@** (C) Copyright 2010-2011 by Fujitsu Semiconductor Europe GmbH
+@*******************************************************************************
+@*******************************************************************************
+#if ARM1176_USE_VFP == 1
+    .text
+    .section ".ARM1176INIT"
+    .code 32
+
+@*******************************************************************************
+@** Bit pattern to enable RunFast mode
+@** - FPSCR [24] - Flush to Zero mode
+@** - FPSCR [25] - Default NaN mode
+@*******************************************************************************
+
+    .equ ARM1176_VFP_ENABLE,   0x40000000 @
+    .equ ARM1176_VFP_FASTMODE, 0x03000000 @ 2_11:SHL:24
+
+@*******************************************************************************
+@** enable the fast-mode of the VFP block
+@*******************************************************************************
+
+    .global ARM1176_VfpSetFastmode
+
+ARM1176_VfpSetFastmode:
+    mov r0,#ARM1176_VFP_FASTMODE
+    fmxr fpscr,r0
+    bx lr
+
+@*******************************************************************************
+@** enable the the VFP block
+@*******************************************************************************
+
+    .global ARM1176_VfpInitialise
+
+ARM1176_VfpInitialise:
+    mrc p15,0,r1,c1,c0,2  @ r1 = Access Control Register
+    orr r1,r1,#(0xf<<20)  @ enable full access for p10,11
+    mcr p15,0,r1,c1,c0,2  @ Access Control Register = r1
+    mov r1,#0             @
+    mcr p15,0,r1,c7,c5,4  @ flush prefetch buffer because of FMXR below and
+                          @ CP 10 & 11 were only just enabled
+    @ Enable VFP itself
+    mov  r0,#ARM1176_VFP_ENABLE
+    fmxr fpexc,r0
+    bx   lr
+
+@*******************************************************************************
+@** End of file
+@*******************************************************************************
+
+    .end
+#endif

bsp/gkipc/armv6/context_gcc.s

+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety    copy from mini2440
+ */
+
+#define NOINT			0xc0
+
+.globl __delay
+__delay:
+		subs	r0, r0, #1
+#if 1
+		movls	pc, lr
+		subs	r0, r0, #1
+		movls	pc, lr
+		subs	r0, r0, #1
+		movls	pc, lr
+		subs	r0, r0, #1
+		movls	pc, lr
+		subs	r0, r0, #1
+		movls	pc, lr
+		subs	r0, r0, #1
+		movls	pc, lr
+		subs	r0, r0, #1
+		movls	pc, lr
+		subs	r0, r0, #1
+#endif
+		bhi	__delay
+		mov	pc, lr
+
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+	mrs r0, cpsr
+	orr r1, r0, #NOINT
+	msr cpsr_c, r1
+	mov pc, lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+	msr cpsr, r0
+	mov pc, lr
+
+
+    .globl  restore_context
+    @.func   restore_context
+    
+    .globl  save_context
+    @.func   save_context
+
+save_context:
+    stmfd	sp!, {lr}		@ push pc (lr should be pushed in place of PC)
+	stmfd	sp!, {r0-r12, lr}	@ push lr & register file
+
+	mrs	r4, cpsr
+	stmfd	sp!, {r4}		@ push cpsr
+	mrs	r4, spsr
+	stmfd	sp!, {r4}		@ push spsr
+
+	str	sp, [r0]			@ store sp in preempted tasks TCB
+	mov pc, lr
+    bx lr                 @ branch back to caller
+
+
+restore_context:
+    ldr	sp, [r0]			@ get new task stack pointer
+
+	ldmfd	sp!, {r4}		@ pop new task spsr
+	msr	spsr_cxsf, r4
+	ldmfd	sp!, {r4}		@ pop new task cpsr
+	msr	spsr_cxsf, r4
+
+	ldmfd	sp!, {r0-r12, lr, pc}^	@ pop new task r0-r12, lr & pc
+
+    
+    
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+	stmfd	sp!, {lr}		@ push pc (lr should be pushed in place of PC)
+	stmfd	sp!, {r0-r12, lr}	@ push lr & register file
+
+	mrs	r4, cpsr
+	stmfd	sp!, {r4}		@ push cpsr
+	mrs	r4, spsr
+	stmfd	sp!, {r4}		@ push spsr
+
+	str	sp, [r0]			@ store sp in preempted tasks TCB
+	ldr	sp, [r1]			@ get new task stack pointer
+
+	ldmfd	sp!, {r4}		@ pop new task spsr
+	msr	spsr_cxsf, r4
+	ldmfd	sp!, {r4}		@ pop new task cpsr
+	msr	spsr_cxsf, r4
+
+	ldmfd	sp!, {r0-r12, lr, pc}^	@ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+	ldr	sp, [r0]		@ get new task stack pointer
+
+	ldmfd	sp!, {r4}		@ pop new task spsr
+	msr	spsr_cxsf, r4
+	ldmfd	sp!, {r4}		@ pop new task cpsr
+	msr	cpsr_cxsf, r4
+
+	ldmfd	sp!, {r0-r12, lr, pc}	@ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+	ldr r2, =rt_thread_switch_interrupt_flag
+	ldr r3, [r2]
+	cmp r3, #1
+	beq _reswitch
+	mov r3, #1				@ set rt_thread_switch_interrupt_flag to 1
+	str r3, [r2]
+	ldr r2, =rt_interrupt_from_thread	@ set rt_interrupt_from_thread
+	str r0, [r2]
+_reswitch:
+	ldr r2, =rt_interrupt_to_thread		@ set rt_interrupt_to_thread
+	str r1, [r2]
+	mov pc, lr

bsp/gkipc/armv6/cpuport.c

+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
+
+extern void machine_reset(void);
+extern void machine_shutdown(void);
+
+#ifdef __GNUC__
+rt_inline rt_uint32_t cp15_rd(void)
+{
+    rt_uint32_t i;
+
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
+}
+
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
+}
+#endif
+
+#ifdef __CC_ARM
+rt_inline rt_uint32_t cp15_rd(void)
+{
+    rt_uint32_t i;
+
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
+
+    return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+    rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+    rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+#endif
+
+/**
+ * enable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_enable()
+{
+    cache_enable(ICACHE_MASK);
+}
+
+/**
+ * disable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_disable()
+{
+    cache_disable(ICACHE_MASK);
+}
+
+/**
+ * return the status of I-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_icache_status()
+{
+    return (cp15_rd() & ICACHE_MASK);
+}
+
+/**
+ * enable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_enable()
+{
+    cache_enable(DCACHE_MASK);
+}
+
+/**
+ * disable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_disable()
+{
+    cache_disable(DCACHE_MASK);
+}
+
+/**
+ * return the status of D-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_dcache_status()
+{
+    return (cp15_rd() & DCACHE_MASK);
+}
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+
+    rt_kprintf("Restarting system...\n");
+    machine_reset();
+
+    while(1);   /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    machine_shutdown();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+#if defined(__CC_ARM)
+int __rt_ffs(int value)
+{
+    register rt_uint32_t x;
+
+    if (value == 0)
+        return value;
+
+    __asm
+    {
+        rsb x, value, #0
+        and x, x, value
+        clz x, x
+        rsb x, x, #32
+    }
+
+    return x;
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+int __rt_ffs(int value)
+{
+    if (value == 0)
+        return value;
+
+    __ASM("RSB  r4, r0, #0");
+    __ASM("AND  r4, r4, r0");
+    __ASM("CLZ  r4, r4");
+    __ASM("RSB  r0, r4, #32");
+}
+#elif defined(__GNUC__)
+int __rt_ffs(int value)
+{
+    if (value == 0)
+        return value;
+
+    value &= (-value);
+    asm ("clz %0, %1": "=r"(value) :"r"(value));
+
+    return (32 - value);
+}
+#endif
+
+#endif
+
+/*
+rt_base_t rt_hw_interrupt_disable()
+{
+    unsigned long old;
+    unsigned long tmp;
+
+    __asm__ __volatile__ (
+        "mrs %0, cpsr\n"
+        "orr %1, %0, #0xc0\n"
+        "msr cpsr_c, %1"
+        : "=r" (old), "=r" (tmp)
+        :
+        : "memory");
+
+    return old;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    unsigned long tmp;
+
+
+    __asm__ __volatile__ (
+        "mrs %0, cpsr\n"
+        "bic %0, %0, #0xc0\n"
+        "msr cpsr_c, %0"
+        : "=r" (tmp)
+        :
+        : "memory");
+
+}
+*/
+/*
+rt_base_t rt_hw_interrupt_disable()
+{
+    unsigned long old;
+    unsigned long tmp;
+
+    __asm__ __volatile__( "mrs %0,cpsr"     : "=r"(old) : "r"(tmp) );
+    __asm__ __volatile__( "orr %0,%1,#0xC0" : "=r"(tmp) : "r"(old) );
+    __asm__ __volatile__( "msr cpsr_c,%0"   : : "r"(tmp) );
+
+    return old;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+
+   asm volatile ( "msr cpsr_c,%0" : : "r"(level) );
+
+}
+*/
+
+/*@}*/

bsp/gkipc/armv6/gk7101.h

+/*
+ * File      : at91sam926x.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+
+ */
+
+#ifndef GK7101_H
+#define GK7101_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtthread.h>
+
+
+
+/*****************************/
+/* CPU Mode                  */
+/*****************************/
+#define USERMODE		0x10
+#define FIQMODE			0x11
+#define IRQMODE			0x12
+#define SVCMODE			0x13
+#define ABORTMODE		0x17
+#define UNDEFMODE		0x1b
+#define MODEMASK		0x1f
+#define NOINT			0xc0
+
+struct rt_hw_register
+{
+	rt_uint32_t r0;
+	rt_uint32_t r1;
+	rt_uint32_t r2;
+	rt_uint32_t r3;
+	rt_uint32_t r4;
+	rt_uint32_t r5;
+	rt_uint32_t r6;
+	rt_uint32_t r7;
+	rt_uint32_t r8;
+	rt_uint32_t r9;
+	rt_uint32_t r10;
+	rt_uint32_t fp;
+	rt_uint32_t ip;
+	rt_uint32_t sp;
+	rt_uint32_t lr;
+	rt_uint32_t pc;
+	rt_uint32_t cpsr;
+	rt_uint32_t ORIG_r0;
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+extern struct clk *clk_get(const char *id);
+extern rt_uint32_t clk_get_rate(struct clk *clk);
+extern void rt_hw_clock_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

bsp/gkipc/armv6/interrupt.c

+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rthw.h>
+#include "gk7101.h"
+
+#define MAX_HANDLERS    (64)
+
+extern rt_uint32_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+
+
+void rt_hw_interrupt_mask(int irq);
+void rt_hw_interrupt_umask(int irq);
+
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    return RT_NULL;
+}
+
+
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    //rt_int32_t i;
+    //register rt_uint32_t idx;
+
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int irq)
+{
+
+}
+
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int irq)
+{
+
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param handler the interrupt service routine to be installed
+ * @param param the interrupt service function parameter
+ * @param name the interrupt name
+ * @return old handler
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                    void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[vector].counter = 0;
+#endif
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+/*@}*/
+
+
+
+#ifdef RT_USING_FINSH
+void list_irq(void)
+{
+    int irq;
+
+#ifdef RT_USING_INTERRUPT_INFO
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
+#endif
+}
+
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT(list_irq, list system irq);
+
+#endif
+
+

bsp/gkipc/armv6/mmu.c

+/*
+ * File      : mmu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include "mmu.h"
+#include "rtthread.h"
+
+#ifdef __CC_ARM
+void mmu_setttbase(rt_uint32_t i)
+{
+	register rt_uint32_t value;
+
+   /* Invalidates all TLBs.Domain access is selected as
+    * client by configuring domain access register,
+    * in that case access controlled by permission value
+    * set by page table entry
+    */
+	value = 0;
+    __asm
+    {
+        mcr p15, 0, value, c8, c7, 0
+	}
+
+	value = 0x55555555;
+	__asm
+	{
+        mcr p15, 0, value, c3, c0, 0
+        mcr p15, 0, i, c2, c0, 0
+    }
+}
+
+void mmu_set_domain(rt_uint32_t i)
+{
+    __asm
+    {
+        mcr p15,0, i, c3, c0,  0
+    }
+}
+
+void mmu_enable()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x01
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_disable()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x01
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_enable_icache()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x1000
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_enable_dcache()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x04
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_disable_icache()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x1000
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_disable_dcache()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x04
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_enable_alignfault()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, #0x02
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_disable_alignfault()
+{
+    register rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, #0x02
+        mcr p15, 0, value, c1, c0, 0
+    }
+}
+
+void mmu_clean_invalidated_cache_index(int index)
+{
+    __asm
+    {
+        mcr p15, 0, index, c7, c14, 2
+    }
+}
+
+void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
+{
+    unsigned int ptr;
+
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+
+    while(ptr < buffer + size)
+    {
+    	__asm
+    	{
+    		MCR p15, 0, ptr, c7, c14, 1
+    	}
+        ptr += CACHE_LINE_SIZE;
+    }
+}
+
+void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
+{
+	unsigned int ptr;
+
+	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+
+	while (ptr < buffer + size)
+	{
+		__asm
+		{
+			MCR p15, 0, ptr, c7, c10, 1
+		}
+		ptr += CACHE_LINE_SIZE;
+	}
+}
+
+void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
+{
+	unsigned int ptr;
+
+	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+
+	while (ptr < buffer + size)
+	{
+		__asm
+		{
+			MCR p15, 0, ptr, c7, c6, 1
+		}
+		ptr += CACHE_LINE_SIZE;
+	}
+}
+
+void mmu_invalidate_tlb()
+{
+    register rt_uint32_t value;
+
+    value = 0;
+    __asm
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
+}
+
+void mmu_invalidate_icache()
+{
+    register rt_uint32_t value;
+
+    value = 0;
+
+    __asm
+    {
+        mcr p15, 0, value, c7, c5, 0
+    }
+}
+
+
+void mmu_invalidate_dcache_all()
+{
+    register rt_uint32_t value;
+
+    value = 0;
+
+    __asm
+    {
+        mcr p15, 0, value, c7, c6, 0
+    }
+}
+#elif defined(__GNUC__)
+void mmu_setttbase(register rt_uint32_t i)
+{
+	//register rt_uint32_t value;
+
+   /* Invalidates all TLBs.Domain access is selected as
+    * client by configuring domain access register,
+    * in that case access controlled by permission value
+    * set by page table entry
+    */
+#if 0
+	value = 0;
+	asm ("mcr p15, 0, %0, c8,c7, 0"::"r"(value));
+
+	value = 0x55555555;
+	asm ("mcr p15, 0, %0, c3,c0, 0"::"r"(value));
+	asm ("mcr p15, 0, %0, c2,c0, 0"::"r"(i));
+#endif
+
+	asm (
+    	"mrc p15,0,r0,c1,c0,0 \r\n"
+        "mov r1,#0x800000  \r\n"
+        "orr r0,r0,r1	 @ disable Subpage AP bits  \r\n"
+        "mcr p15,0,r0,c1,c0,0 @ write value back  \r\n"
+        "mov r0,#0x0  \r\n"
+        "mcr p15,0,r0,c2,c0,2 @ W  \r\n"
+    );
+    asm("mcr p15,0,%0,c2,c0,0"::"r"(i));
+}
+
+void mmu_set_domain(register rt_uint32_t i)
+{
+	asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+}
+
+void mmu_enable()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i |= 0x1;
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disable()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i &= ~0x1;
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_enable_icache()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i |= (1 << 12);
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_enable_dcache()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i |= (1 << 2);
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disable_icache()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i &= ~(1 << 12);
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disable_dcache()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i &= ~(1 << 2);
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_enable_alignfault()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i |= (1 << 1);
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disable_alignfault()
+{
+	register rt_uint32_t i;
+
+	/* read control register */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+	i &= ~(1 << 1);
+
+	/* write back to control register */
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_clean_invalidated_cache_index(int index)
+{
+	asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+}
+
+void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
+{
+    unsigned int ptr;
+
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+
+    while(ptr < buffer + size)
+    {
+    	asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
+}
+
+
+void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
+{
+	unsigned int ptr;
+
+	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+
+	while (ptr < buffer + size)
+	{
+		asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+		ptr += CACHE_LINE_SIZE;
+	}
+}
+
+void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
+{
+	unsigned int ptr;
+
+	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+
+	while (ptr < buffer + size)
+	{
+		asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+		ptr += CACHE_LINE_SIZE;
+	}
+}
+
+void mmu_invalidate_tlb()
+{
+	asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+}
+
+void mmu_invalidate_icache()
+{
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+}
+
+void mmu_invalidate_dcache_all()
+{
+    asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+}
+#endif
+
+/* level1 page table */
+//static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
+#define ARM1176_GCC_ALIGN(bits) __attribute__((aligned(1UL<<bits)))
+#define ARM1176_MMU_TTB_ALIGNMENT 14
+static volatile unsigned int _page_table[4096]
+    ARM1176_GCC_ALIGN(ARM1176_MMU_TTB_ALIGNMENT) __attribute__ ((section(".nocache_buffer"))) = { 0x000011E2UL };
+
+void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i,nSec;
+    pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
+    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
+    for(i=0;i<=nSec;i++)
+    {
+		*pTT = attr |(((paddrStart>>20)+i)<<20);
+		pTT++;
+    }
+}
+
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
+{
+	/* disable I/D cache */
+	mmu_disable_dcache();
+	mmu_disable_icache();
+	mmu_disable();
+	mmu_invalidate_tlb();
+
+	/* set page table */
+	for (; size > 0; size--)
+	{
+		mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
+			mdesc->paddr_start, mdesc->attr);
+		mdesc++;
+	}
+
+	/* set MMU table address */
+	mmu_setttbase((rt_uint32_t)_page_table);
+
+    /* enables MMU */
+    mmu_enable();
+
+    /* enable Instruction Cache */
+    mmu_enable_icache();
+
+    /* enable Data Cache */
+    mmu_enable_dcache();
+
+    mmu_invalidate_icache();
+    mmu_invalidate_dcache_all();
+}
+
+
+
+

bsp/gkipc/armv6/mmu.h

+/*
+ * File      : mmu.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef __MMU_H__
+#define __MMU_H__
+
+#include <rtthread.h>
+
+#define CACHE_LINE_SIZE	32
+
+#define DESC_SEC		(0x2|(1<<4))
+#define CB				(3<<2)  //cache_on, write_back
+#define CNB				(2<<2)  //cache_on, write_through
+#define NCB				(1<<2)  //cache_off,WR_BUF on
+#define NCNB			(0<<2)  //cache_off,WR_BUF off
+#define AP_RW			(3<<10) //supervisor=RW, user=RW
+#define AP_RO			(2<<10) //supervisor=RW, user=RO
+
+#define DOMAIN_FAULT	(0x0)
+#define DOMAIN_CHK		(0x1)
+#define DOMAIN_NOTCHK	(0x3)
+#define DOMAIN0			(0x0<<5)
+#define DOMAIN1			(0x1<<5)
+
+#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+
+#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
+#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
+#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+
+#define ARM1176_1MB_NOCACHE_BUFFER      0x00000DE6  // non-cachable/bufferable
+#define ARM1176_1MB_CACHE_NOBUFFER      0x00000DEA  // cachable/non-bufferable
+#define ARM1176_1MB_CACHE_BUFFER        0x00000DEE  // cachable/bufferable
+#define ARM1176_1MB_NOCACHE_NOBUFFER    0x00000DE2  // non-cachable/non-bufferable
+#define ARM1176_1MB_NORMAL_NOCACHE      0x00001DE2  // Normal memory, non-cachable/non-bufferable
+#define ARM1176_1MB_CACHE_BUFFER_RO     0x000011EE  // cachable/bufferable read-only
+#define ARM1176_1MB_NOCACHE_NOBUFFER_RO 0x000011E2  // non-cachable/non-bufferable read-only
+
+
+struct mem_desc {
+	rt_uint32_t vaddr_start;
+	rt_uint32_t vaddr_end;
+	rt_uint32_t paddr_start;
+	rt_uint32_t attr;
+};
+
+void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb);
+
+#endif
+

bsp/gkipc/armv6/reset.c

+/*
+ * File      : reset.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "gk7101.h"
+
+
+
+void machine_reset(void)
+{
+
+}
+
+void machine_shutdown(void)
+{
+}
+
+/*@}*/

bsp/gkipc/armv6/rtos.h

+/*!
+********************************************************************************
+**
+** \file        ./GKOS2/inc/rtos_lib.h
+**
+** \brief       RTOS user interface
+**
+** This file contains all public API functions and definitions to use the
+** RTOS real time operating system within an application.
+**
+** \attention   THIS SAMPLE CODE IS PROVIDED AS IS. Goke SEMICONDUCTOR
+**              ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
+**              OMMISSIONS.
+**
+********************************************************************************
+*/
+#ifndef RTOS__H
+#define RTOS__H
+
+#include "rtos_lib.h"
+#include "rtos_memory.h"
+/*
+********************************************************************************
+** end of file
+********************************************************************************
+*/
+#endif /* RTOS__H */

bsp/gkipc/armv6/rtos_lib.h

+#ifndef RTOS_LIB_H
+#define RTOS_LIB_H
+#include <limits.h>
+#include <string.h>
+#include "rthw.h"
+#include "rtthread.h"
+
+#include "gtypes.h"    /* global type definitions */
+#include "gd_int.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void(*RTOS_ThreadFunctionT)(void*);
+typedef void(*RTOS_HookFunctionT)(void*);
+typedef void (*RTOS_TimerFunctionT)(void *);
+typedef void* RTOS_ThreadT;
+typedef void* RTOS_EventT;
+typedef void* RTOS_SemaphoreT;
+typedef void* RTOS_MailboxT;
+typedef void* RTOS_MailqueueT;
+typedef void* RTOS_MutexT;
+typedef void* RTOS_TimerT;
+typedef void* RTOS_CondT;
+
+typedef U32   RTOS_SYS_SemaphoreT;
+typedef void* RTOS_SYS_MailqueueT;
+
+//typedef struct rt_thread *RTOS_ThreadT;
+//typedef struct rt_semaphore * RTOS_SemaphoreT;
+//typedef struct rt_messagequeue *RTOS_MailqueueT;
+//typedef struct rt_mailbox *RTOS_MailqueueT;
+//typedef struct rt_mutex *RTOS_MutexT;
+
+/*
+********************************************************************************
+********************************************************************************
+**
+** macros to define various suspend modes
+**
+********************************************************************************
+********************************************************************************
+*/
+#define RTOS_OK                     (RTOS_Status)0   //!< The OK status
+#define RTOS_FAILURE                (RTOS_Status)-1  //!< The general FAILURE status
+
+
+#define RTOS_NO_SUSPEND                0x00000000UL //!< do not suspend, return immediately
+#define RTOS_SUSPEND                   0xFFFFFFFFUL //!< suspend forever, wait for valid event without timeout
+
+#define RTOS_MAX_MAILQUEUE_ENTRIES     4096
+#define RTOS_MSG_IS_POINTER 0xFFFFFFFFUL //!< the message to transport is a generic pointer only
+
+typedef GBOOL                    RTOS_Flag;             //!< the boolean flag type
+typedef S32                      RTOS_Status;           //!< the result status type
+typedef S32                      RTOS_Size;             //!< the generic size type
+typedef U32                      RTOS_Time;             //!< the generic time type
+typedef RTOS_TimerT              RTOS_Timer;            //!< the generic time type
+typedef RTOS_ThreadT             RTOS_Thread;           //!< the thread identifier type
+typedef S32                      RTOS_Priority;         //!< the generic priority type
+typedef RTOS_SemaphoreT          RTOS_Semaphore;        //!< the semaphore identifier type
+typedef RTOS_MutexT              RTOS_Mutex;            //!< the mutex semaphore identifier type
+typedef RTOS_MailboxT            RTOS_Mailbox;          //!< the mailbox identifier type
+typedef RTOS_MailqueueT          RTOS_Mailqueue;        //!< the mailqueue identifier type
+typedef void*                    RTOS_Message;          //!< the generic message identifier type
+typedef void*                    RTOS_Memory;           //!< the generic memory pointer type
+typedef U32                      RTOS_Segment;          //!< the memory heap segment type
+typedef RTOS_ThreadFunctionT     RTOS_ThreadFunction;   //!< the thread function definition type
+typedef RTOS_HookFunctionT       RTOS_HookFunction;     //!< the hook function definition type
+typedef RTOS_ThreadT             RTOS_ThreadData;       //!< the optional thread data structure
+typedef RTOS_CondT               RTOS_Cond;             //!< the cond semaphore identifier type
+
+
+#define GKOS_TIMER_HOOK_TABLE_SIZE   8    //!< number of timer-tick hook function entries
+#define GKOS_SWITCH_HOOK_TABLE_SIZE  4    //!< number of context-switch hook function entries
+
+#define RTOS_ThreadPriorityHighest (RTOS_Priority)127 //!< The highest possible priority
+#define RTOS_ThreadPriorityLowest  (RTOS_Priority)1   //!< The lowest possible priority
+
+/*
+********************************************************************************
+********************************************************************************
+**
+** rtos type, gkos:0, rtthread:1
+**
+********************************************************************************
+********************************************************************************
+*/
+#define RTOS_GKOS                   0
+#define RTOS_RTTHREAD               1
+
+#define RTOS_TIMER_FLAG_DEACTIVATED       0x0             /**< timer is deactive */
+#define RTOS_TIMER_FLAG_ACTIVATED         0x1             /**< timer is active */
+#define RTOS_TIMER_FLAG_ONE_SHOT          0x0             /**< one shot timer */
+#define RTOS_TIMER_FLAG_PERIODIC          0x2             /**< periodic timer */
+
+#define RTOS_TIMER_FLAG_HARD_TIMER        0x0             /**< hard timer,the timer's callback function will be called in tick isr. */
+#define RTOS_TIMER_FLAG_SOFT_TIMER        0x4             /**< soft timer,the timer's callback function will be called in timer thread. */
+
+#define RTOS_TIMER_CTRL_SET_TIME          0x0             /**< set timer control command */
+#define RTOS_TIMER_CTRL_GET_TIME          0x1             /**< get timer control command */
+#define RTOS_TIMER_CTRL_SET_ONESHOT       0x2             /**< change timer to one shot */
+#define RTOS_TIMER_CTRL_SET_PERIODIC      0x3             /**< change timer to periodic */
+
+typedef struct
+{
+    RTOS_HookFunctionT timerFunctionArray[GKOS_TIMER_HOOK_TABLE_SIZE];
+    U32                timerFunctionCount;
+    RTOS_HookFunctionT switchFunctionArray[GKOS_SWITCH_HOOK_TABLE_SIZE];
+    U32                switchFunctionCount;
+}gkosHookDataT;
+
+gkosHookDataT*      gkosHookData;
+
+
+#define THREAD_TIMESLICE       10
+
+#define RTOS_ThreadCreate(function,arg,priority,stackBuffer,stackSize)  \
+        RTOS_CreateThread(stackBuffer, stackSize, priority, function, arg, 0, 0)
+U32 RTOS_DestroyThread( RTOS_ThreadT threadHandle );
+
+#define RTOS_ThreadSleep(msecs)    rt_thread_delay(msecs)
+
+
+
+U32 RTOS_ThreadSetName( RTOS_ThreadT threadHandle, const char* optName);
+U32 RTOS_SetThreadName( RTOS_ThreadT threadHandle, const char* optName);
+char * RTOS_ThreadGetName();
+
+
+
+
+RTOS_Status RTOS_MemoryRelease( RTOS_Memory memory );
+RTOS_Memory RTOS_MemoryAllocate( RTOS_Size bytes, RTOS_Flag shared );
+RTOS_Memory RTOS_MemorySet( RTOS_Memory mem, U8 value, RTOS_Size bytes );
+RTOS_Memory RTOS_MemoryCopy( RTOS_Memory dst, RTOS_Memory src, RTOS_Size bytes );
+
+RTOS_Memory RTOS_KernelMemoryAllocate( RTOS_Size bytes);
+RTOS_Status RTOS_KernelMemoryRelease( RTOS_Memory memory );
+
+#define RTOS_ATOM_PRINTF(format, ...)   do {\
+        U32 pval = 0;\
+        RTOS_EnterCritical(pval);\
+        printf("\033[0;31m[@%s.%d]->"format"\033[0;0m\n", __FUNCTION__, __LINE__, ##__VA_ARGS__);\
+        RTOS_LeaveCritical(pval);\
+    }while(0)
+
+#define RTOS_ASSERT(EX)                                                         \
+    if (!(EX))                                                                    \
+    {                                                                             \
+        volatile char dummy = 0;                                                  \
+        U32 pval = 0;\
+        RTOS_EnterCritical(pval);\
+        printf("(%s) assert failed at %s:%d thread name:%s\n", #EX, __FUNCTION__, __LINE__, RTOS_ThreadGetSelfName());\
+        while (dummy == 0);                                                       \
+    }
+
+//U32 GKOS_EnterCriticalSection( void );
+//void GKOS_LeaveCriticalSection( U32 cpuStatus );
+
+void RTOS_LockScheduler( void );
+void RTOS_UnlockScheduler( void );
+
+void gkosFinishThread( void );
+
+U32 RTOS_SleepThread( U32 msecs );
+
+
+RTOS_SemaphoreT RTOS_CreateSemaphore( U32 initCount );
+U32 RTOS_GetSemaphore( RTOS_SemaphoreT semaphoreHandle, U32 msecsTimeout );
+U32 RTOS_SetSemaphore( RTOS_SemaphoreT semaphoreHandle, U32 msecsTimeout );
+S32 RTOS_SemaphoreQuery( RTOS_Semaphore semaphoreHandle );
+RTOS_Status RTOS_SemaphoreDestroy( RTOS_Semaphore semaphoreHandle );
+
+#define RTOS_SemaphoreWait(semaphoreHandle, suspend)		RTOS_WaitSemaphore(semaphoreHandle, suspend)
+#define RTOS_SemaphoreWaitTimeout(semaphoreHandle, timeout) RTOS_GetSemaphore((RTOS_Semaphore)semaphoreHandle, timeout)
+#define RTOS_SemaphoreCreate(initCount)                     RTOS_CreateSemaphore(initCount)
+#define RTOS_SemaphoreRelease(semaphoreHandle)              RTOS_SetSemaphore((RTOS_Semaphore)semaphoreHandle,RTOS_SUSPEND)
+
+
+void RTOS_HwTickInit(void);
+
+
+void RTOS_KernelTimerSetHook(RTOS_HookFunction function);
+
+
+RTOS_MailqueueT RTOS_CreateMailqueue( U32 queueElements, U32 elementBytes );
+#define RTOS_MailqueueCreate(elements)      RTOS_CreateMailqueue(elements, RTOS_MSG_IS_POINTER)
+
+
+#define RTOS_EnterCritical(cpusr)   {cpusr=rt_hw_interrupt_disable();}
+#define RTOS_LeaveCritical(cpusr)   {rt_hw_interrupt_enable(cpusr);}
+
+extern U32 cpu_cpsr;
+
+#define RTOS_EnterCriticalEx()   cpu_cpsr = RTOS_EnterCriticalSection()
+#define RTOS_LeaveCriticalEx()   RTOS_LeaveCriticalSection(cpu_cpsr)
+
+#define RTOS_ThreadSuspend(threadHandle)                                RTOS_SuspendThread(threadHandle)
+#define RTOS_ThreadWakeup(threadHandle)                                 RTOS_WakeupThread(threadHandle)
+
+RTOS_Status RTOS_MailqueueSend(RTOS_Mailqueue mailqueue, RTOS_Message data);
+
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+                                    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+                                    : : "r" (0) : "memory")
+
+void 	rtos_cache_inv_range(void *addr, unsigned int size);
+void 	rtos_cache_clean_range(void *addr, unsigned int size);
+
+
+U32 RTOS_Initialize(U32 Heap_size);
+
+#define RTOS_Initialize             RTOS_InitKernel
+
+#define RTOS_GetIdentity            RTOS_GetIdentity
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/*
+********************************************************************************
+** end of file
+********************************************************************************
+*/
+#endif /* RTOS_LIB_H */
+
+
+

bsp/gkipc/armv6/rtos_memory.h

+/*!
+*******************************************************************************
+**
+** \file        rtos_memory.h
+**
+** \version     1.0
+**
+** \date        March 20, 2003
+**
+** \author      Wolfgang Larisch
+**
+** \brief       A generic OS adaptation layer library
+**
+** This header file defines RTOS internal functions which are implemented
+** either in the uC/OS or the Nucleus port (maybe others OSes will follow in
+** the future).
+**
+** \attention   THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
+**              ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
+**              OMMISSIONS.
+**
+** (C) Copyright 2002 - 2007 by Goke Microelectronics China
+**
+*******************************************************************************
+*/
+#ifndef RTOS_MEMORY_H
+#define RTOS_MEMORY_H
+#include "gtypes.h"
+#include "rtos_lib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+*******************************************************************************
+**
+** \brief Allocate a bunch of memory from the system heap
+**
+** This function allocates the given size of memory from the available
+** OS controlled SDRAM heap space.
+**
+** \param  size   size of memory in bytes to allocate.
+** \param  shared a boolean value which decides whether to allocate a
+**                memory block as shared (GTRUE) or as private (GFALSE)
+**                memory. Private memory can only be de-allocated by
+**                the thread that has allocated the memory, shared
+**                memory can be de-allocated by any thread.
+**
+** \return memory a pointer to the start address of the allocated memory
+**                block, or \b NULL if the required size of memory was not
+**                available.
+**
+** \sa     rtos_types
+**
+*******************************************************************************
+*/
+RTOS_Memory RTOS_SysMemoryAllocate( RTOS_Size size, RTOS_Flag shared );
+
+/*!
+*******************************************************************************
+**
+** \brief Release (de-allocate) a bunch of system heap memory
+**
+** This function de-allocates a previoulsy allocated bunch of memory.
+**
+** \param  memory a pointer to the start of the memory block  to release.
+**
+** \return status the result status, either \b RTOS_OK,
+**                \b RTOS_MEMORY_FAILURE if the given memory pointer does not
+**                point to dynamic allocated memory  or \b RTOS_THREAD_FAILURE
+**                if the allocated memory space is owned by a different
+**                thread.
+**
+** \sa     rtos_types
+** \sa     rtos_status
+**
+*******************************************************************************
+*/
+RTOS_Status RTOS_SysMemoryRelease( RTOS_Memory memory );
+
+/*
+*******************************************************************************
+**
+** This function allocates the given size of memory from the available
+** OS controlled user heap.
+** For better performace, we control all the available OS handled RAM by
+** segments of a min. size of RTOS_HeapMinAllocSize bytes.
+**
+*******************************************************************************
+*/
+RTOS_Memory RTOS_MemoryAllocate( RTOS_Size bytes, RTOS_Flag shared );
+
+RTOS_Memory RTOS_Malloc( RTOS_Size bytes);
+
+RTOS_Memory RTOS_Realloc( RTOS_Memory addr, RTOS_Size bytes );
+
+/*
+*******************************************************************************
+**
+** This function de-allocates a previoulsy allocated bunch of memory
+** within the user heap.
+**
+*******************************************************************************
+*/
+RTOS_Status RTOS_MemoryRelease( RTOS_Memory memory );
+
+/*
+*******************************************************************************
+**
+** This function sets the given amount of bytes in the given source address
+** the the specified byte value.
+**
+*******************************************************************************
+*/
+RTOS_Memory RTOS_MemorySet( RTOS_Memory mem, U8 value, RTOS_Size bytes );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*
+*******************************************************************************
+**
+** end
+**
+*******************************************************************************
+*/
+#endif /* RTOS_MEMORY_H */

bsp/gkipc/armv6/stack.c

+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+#include <rtthread.h>
+
+/*****************************/
+/* CPU Mode                  */
+/*****************************/
+#define USERMODE		0x10
+#define FIQMODE			0x11
+#define IRQMODE			0x12
+#define SVCMODE			0x13
+#define ABORTMODE		0x17
+#define UNDEFMODE		0x1b
+#define MODEMASK		0x1f
+#define NOINT			0xc0
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+	*(--stk) = SVCMODE;						/* cpsr */
+	*(--stk) = SVCMODE;						/* spsr */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+

bsp/gkipc/armv6/start_gcc.s

+/*
+ * File      : start.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date                 Author          Notes
+ * 2016/3/9 16:27:48    louis           first version
+ */
+
+#define CONFIG_STACKSIZE    512
+#define S_FRAME_SIZE        72
+
+#define S_OLD_R0            68
+#define S_PSR               64
+#define S_PC                60
+#define S_LR                56
+#define S_SP                52
+
+#define S_IP                48
+#define S_FP                44
+#define S_R10               40
+#define S_R9                36
+#define S_R8                32
+#define S_R7                28
+#define S_R6                24
+#define S_R5                20
+#define S_R4                16
+#define S_R3                12
+#define S_R2                8
+#define S_R1                4
+#define S_R0                0
+
+.equ    USERMODE,           0x10
+.equ    FIQMODE,            0x11
+.equ    IRQMODE,            0x12
+.equ    SVCMODE,            0x13
+.equ    ABORTMODE,          0x17
+.equ    UNDEFMODE,          0x1b
+.equ    MODEMASK,           0x1f
+.equ    NOINT,              0xc0
+
+
+
+
+    .text
+    .section ".ARM1176START"
+    .code 32
+
+
+@*******************************************************************************
+@** Common cpu modes
+@*******************************************************************************
+
+    .equ ARM1176_MODE_USR,   0x10  @ CPSR_c xxx10000
+    .equ ARM1176_MODE_FIQ,   0x11  @ CPSR_c xxx10001
+    .equ ARM1176_MODE_IRQ,   0x12  @ CPSR_c xxx10010
+    .equ ARM1176_MODE_SVC,   0x13  @ CPSR_c xxx10011
+    .equ ARM1176_MODE_ABT,   0x17  @ CPSR_c xxx10111
+    .equ ARM1176_MODE_UND,   0x1B  @ CPSR_c xxx11011
+    .equ ARM1176_MODE_SYS,   0x1F  @ CPSR_c xxx11111
+    .equ ARM1176_CPSR_I_BIT, 0x80  @ CPSR_c 100xxxxx
+    .equ ARM1176_CPSR_F_BIT, 0x40  @ CPSR_c 010xxxxx
+    .equ ARM1176_CPSR_T_BIT, 0x20  @ CPSR_c 001xxxxx
+
+
+
+.globl _start
+.globl  ARM1176_Start
+_start:
+ARM1176_Start:
+    msr cpsr_c,#(ARM1176_MODE_SYS | ARM1176_CPSR_I_BIT | ARM1176_CPSR_F_BIT)    @disable irq/fiq first
+    ldr r0, =Reset          ;@load translation table base address
+    mcr p15,0,r0,c12,c0,0   ;@write translation table base address req
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+Reset:
+    ldr pc, =reset
+    ldr pc, =vector_undef
+    ldr pc, =vector_swi
+    ldr pc, =vector_pabt
+    ldr pc, =vector_dabt
+    ldr pc, =vector_resv
+    ldr pc, =vector_irq
+    ldr pc, =vector_fiq
+    nop
+    nop
+
+
+.balignl    16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+
+/*
+ * rtthread bss start and end which are defined in linker script
+ */
+
+
+.extern __stack_start__
+
+
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,  0x00000200
+.equ SVC_Stack_Size,  0x00000200
+.equ ABT_Stack_Size,  0x00000000
+.equ FIQ_Stack_Size,  0x00000000
+.equ IRQ_Stack_Size,  0x00000200
+.equ USR_Stack_Size,  0x00000200
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 FIQ_Stack_Size + IRQ_Stack_Size)
+
+.globl stack_top
+stack_top:
+    .word __stack_start__
+
+
+
+    .extern ARM1176_TcmInitialise
+    .extern ARM1176_MmuInitialise
+    .extern GH_VIC_set_EdgeClr
+    .extern entry
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table
+ *
+ *************************************************************************
+ */
+
+/* ----------------------------------entry------------------------------*/
+reset:
+    msr cpsr_c,#(ARM1176_MODE_SYS | ARM1176_CPSR_I_BIT | ARM1176_CPSR_F_BIT)    @disable irq/fiq first
+    @/* First read in some misc registers */
+    mrc p15, 0, r0, c0, c0, 0     @/* Read ID value {A5S=0x41 1 7 b36 5}*/
+    mrc p15, 0, r1, c0, c0, 1     @/* Read cache type {0x1d152152}*/
+    mrc p15, 0, r2, c0, c0, 2     @/* Read TCM status {0x10001}*/
+
+#ifdef GK7102C    
+    @mrc    p15, 0, r0, c15,c14,0  @ read CP15 register c15 into r0
+    @orr    r0,  r0,#0x80000000    @ system bit enabled
+    @bic    r0,  r0,#0x00000077    @
+    @orr    r0,  r0,#0x00000055    @ specifies 16KB data cache
+    @mcr    p15, 0, r0, c15,c14,0  @ wraite CP15 register c15 into r0
+
+    mrc     p15, 0, r0, c1, c0, 1  @read CP15 register c1 into r0
+    orr     r0,  r0,#0x00000040    @CZ bit enabled
+    mcr     p15, 0, r0, c1, c0, 1  @read CP15 register c1 into r0
+#endif
+    
+    @/* Turn on instrucion cache and disable MMU */
+    mrc p15, 0, r0, c1, c0, 0     @/* Read control register {0x5327d}*/
+    @bic r0, r0, #0x1000          @ Turn off bit 12 - I-cache
+    orr    r0, r0, #0x1000        @ Turn on bit 12 - I-cache
+    @bic r0, r0, #0x0004          @ Turn off bit 03 - D-cache
+    orr    r0, r0, #0x0004        @ Turn on bit 03 - D-cache
+    bic r0, r0, #0x2000           @ Turn off bit 13 - HV
+    bic r0, r0, #0x0001           @ Turn off bit 1 - MMU
+
+    @orr    r0, r0, #0x2    @ Turn on bit 1 - Alignment fault
+    bic r0, r0, #0x400000   @ Turn off bit 22 - Unainged support
+
+    @bic    r0, r0, #0x2        @ Turn off bit 1 - Alignment fault
+    @orr    r0, r0, #0x400000   @ Turn on bit 22 - Unainged support
+
+    mcr p15, 0, r0, c1, c0, 0   @/* Write control register */
+
+    mov r0, #0x1
+    mcr p15, 0, r0, c3, c0, 0   @/* Write domain access control reg */
+
+
+    @bl switch_core_freq    @/* Change PLL for core if necessary */
+    @bl memsetup5       @/* Initialize Memory */
+
+
+    @/* -------------------------------------------------- */
+    @/* Redirect peripheral port 0x60000000 - 0x7fffffff   */
+    @/* -------------------------------------------------- */
+    .if CPU_USE_GK710XS==1
+    mov r0, #0x80000000
+    orr r0, r0, #0x00000015 @0x14=512M
+    .else
+    mov r0, #0x60000000
+    orr r0, r0, #0x00000014 @0x14=512M
+    .endif
+    mcr p15, 0, r0, c15, c2, 4
+
+    @ clear the irq or fiq first
+    mov r0,#0x0
+    mov r1,#0xFFFFFFFF
+    bl GH_VIC_set_EdgeClr
+    mov r0,#0x1
+    mov r1,#0xFFFFFFFF
+    bl GH_VIC_set_EdgeClr
+
+    nop
+
+    @ bl ARM1176_TcmInitialise
+    msr cpsr_c,#(ARM1176_MODE_SYS | ARM1176_CPSR_I_BIT | ARM1176_CPSR_F_BIT)    @disable irq/fiq first
+    .if ARM1176_USE_VFP == 1
+    bl ARM1176_VfpInitialise
+    bl ARM1176_VfpSetFastmode
+    .endif
+    bl ARM1176_Invalid_Cache
+
+    /* setup stack */
+    ldr     r0, =stack_top
+    ldr     r0, [r0]
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #FIQ_Stack_Size
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #IRQ_Stack_Size
+
+    @  Enter Supervisor Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #SVC_Stack_Size
+
+    @  Enter User Mode and set its Stack Pointer
+    mov     sp, r0
+    sub     sl, sp, #USR_Stack_Size
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start__         /* bss start                      */
+    ldr     r2,=__bss_end__           /* bss end                            */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* call C++ constructors of global objects                          */
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
+
+ctor_loop:
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
+
+ctor_end:
+
+
+    @ need nocache buffer
+    bl ARM1176_MmuInitialise
+
+    /* start RT-Thread Kernel       */
+    ldr     pc, =entry
+
+    .global ARM1176_Invalid_Cache
+    .func   ARM1176_Invalid_Cache
+
+ARM1176_Invalid_Cache:
+    stmfd sp!,{r0-r12,lr}
+    mov r11,lr
+
+    mov r0,#0x0        @Set [31:30]
+    mov r1,#0x3
+loop1:
+    mov r2,#0x0
+    mov r3,#0x80
+
+loop2:
+    mov r4,r0,LSL #30
+    mov r5,r2,LSL #5        @Index [S+4:5] S=8 32K
+    add r4,r4,r5
+    mcr    p15, 0, r4, c7, c5, 2
+    add r2,r2,#0x1
+    cmp r2,r3
+    bne loop2
+
+    add r0,r0,#1
+    cmp r0,r1
+    bne loop1
+
+    mov lr,r11            @ restore link register
+    ldmfd sp!,{r0-r12,lr}
+    bx lr                 @ branch back to caller
+
+    .size ARM1176_Invalid_Cache, . - ARM1176_Invalid_Cache
+    .endfunc
+
+
+.global cpu_reset
+cpu_reset:
+    mov pc, lr
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+/* exception handlers               */
+    .align  5
+vector_undef:
+    sub     sp, sp, #S_FRAME_SIZE
+    stmia   sp, {r0 - r12}          /* Calling r0-r12                   */
+    add     r8, sp, #S_PC
+    stmdb   r8, {sp, lr}^           /* Calling SP, LR                   */
+    str     lr, [r8, #0]            /* Save calling PC                  */
+    mrs     r6, spsr
+    str     r6, [r8, #4]            /* Save CPSR                        */
+    str     r0, [r8, #8]            /* Save OLD_R0                      */
+    mov     r0, sp
+
+    bl      rt_hw_trap_udef
+
+    .align  5
+vector_swi:
+    bl      rt_hw_trap_swi
+
+    .align  5
+vector_pabt:
+    bl      rt_hw_trap_pabt
+
+    .align  5
+vector_dabt:
+    sub     sp, sp, #S_FRAME_SIZE
+    stmia   sp, {r0 - r12}          /* Calling r0-r12                   */
+    add     r8, sp, #S_PC
+    stmdb   r8, {sp, lr}^           /* Calling SP, LR                   */
+    str     lr, [r8, #0]            /* Save calling PC                  */
+    mrs     r6, spsr
+    str     r6, [r8, #4]            /* Save CPSR                        */
+    str     r0, [r8, #8]            /* Save OLD_R0                      */
+    mov     r0, sp
+
+    bl      rt_hw_trap_dabt
+
+    .align  5
+vector_resv:
+    bl      rt_hw_trap_resv
+
+    .align  5
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    /* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     _interrupt_thread_switch
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc, lr, #4
+
+    .align  5
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc,lr,#4
+
+_interrupt_thread_switch:
+    mov     r1,  #0                 /* clear rt_thread_switch_interrupt_flag*/
+    str     r1,  [r0]
+
+    ldmfd   sp!, {r0-r12,lr}        /* reload saved registers           */
+    stmfd   sp!, {r0-r3}            /* save r0-r3                       */
+    mov     r1,  sp
+    add     sp,  sp, #16            /* restore sp                       */
+    sub     r2,  lr, #4             /* save old task's pc to r2         */
+
+    mrs     r3,  spsr               /* disable interrupt                */
+    orr     r0,  r3, #NOINT
+    msr     spsr_c, r0
+
+    ldr     r0,  =.+8               /* switch to interrupted task's stack*/
+    movs    pc,  r0
+
+    stmfd   sp!, {r2}               /* push old task's pc               */
+    stmfd   sp!, {r4-r12,lr}        /* push old task's lr,r12-r4        */
+    mov     r4,  r1                 /* Special optimised code below     */
+    mov     r5,  r3
+    ldmfd   r4!, {r0-r3}
+    stmfd   sp!, {r0-r3}            /* push old task's r3-r0            */
+    stmfd   sp!, {r5}               /* push old task's psr              */
+    mrs     r4,  spsr
+    stmfd   sp!, {r4}               /* push old task's spsr             */
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]               /* store sp in preempted tasks's TCB*/
+
+    ldr r6,  =rt_interrupt_to_thread
+    ldr r6,  [r6]
+    ldr sp,  [r6]                   /* get new task's stack pointer     */
+
+    ldmfd   sp!, {r4}               /* pop new task's spsr              */
+    msr     SPSR_cxsf, r4
+    ldmfd   sp!, {r4}               /* pop new task's psr               */
+    msr     CPSR_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}     /* pop new task's r0-r12,lr & pc    */
+
+
+
+@*******************************************************************************
+@** End of file
+@*******************************************************************************
+

bsp/gkipc/drivers/SConscript

+from building import *
+Import('rtconfig')
+
+cwd = GetCurrentDir()
+src	= Glob('*.c')
+path = [cwd + '/..']
+
+if GetDepend('SOC_GK7101') or GetDepend('SOC_GK7102'):
+    path += [cwd + '/../libraries/drv/710X/gh/inc', cwd + '/../libraries/drv/710X/gd/inc']
+elif GetDepend('SOC_GK7101S') or GetDepend('SOC_GK7102S'):
+    path += [cwd + '/../libraries/drv/710XS/gh/inc', cwd + '/../libraries/drv/710XS/gd/inc']
+elif GetDepend('SOC_GK7102C'):
+    path += [cwd + '/../libraries/drv/7102C/gh/inc', cwd + '/../libraries/drv/7102C/gd/inc']
+	
+path += [cwd + '/../../../components/drivers/include/drivers']
+path += [cwd + '/../libraries/adi/inc']
+path += [cwd + '/../platform/board']
+path += [cwd + '/../platform']
+
+libcwd = str(Dir('#'))
+
+group = DefineGroup('drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/gkipc/drivers/drv_flash.h

+#ifndef __FLASH__
+#define __FLASH__
+
+void rt_flash_init(void);
+
+#endif

bsp/gkipc/drivers/drv_uart.h

+#ifndef UART_H_
+#define UART_H_
+
+void rt_hw_uart_init(void);
+
+
+#endif

bsp/gkipc/libraries/SConscript

+# for module compiling
+import os
+Import('rtconfig')
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+objs += SConscript(os.path.join('drv', 'SConscript'))
+  
+Return('objs')
+
+