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未验证 提交 c73c3491 编写于 作者: B Bernard Xiong 提交者： GitHub
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Merge pull request #3257 from FlyGoat/mips-refine-v1 

MIPS Base Code Refine v1
上级 4e295d00 c236e8c5
展开全部 隐藏空白更改
内联 并排
Showing with 4582 addition and 8251 deletion
bsp/ls1bdev/Kconfig 0 → 100644
浏览文件 @ c73c3491
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/libcpu/mips/common/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_LS1B
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
if RT_USING_SERIAL
config RT_USING_UART0
bool "Using RT_USING_UART0"
default y
config RT_USING_UART1
bool "Using RT_USING_UART1"
default n
config RT_USING_UART3
bool "Using RT_USING_UART3"
default n
config RT_UART_RX_BUFFER_SIZE
int "The rx buffer size"
default 64 if RT_USING_SERIAL
default 64
endif
bsp/ls1bdev/SConstruct
浏览文件 @ c73c3491
...@@ -14,10 +14,10 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT ...@@ -14,10 +14,10 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[]) DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'], env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc', AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH) env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT') Export('RTT_ROOT')
......
bsp/ls1bdev/applications/application.c 已删除 100644 → 0
浏览文件 @ 4e295d00
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B
*/
#include <rtthread.h>
#include <ls1b.h>
#ifdef RT_USING_RTGUI
#include <rtgui/rtgui.h>
extern void rt_hw_dc_init(void);
#endif
void rt_init_thread_entry(void *parameter)
{
#ifdef RT_USING_RTGUI
{
rt_device_t dc;
/* init Display Controller */
rt_hw_dc_init();
/* find Display Controller device */
dc = rt_device_find("dc");
/* set Display Controller device as rtgui graphic driver */
rtgui_graphic_set_device(dc);
}
#endif
#ifdef RT_USING_COMPONENTS_INIT
/* initialization RT-Thread Components */
rt_components_init();
#endif
}
int rt_application_init(void)
{
rt_thread_t tid;
/* create initialization thread */
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
4096, 8, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
bsp/ls1bdev/applications/main.c 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-10 zhuangwei first version
*/
#include <rtthread.h>
int main(int argc, char** argv)
{
return 0;
}
bsp/ls1bdev/applications/startup.c 已删除 100644 → 0
浏览文件 @ 4e295d00
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#define A_K0BASE 0x80000000
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
extern unsigned char __bss_end;
extern int rt_application_init(void);
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
extern void rt_hw_cache_init(void);
extern void invalidate_writeback_dcache_all(void);
extern void invalidate_icache_all(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* init cache */
rt_hw_cache_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
/* copy vector */
rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
invalidate_writeback_dcache_all();
invalidate_icache_all();
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
/* initialize timer */
rt_system_timer_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* init application */
rt_application_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return;
}
/*@}*/
bsp/ls1bdev/drivers/board.c
浏览文件 @ c73c3491
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
* Date Author Notes * Date Author Notes
* 2010-06-25 Bernard first version * 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B * 2011-08-08 lgnq modified for Loongson LS1B
* 2019-12-04 Jiaxun Yang Adapt new MIPS generic code
*/ */
#include <rtthread.h> #include <rtthread.h>
...@@ -20,92 +21,68 @@ ...@@ -20,92 +21,68 @@
#include "uart.h" #include "uart.h"
#include "ls1b.h" #include "ls1b.h"
#ifdef RT_USING_RTGUI
#include <rtgui/rtgui.h>
rt_device_t dc;
extern void rt_hw_dc_init(void);
#endif
extern unsigned char __bss_end;
/** /**
* @addtogroup Loongson LS1B * @addtogroup Loongson LS1B
*/ */
/*@{*/ /*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
}
/** /**
* This function will initial sam7s64 board. * This function will initial sam7s64 board.
*/ */
void rt_hw_board_init(void) void rt_hw_board_init(void)
{ {
#ifdef RT_USING_UART /* init hardware interrupt */
/* init hardware UART device */ rt_hw_exception_init();
rt_hw_uart_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
#ifdef RT_USING_SERIAL
/* init hardware UART device */
rt_hw_uart_init();
#endif #endif
#ifdef RT_USING_CONSOLE #ifdef RT_USING_CONSOLE
/* set console device */ /* set console device */
rt_console_set_device("uart0"); rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif #endif
/* init operating system timer */
rt_hw_timer_init();
/* init operating system timer */ #ifdef RT_USING_FPU
rt_hw_timer_init(); /* init hardware fpu */
rt_hw_fpu_init();
#endif
rt_kprintf("current sr: 0x%08x\n", read_c0_status()); #ifdef RT_USING_RTGUI
} rt_device_t dc;
#define __raw_out_put(unr) \ /* init Display Controller */
while (*ptr) \ rt_hw_dc_init();
{ \
if (*ptr == '\n') \
{ \
/* FIFO status, contain valid data */ \
while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
/* write data */ \
UART_DAT(UART##unr##_BASE) = '\r'; \
} \
/* FIFO status, contain valid data */ \
while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
/* write data */ \
UART_DAT(UART##unr##_BASE) = *ptr; \
ptr ++; \
}
/* UART line status register value */ /* find Display Controller device */
#define UARTLSR_ERROR (1 << 7) dc = rt_device_find("dc");
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5) /* set Display Controller device as rtgui graphic driver */
#define UARTLSR_BI (1 << 4) rtgui_graphic_set_device(dc);
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_console_output(const char *ptr)
{
#if defined(RT_USING_UART0)
__raw_out_put(0);
#elif defined(RT_USING_UART1)
__raw_out_put(1);
#elif defined(RT_USING_UART3)
__raw_out_put(3);
#endif #endif
}
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
/*@}*/ /*@}*/
bsp/ls1bdev/drivers/uart.c
浏览文件 @ c73c3491
...@@ -23,257 +23,257 @@ ...@@ -23,257 +23,257 @@
/*@{*/ /*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE) #if defined(RT_USING_DEVICE)
struct rt_uart_ls1b struct rt_uart_ls1b
{ {
struct rt_device parent; struct rt_device parent;
rt_uint32_t hw_base; rt_uint32_t hw_base;
rt_uint32_t irq; rt_uint32_t irq;
/* buffer for reception */ /* buffer for reception */
rt_uint8_t read_index, save_index; rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device; }uart_device;
static void rt_uart_irqhandler(int irqno, void *param) static void rt_uart_irqhandler(int irqno, void *param)
{ {
rt_ubase_t level; rt_ubase_t level;
rt_uint8_t isr; rt_uint8_t isr;
struct rt_uart_ls1b *uart = &uart_device; struct rt_uart_ls1b *uart = &uart_device;
/* read interrupt status and clear it */ /* read interrupt status and clear it */
isr = UART_IIR(uart->hw_base); isr = UART_IIR(uart->hw_base);
isr = (isr >> 1) & 0x3; isr = (isr >> 1) & 0x3;
/* receive data available */ /* receive data available */
if (isr & 0x02) if (isr & 0x02)
{ {
/* Receive Data Available */ /* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR) while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{ {
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base); uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
uart->save_index ++; uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0; uart->save_index = 0;
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
} }
/* invoke callback */ /* invoke callback */
if (uart->parent.rx_indicate != RT_NULL) if (uart->parent.rx_indicate != RT_NULL)
{ {
rt_size_t length; rt_size_t length;
if (uart->read_index > uart->save_index) if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else else
length = uart->save_index - uart->read_index; length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length); uart->parent.rx_indicate(&uart->parent, length);
} }
} }
return; return;
} }
static rt_err_t rt_uart_init(rt_device_t dev) static rt_err_t rt_uart_init(rt_device_t dev)
{ {
rt_uint32_t baud_div; rt_uint32_t baud_div;
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
#if 0 #if 0
/* init UART Hardware */ /* init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */ UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */ UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
/* enable UART clock */ /* enable UART clock */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = 0x3; UART_LCR(uart->hw_base) = 0x3;
/* set baudrate */ /* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE; baud_div = DEV_CLK / 16 / UART_BAUDRATE;
UART_LCR(uart->hw_base) |= UARTLCR_DLAB; UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff; UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_LSB(uart->hw_base) = baud_div & 0xff; UART_LSB(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB; UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
/* Enable UART unit, enable and clear FIFO */ /* Enable UART unit, enable and clear FIFO */
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS; UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
#endif #endif
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{ {
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX) if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{ {
/* Enable the UART Interrupt */ /* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= UARTIER_IRXE; UART_IER(uart->hw_base) |= UARTIER_IRXE;
/* install interrupt */ /* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART"); rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
rt_hw_interrupt_umask(uart->irq); rt_hw_interrupt_umask(uart->irq);
} }
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_uart_close(rt_device_t dev) static rt_err_t rt_uart_close(rt_device_t dev)
{ {
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX) if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{ {
/* Disable the UART Interrupt */ /* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE); UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
} }
return RT_EOK; return RT_EOK;
} }
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{ {
rt_uint8_t *ptr; rt_uint8_t *ptr;
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
/* point to buffer */ /* point to buffer */
ptr = (rt_uint8_t *)buffer; ptr = (rt_uint8_t *)buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX) if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{ {
while (size) while (size)
{ {
/* interrupt receive */ /* interrupt receive */
rt_base_t level; rt_base_t level;
/* disable interrupt */ /* disable interrupt */
level = rt_hw_interrupt_disable(); level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index) if (uart->read_index != uart->save_index)
{ {
*ptr = uart->rx_buffer[uart->read_index]; *ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++; uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0; uart->read_index = 0;
} }
else else
{ {
/* no data in rx buffer */ /* no data in rx buffer */
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
break; break;
} }
/* enable interrupt */ /* enable interrupt */
rt_hw_interrupt_enable(level); rt_hw_interrupt_enable(level);
ptr ++; ptr ++;
size --; size --;
} }
return (rt_uint32_t)ptr - (rt_uint32_t)buffer; return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
} }
return 0; return 0;
} }
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{ {
char *ptr; char *ptr;
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev; struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
RT_ASSERT(uart != RT_NULL); RT_ASSERT(uart != RT_NULL);
ptr = (char *)buffer; ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM) if (dev->flag & RT_DEVICE_FLAG_STREAM)
{ {
/* stream mode */ /* stream mode */
while (size) while (size)
{ {
if (*ptr == '\n') if (*ptr == '\n')
{ {
/* FIFO status, contain valid data */ /* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */ /* write data */
UART_DAT(uart->hw_base) = '\r'; UART_DAT(uart->hw_base) = '\r';
} }
/* FIFO status, contain valid data */ /* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */ /* write data */
UART_DAT(uart->hw_base) = *ptr; UART_DAT(uart->hw_base) = *ptr;
ptr ++; ptr ++;
size --; size --;
} }
} }
else else
{ {
while (size != 0) while (size != 0)
{ {
/* FIFO status, contain valid data */ /* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE))); while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */ /* write data */
UART_DAT(uart->hw_base) = *ptr; UART_DAT(uart->hw_base) = *ptr;
ptr++; ptr++;
size--; size--;
} }
} }
return (rt_size_t)ptr - (rt_size_t)buffer; return (rt_size_t)ptr - (rt_size_t)buffer;
} }
void rt_hw_uart_init(void) void rt_hw_uart_init(void)
{ {
struct rt_uart_ls1b *uart; struct rt_uart_ls1b *uart;
/* get uart device */ /* get uart device */
uart = &uart_device; uart = &uart_device;
/* device initialization */ /* device initialization */
uart->parent.type = RT_Device_Class_Char; uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0; uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART0) #if defined(RT_USING_UART0)
uart->hw_base = UART0_BASE; uart->hw_base = UART0_BASE;
uart->irq = LS1B_UART0_IRQ; uart->irq = LS1B_UART0_IRQ;
#elif defined(RT_USING_UART1) #elif defined(RT_USING_UART1)
uart->hw_base = UART1_BASE; uart->hw_base = UART1_BASE;
uart->irq = LS1B_UART1_IRQ; uart->irq = LS1B_UART1_IRQ;
#elif defined(RT_USING_UART3) #elif defined(RT_USING_UART3)
uart->hw_base = UART3_BASE; uart->hw_base = UART3_BASE;
uart->irq = LS1B_UART3_IRQ; uart->irq = LS1B_UART3_IRQ;
#endif #endif
/* device interface */ /* device interface */
uart->parent.init = rt_uart_init; uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open; uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close; uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read; uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write; uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL; uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL; uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent, "uart0", rt_device_register(&uart->parent, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_RDWR |
RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_STREAM |
RT_DEVICE_FLAG_INT_RX); RT_DEVICE_FLAG_INT_RX);
} }
#endif /* end of UART */ #endif /* end of UART */
......
bsp/ls1bdev/drivers/uart.h
浏览文件 @ c73c3491
...@@ -16,8 +16,9 @@ ...@@ -16,8 +16,9 @@
#define __UART_H__ #define __UART_H__
#include "ls1b.h" #include "ls1b.h"
#include <rthw.h>
#define UART0_BASE 0xBFE40000 #define UART0_BASE 0xBFE40000
#define UART0_1_BASE 0xBFE41000 #define UART0_1_BASE 0xBFE41000
#define UART0_2_BASE 0xBFE42000 #define UART0_2_BASE 0xBFE42000
#define UART0_3_BASE 0xBFE43000 #define UART0_3_BASE 0xBFE43000
...@@ -31,43 +32,43 @@ ...@@ -31,43 +32,43 @@
#define UART5_BASE 0xBFE7C000 #define UART5_BASE 0xBFE7C000
/* UART registers */ /* UART registers */
#define UART_DAT(base) __REG8(base + 0x00) #define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) __REG8(base + 0x01) #define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) __REG8(base + 0x02) #define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) __REG8(base + 0x02) #define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) __REG8(base + 0x03) #define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) __REG8(base + 0x04) #define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) __REG8(base + 0x05) #define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) __REG8(base + 0x06) #define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) __REG8(base + 0x00) #define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) __REG8(base + 0x01) #define UART_MSB(base) HWREG8(base + 0x01)
/* UART0 registers */ /* UART0 registers */
#define UART0_DAT __REG8(UART0_BASE + 0x00) #define UART0_DAT HWREG8(UART0_BASE + 0x00)
#define UART0_IER __REG8(UART0_BASE + 0x01) #define UART0_IER HWREG8(UART0_BASE + 0x01)
#define UART0_IIR __REG8(UART0_BASE + 0x02) #define UART0_IIR HWREG8(UART0_BASE + 0x02)
#define UART0_FCR __REG8(UART0_BASE + 0x02) #define UART0_FCR HWREG8(UART0_BASE + 0x02)
#define UART0_LCR __REG8(UART0_BASE + 0x03) #define UART0_LCR HWREG8(UART0_BASE + 0x03)
#define UART0_MCR __REG8(UART0_BASE + 0x04) #define UART0_MCR HWREG8(UART0_BASE + 0x04)
#define UART0_LSR __REG8(UART0_BASE + 0x05) #define UART0_LSR HWREG8(UART0_BASE + 0x05)
#define UART0_MSR __REG8(UART0_BASE + 0x06) #define UART0_MSR HWREG8(UART0_BASE + 0x06)
#define UART0_LSB __REG8(UART0_BASE + 0x00) #define UART0_LSB HWREG8(UART0_BASE + 0x00)
#define UART0_MSB __REG8(UART0_BASE + 0x01) #define UART0_MSB HWREG8(UART0_BASE + 0x01)
/* UART1 registers */ /* UART1 registers */
#define UART1_DAT __REG8(UART1_BASE + 0x00) #define UART1_DAT HWREG8(UART1_BASE + 0x00)
#define UART1_IER __REG8(UART1_BASE + 0x01) #define UART1_IER HWREG8(UART1_BASE + 0x01)
#define UART1_IIR __REG8(UART1_BASE + 0x02) #define UART1_IIR HWREG8(UART1_BASE + 0x02)
#define UART1_FCR __REG8(UART1_BASE + 0x02) #define UART1_FCR HWREG8(UART1_BASE + 0x02)
#define UART1_LCR __REG8(UART1_BASE + 0x03) #define UART1_LCR HWREG8(UART1_BASE + 0x03)
#define UART1_MCR __REG8(UART1_BASE + 0x04) #define UART1_MCR HWREG8(UART1_BASE + 0x04)
#define UART1_LSR __REG8(UART1_BASE + 0x05) #define UART1_LSR HWREG8(UART1_BASE + 0x05)
#define UART1_MSR __REG8(UART1_BASE + 0x06) #define UART1_MSR HWREG8(UART1_BASE + 0x06)
#define UART1_LSB __REG8(UART1_BASE + 0x00) #define UART1_LSB HWREG8(UART1_BASE + 0x00)
#define UART1_MSB __REG8(UART1_BASE + 0x01) #define UART1_MSB HWREG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */ /* UART interrupt enable register value */
#define UARTIER_IME (1 << 3) #define UARTIER_IME (1 << 3)
......
bsp/ls1bdev/ls1b_ram.lds
浏览文件 @ c73c3491
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
* Date Author Notes * Date Author Notes
* 2010-05-17 swkyer first version * 2010-05-17 swkyer first version
* 2010-09-04 bernard move the beginning entry to 0x80200000 * 2010-09-04 bernard move the beginning entry to 0x80200000
* 2019-12-04 Jiaxun Yang Adapt new memory layout
*/ */
OUTPUT_ARCH(mips) OUTPUT_ARCH(mips)
...@@ -19,16 +20,19 @@ GROUP(-lgcc -lc) ...@@ -19,16 +20,19 @@ GROUP(-lgcc -lc)
ENTRY(_start) ENTRY(_start)
SECTIONS SECTIONS
{ {
. = 0x80200000 ; . = 0x80200000;
.start :
{
*(.start);
}
. = ALIGN(4);
.text : .text :
{ {
start = ABSOLUTE(.);
*(.selfboot);
*(.selfboot_data);
. = ALIGN(4);
__selfboot_end = .;
. = ALIGN(0x1000);
__ebase_entry = .;
KEEP(*(.exc_vectors))
__ebase_end = .;
*(.start);
*(.text) *(.text)
*(.text.*) *(.text.*)
*(.rodata) *(.rodata)
...@@ -76,6 +80,15 @@ SECTIONS ...@@ -76,6 +80,15 @@ SECTIONS
*(.sdata) *(.sdata)
*(.sdata.*) *(.sdata.*)
} }
_edata = .;
.stack :
{
. = ALIGN(8);
_system_stack_start = .;
. = . + 0x400; /* 1kb system stack */
_system_stack = .;
}
.sbss : .sbss :
{ {
......
bsp/ls1bdev/readme.txt → bsp/ls1bdev/readme.md
浏览文件 @ c73c3491
this bsp is based on LS1G DEMO BOARD V1.1 This bsp is based on LS1B DEMO BOARD V1.1
# download script for RT-Thread # download script for RT-Thread
ifaddr syn0 192.168.1.100;load tftp://192.168.1.5/rtthread.elf;g ifaddr syn0 192.168.1.100;load tftp://192.168.1.5/rtthread.elf;g
\ No newline at end of file
bsp/ls1bdev/rtconfig.h
浏览文件 @ c73c3491
#ifndef __RTTHREAD_CFG_H__ #ifndef RT_CONFIG_H__
#define __RTTHREAD_CFG_H__ #define RT_CONFIG_H__
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse"> /* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 10
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
#define RT_USING_OVERFLOW_CHECK
// <bool name="RT_USING_INTERRUPT_INFO" description="Show more interrupt description" default="true" />
#define RT_USING_INTERRUPT_INFO
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" /> /* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK #define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" > #define RT_USING_IDLE_HOOK
// #define RT_USING_TIMER_SOFT #define RT_IDLE_HOOK_LIST_SIZE 4
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" /> #define IDLE_THREAD_STACK_SIZE 256
#define RT_TIMER_THREAD_PRIO 4 #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" /> #define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512 #define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" /> #define RT_DEBUG
#define RT_TIMER_TICK_PER_SECOND 10
// </section> /* Inter-Thread communication */
// <section name="IPC" description="Inter-Thread communication" default="always" >
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
#define RT_USING_SEMAPHORE #define RT_USING_SEMAPHORE
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
#define RT_USING_MUTEX #define RT_USING_MUTEX
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
#define RT_USING_EVENT #define RT_USING_EVENT
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
#define RT_USING_MAILBOX #define RT_USING_MAILBOX
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
#define RT_USING_MESSAGEQUEUE #define RT_USING_MESSAGEQUEUE
// </section>
// <section name="MM" description="Memory Management" default="always" > /* Memory Management */
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
#define RT_USING_MEMPOOL #define RT_USING_MEMPOOL
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
#define RT_USING_MEMHEAP
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
#define RT_USING_HEAP
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
#define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" /> #define RT_USING_HEAP
// #define RT_USING_SLAB
// </section>
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" > /* Kernel Device Object */
#define RT_USING_DEVICE
// <bool name="RT_USING_UART" description="Using UART" default="true" />
#define RT_USING_UART
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" > #define RT_USING_DEVICE
#define RT_USING_CONSOLE #define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" /> #define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart"
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" /> #define RT_VER_NUM 0x40002
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </section> /* RT-Thread Components */
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
#define RT_USING_COMPONENTS_INIT #define RT_USING_COMPONENTS_INIT
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" > #define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH #define RT_USING_FINSH
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" /> #define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB #define FINSH_USING_SYMTAB
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION #define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" /> #define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_THREAD_STACK_SIZE 4096
// </section> #define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
// <section name="RT_USING_LIBC" description="C Runtime library setting" default="true" >
#define RT_USING_LIBC #define RT_USING_LIBC
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" /> #define RT_USING_POSIX
#define RT_USING_PTHREADS
// </section> /* Network */
// <section name="RT_USING_DFS" description="Device file system" default="true" > /* Socket abstraction layer */
// #define RT_USING_DFS
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// #define DFS_USING_WORKDIR /* Network interface device */
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" /> /* light weight TCP/IP stack */
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT /* AT commands */
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item> /* VBUS(Virtual Software BUS) */
// </integer>
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" /> /* Utilities */
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2 /* RT-Thread MIPS CPU */
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
// #define RT_USING_DFS_UFFS
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" /> /* RT-Thread online packages */
// #define RT_USING_DFS_DEVFS
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" /> /* IoT - internet of things */
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/" /* Wi-Fi */
// </section>
/* Marvell WiFi */
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
// #define RT_USING_LWIP
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" /> /* Wiced WiFi */
#define RT_LWIP_ICMP
// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
// #define RT_LWIP_IGMP /* IoT Cloud */
// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
#define RT_LWIP_UDP
// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" /> /* security packages */
#define RT_LWIP_TCP
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS /* language packages */
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" /> /* multimedia packages */
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF 2048 /* tools packages */
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" /> /* system packages */
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP /* peripheral libraries and drivers */
// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
#define RT_LWIP_TCP_SEG_NUM 4
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" /> /* miscellaneous packages */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 /* samples: kernel and components samples */
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 #define SOC_LS1B
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" /> #define RT_USING_UART0
#define RT_LWIP_ETHTHREAD_PRIORITY 14 #define RT_UART_RX_BUFFER_SIZE 64
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
// </section>
// <section name="RT_USING_MODULE" description="Application module" default="true" >
// #define RT_USING_MODULE
// </section>
// <section name="RT_USING_RTGUI" description="RTGUI, a graphic user interface" default="true" >
// #define RT_USING_RTGUI
// <integer name="RTGUI_NAME_MAX" description="Maximal size of RTGUI object name length" default="16" />
#define RTGUI_NAME_MAX 16
// <bool name="RTGUI_USING_FONT16" description="Support 16 weight font" default="true" />
#define RTGUI_USING_FONT16
// <bool name="RTGUI_USING_FONT12" description="Support 12 weight font" default="true" />
#define RTGUI_USING_FONT12
// <bool name="RTGUI_USING_FONTHZ" description="Support Chinese font" default="true" />
#define RTGUI_USING_FONTHZ
// <bool name="RTGUI_USING_DFS_FILERW" description="Using DFS as file interface " default="true" />
#define RTGUI_USING_DFS_FILERW
// <bool name="RTGUI_USING_HZ_FILE" description="Using font file as Chinese font" default="false" />
// #define RTGUI_USING_HZ_FILE
// <bool name="RTGUI_USING_HZ_BMP" description="Using Chinese bitmap font" default="true" />
#define RTGUI_USING_HZ_BMP
// <bool name="RTGUI_USING_SMALL_SIZE" description="Using small size in RTGUI" default="false" />
#define RTGUI_USING_SMALL_SIZE
// <bool name="RTGUI_USING_MOUSE_CURSOR" description="Using mouse cursor in RTGUI" default="false" />
// #define RTGUI_USING_MOUSE_CURSOR
// <bool name="RTGUI_IMAGE_XPM" description="Using xpm image in RTGUI" default="true" />
#define RTGUI_IMAGE_XPM
// <bool name="RTGUI_IMAGE_JPEG" description="Using jpeg image in RTGUI" default="true" />
// #define RTGUI_IMAGE_JPEG
// <bool name="RTGUI_IMAGE_PNG" description="Using png image in RTGUI" default="true" />
// #define RTGUI_IMAGE_PNG
// <bool name="RTGUI_IMAGE_BMP" description="Using bmp image in RTGUI" default="true" />
#define RTGUI_IMAGE_BMP
// </section>
// </RDTConfigurator>
#endif #endif
bsp/ls1bdev/rtconfig.py
浏览文件 @ c73c3491
...@@ -2,7 +2,7 @@ import os ...@@ -2,7 +2,7 @@ import os
# CPU options # CPU options
ARCH='mips' ARCH='mips'
CPU ='loongson_1b' CPU ='gs232'
# toolchains options # toolchains options
CROSS_TOOL = 'gcc' CROSS_TOOL = 'gcc'
...@@ -12,7 +12,8 @@ if os.getenv('RTT_CC'): ...@@ -12,7 +12,8 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc': if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc' PLATFORM = 'gcc'
EXEC_PATH = r'C:\Program Files\CodeSourcery\Sourcery G++ Lite For MIPS ELF\bin' EXEC_PATH = "/opt/mips-2016.05/bin"
# EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
else: else:
print('================ERROR============================') print('================ERROR============================')
print('Not support %s yet!' % CROSS_TOOL) print('Not support %s yet!' % CROSS_TOOL)
...@@ -37,7 +38,7 @@ READELF = PREFIX + 'readelf' ...@@ -37,7 +38,7 @@ READELF = PREFIX + 'readelf'
DEVICE = ' -mips32' DEVICE = ' -mips32'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer' CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8' AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds' LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'
CPATH = '' CPATH = ''
......
bsp/ls1cdev/Kconfig
浏览文件 @ c73c3491
...@@ -9,108 +9,118 @@ config RTT_DIR ...@@ -9,108 +9,118 @@ config RTT_DIR
string string
option env="RTT_ROOT" option env="RTT_ROOT"
default "../.." default "../.."
config PKGS_DIR config PKGS_DIR
string string
option env="PKGS_ROOT" option env="PKGS_ROOT"
default "packages" default "packages"
source "$RTT_DIR/Kconfig" source "$RTT_DIR/Kconfig"
source "$RTT_DIR/libcpu/mips/common/Kconfig"
source "$PKGS_DIR/Kconfig" source "$PKGS_DIR/Kconfig"
config SOC_1C300 config SOC_1C300
bool bool
select RT_USING_COMPONENTS_INIT select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN select RT_USING_USER_MAIN
default y default y
choice
prompt "Board Type"
config RT_LS1C_OPENLOONGSON
bool "OpenLoongson Board"
config RT_LS1C_BAICAIBOARD
bool "Baicai Board"
endchoice
config RT_USING_SELF_BOOT config RT_USING_SELF_BOOT
bool "Enable RT-Thread run without bootloader" bool "Enable RT-Thread run without bootloader"
default n default n
if RT_USING_SELF_BOOT
config RT_SELF_BOOT_DEBUG
bool "Debug self boot code"
default n
endif
if RT_USING_SERIAL if RT_USING_SERIAL
config RT_USING_UART2 config RT_USING_UART2
bool "Using RT_USING_UART2" bool "Using RT_USING_UART2"
default y default y
config RT_USING_UART1 config RT_USING_UART1
bool "Using RT_USING_UART1" bool "Using RT_USING_UART1"
default y default y
config RT_USING_UART3 config RT_USING_UART3
bool "Using RT_USING_UART3" bool "Using RT_USING_UART3"
default n default n
config RT_UART_RX_BUFFER_SIZE config RT_UART_RX_BUFFER_SIZE
int "The rx buffer size" int "The rx buffer size"
default 64 if RT_USING_SERIAL default 64 if RT_USING_SERIAL
default 64 default 64
endif endif
config RT_USING_GMAC_INT_MODE config RT_USING_GMAC_INT_MODE
bool "Using RT_USING_GMAC_INT_MODE" bool "Using RT_USING_GMAC_INT_MODE"
default y default y
config RT_USING_FPU
bool "Using RT_USING_FPU"
default y
config RT_USING_SPI0 config RT_USING_SPI0
bool "Enable SPI0" bool "Enable SPI0"
select RT_USING_SPI select RT_USING_SPI
default y default y
config RT_USING_SPI1 config RT_USING_SPI1
bool "Enable SPI1" bool "Enable SPI1"
select RT_USING_SPI select RT_USING_SPI
default y default y
if RT_USING_I2C if RT_USING_I2C
config RT_USING_I2C1 config RT_USING_I2C1
bool "Enable I2C1" bool "Enable I2C1"
default y default y
config RT_USING_I2C2 config RT_USING_I2C2
bool "Enable I2C2" bool "Enable I2C2"
default y default y
endif endif
config USING_BXCAN0 config USING_BXCAN0
bool "Enable CAN0" bool "Enable CAN0"
select RT_USING_CAN select RT_USING_CAN
default y default y
config USING_BXCAN1 config USING_BXCAN1
bool "Enable CAN1" bool "Enable CAN1"
select RT_USING_CAN select RT_USING_CAN
default y default y
if RT_USING_CAN if RT_USING_CAN
config RT_CAN_USING_HDR config RT_CAN_USING_HDR
bool "Using RT_CAN_USING_HDR" bool "Using RT_CAN_USING_HDR"
select RT_USING_CAN select RT_USING_CAN
default y default y
endif endif
choice choice
prompt "Touch format" prompt "Touch format"
default NO_TOUCH default NO_TOUCH
config NO_TOUCH config NO_TOUCH
bool "with no touch" bool "with no touch"
if RT_USING_RTGUI if RT_USING_RTGUI
config XPT2046_USING_TOUCH config XPT2046_USING_TOUCH
bool "with XPT2046 touch" bool "with XPT2046 touch"
endif endif
config TINA_USING_TOUCH config TINA_USING_TOUCH
bool "with TINA touch" bool "with TINA touch"
endchoice endchoice
if RT_USING_RTC if RT_USING_RTC
config RT_RTC_NAME config RT_RTC_NAME
string "RT_RTC_NAME" string "RT_RTC_NAME"
default "RTC" default "RTC"
endif endif
\ No newline at end of file
bsp/ls1cdev/SConstruct
浏览文件 @ c73c3491
...@@ -16,10 +16,10 @@ rtconfig.AFLAGS += ' -I' + str(Dir('#')) ...@@ -16,10 +16,10 @@ rtconfig.AFLAGS += ' -I' + str(Dir('#'))
DefaultEnvironment(tools=[]) DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'], env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc', AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH) env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT') Export('RTT_ROOT')
...@@ -29,9 +29,9 @@ Export('rtconfig') ...@@ -29,9 +29,9 @@ Export('rtconfig')
objs = PrepareBuilding(env, RTT_ROOT) objs = PrepareBuilding(env, RTT_ROOT)
if GetDepend('RT_USING_SELF_BOOT'): if GetDepend('RT_USING_SELF_BOOT'):
rtconfig.LFLAGS += " -Ttext 0x80010000" rtconfig.LFLAGS += " -Ttext 0x80000000"
else: else:
rtconfig.LFLAGS += " -Ttext 0x80200000" rtconfig.LFLAGS += " -Ttext 0x80200000"
env.Replace(LINKFLAGS = rtconfig.LFLAGS) env.Replace(LINKFLAGS = rtconfig.LFLAGS)
if GetDepend('RT_USING_FPU'): if GetDepend('RT_USING_FPU'):
...@@ -39,9 +39,9 @@ if GetDepend('RT_USING_FPU'): ...@@ -39,9 +39,9 @@ if GetDepend('RT_USING_FPU'):
env['ASFLAGS'] = env['ASFLAGS'].replace('-msoft-float', '-mhard-float') env['ASFLAGS'] = env['ASFLAGS'].replace('-msoft-float', '-mhard-float')
env['CXXFLAGS'] = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float') env['CXXFLAGS'] = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float')
env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float') env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float')
if GetDepend('RT_USING_RTGUI'): if GetDepend('RT_USING_RTGUI'):
objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0) objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
# make a building # make a building
DoBuilding(TARGET, objs) DoBuilding(TARGET, objs)
bsp/ls1cdev/drivers/SConscript
浏览文件 @ c73c3491
from building import * from building import *
cwd = GetCurrentDir() cwd = GetCurrentDir()
src = Glob('*.c') src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd] CPPPATH = [cwd]
......
bsp/ls1cdev/drivers/board.c
浏览文件 @ c73c3491
...@@ -8,74 +8,20 @@ ...@@ -8,74 +8,20 @@
* 2010-06-25 Bernard first version * 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B * 2011-08-08 lgnq modified for Loongson LS1B
* 2015-07-06 chinesebear modified for Loongson LS1C * 2015-07-06 chinesebear modified for Loongson LS1C
* 2019-12-04 Jiaxun Yang Adapt new generic MIPS code
*/ */
#include <rtthread.h> #include <rtthread.h>
#include <rthw.h> #include <rthw.h>
#include <mips.h>
#include "board.h" #include "board.h"
#include "drv_uart.h" #include "drv_uart.h"
#include "ls1c.h" #include "ls1c.h"
#define A_K0BASE 0x80000000
extern unsigned char __bss_end; extern unsigned char __bss_end;
#define RT_HW_HEAP_END (0x80000000 + MEM_SIZE)
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
extern void rt_hw_cache_init(void);
extern void invalidate_writeback_dcache_all(void);
extern void invalidate_icache_all(void);
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
}
/**
* init hardware FPU
*/
void rt_hw_fpu_init(void)
{
rt_uint32_t c0_status = 0;
rt_uint32_t c1_status = 0;
// 使能协处理器1--FPU
c0_status = read_c0_status();
c0_status |= (ST0_CU1 | ST0_FR);
write_c0_status(c0_status);
// 配置FPU
c1_status = read_c1_status();
c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); // set FS, FO, FN
c1_status &= ~(FPU_CSR_ALL_E); // disable exception
c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; // set RN
write_c1_status(c1_status);
return ;
}
/** /**
...@@ -83,35 +29,24 @@ void rt_hw_fpu_init(void) ...@@ -83,35 +29,24 @@ void rt_hw_fpu_init(void)
*/ */
void rt_hw_board_init(void) void rt_hw_board_init(void)
{ {
/* init cache */ /* init hardware interrupt */
rt_hw_cache_init(); rt_hw_exception_init();
/* init hardware interrupt */ /* init hardware interrupt */
rt_hw_interrupt_init(); rt_hw_interrupt_init();
/* clear bev */
write_c0_status(read_c0_status()&(~(1<<22)));
/* copy vector */
rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80);
rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80);
rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80);
invalidate_writeback_dcache_all();
invalidate_icache_all();
#ifdef RT_USING_HEAP #ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END); rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif #endif
#ifdef RT_USING_SERIAL #ifdef RT_USING_SERIAL
/* init hardware UART device */ /* init hardware UART device */
rt_hw_uart_init(); rt_hw_uart_init();
#endif #endif
#ifdef RT_USING_CONSOLE #ifdef RT_USING_CONSOLE
/* set console device */ /* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME); rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif #endif
/* init operating system timer */ /* init operating system timer */
rt_hw_timer_init(); rt_hw_timer_init();
......
bsp/ls1cdev/drivers/board.h
浏览文件 @ c73c3491
...@@ -8,15 +8,55 @@ ...@@ -8,15 +8,55 @@
* 2010-06-25 Bernard first version * 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B * 2011-08-08 lgnq modified for Loongson LS1B
* 2015-07-06 chinesebear modified for Loongson LS1C * 2015-07-06 chinesebear modified for Loongson LS1C
* 2019-12-04 Jiaxun Yang Add board config defines
*/ */
#ifndef __BOARD_H__ #ifndef __BOARD_H__
#define __BOARD_H__ #define __BOARD_H__
#include <rtconfig.h>
#ifndef __ASSEMBLY__
void rt_hw_board_init(void); void rt_hw_board_init(void);
#endif
/*
* SDRAM config
*
* Take IS42S16400 SDRAM chip as a example
* The specfication is
* Size 8MB
* WIDTH: 16 bits
* COL WIDTH: 8 bits, so we should take the 8 power of 2, it's 256
* ROW WIDTH: 12 bits, so we take the 12 power of 2, it's 4K
*
* Please reference macro SD_PARA0 and SDRAM registers intruduction
* in user's manual to edit the SDRAM config.
*/
#if defined(RT_LS1C_BAICAIBOARD)
/* 8MByte IS42S16400 appeared in bacai_board V1.x V2.x */
#define MEM_SIZE (0x800000)
#define SDRAM_WIDTH (WIDTH_16)
#define SDRAM_COL (COL_256)
#define SDRAM_ROW (ROW_4K)
#elif defined(RT_LS1C_OPENLOONGSON)
/* 32MByte appeared in SmartLoong board */
#define MEM_SIZE (0x2000000)
#define SDRAM_WIDTH (WIDTH_16)
#define SDRAM_COL (COL_512)
#define SDRAM_ROW (ROW_8K)
#else
#error Unknown Board
#endif
/* Early Debug config */
#define EARLY_DEBUG /* UART2 serial print debug in early stage */
#define EARLY_DEBUG_BAUD (115200)
/* 32M SDRAM */ /* Clock config */
#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
#define CPU_HZ (252 * 1000000) #define CPU_HZ (252 * 1000000)
#define PLL_MULT (0x54) /* When external clock is 24Mhz PLL=504Mhz */
#define SDRAM_DIV (0) /* SDRAM is CPU divided by 2*/
#define CPU_DIV (2) /* CPU clock is PLL divided by 2 */
#endif #endif
bsp/ls1cdev/drivers/drv_uart.h
浏览文件 @ c73c3491
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#define __DRV_UART_H__ #define __DRV_UART_H__
#include "ls1c.h" #include "ls1c.h"
#include <rthw.h>
#define DEV_CLK 252000000 // 252MHz #define DEV_CLK 252000000 // 252MHz
#define UART_BAUDRATE 115200 #define UART_BAUDRATE 115200
...@@ -31,43 +32,43 @@ ...@@ -31,43 +32,43 @@
#define UART11_BASE 0xBFE4Cb00 #define UART11_BASE 0xBFE4Cb00
/* UART registers */ /* UART registers */
#define UART_DAT(base) __REG8(base + 0x00) #define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) __REG8(base + 0x01) #define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) __REG8(base + 0x02) #define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) __REG8(base + 0x02) #define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) __REG8(base + 0x03) #define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) __REG8(base + 0x04) #define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) __REG8(base + 0x05) #define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) __REG8(base + 0x06) #define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) __REG8(base + 0x00) #define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) __REG8(base + 0x01) #define UART_MSB(base) HWREG8(base + 0x01)
/* UART0 registers */ /* UART0 registers */
#define UART0_DAT __REG8(UART0_BASE + 0x00) #define UART0_DAT HWREG8(UART0_BASE + 0x00)
#define UART0_IER __REG8(UART0_BASE + 0x01) #define UART0_IER HWREG8(UART0_BASE + 0x01)
#define UART0_IIR __REG8(UART0_BASE + 0x02) #define UART0_IIR HWREG8(UART0_BASE + 0x02)
#define UART0_FCR __REG8(UART0_BASE + 0x02) #define UART0_FCR HWREG8(UART0_BASE + 0x02)
#define UART0_LCR __REG8(UART0_BASE + 0x03) #define UART0_LCR HWREG8(UART0_BASE + 0x03)
#define UART0_MCR __REG8(UART0_BASE + 0x04) #define UART0_MCR HWREG8(UART0_BASE + 0x04)
#define UART0_LSR __REG8(UART0_BASE + 0x05) #define UART0_LSR HWREG8(UART0_BASE + 0x05)
#define UART0_MSR __REG8(UART0_BASE + 0x06) #define UART0_MSR HWREG8(UART0_BASE + 0x06)
#define UART0_LSB __REG8(UART0_BASE + 0x00) #define UART0_LSB HWREG8(UART0_BASE + 0x00)
#define UART0_MSB __REG8(UART0_BASE + 0x01) #define UART0_MSB HWREG8(UART0_BASE + 0x01)
/* UART1 registers */ /* UART1 registers */
#define UART1_DAT __REG8(UART1_BASE + 0x00) #define UART1_DAT HWREG8(UART1_BASE + 0x00)
#define UART1_IER __REG8(UART1_BASE + 0x01) #define UART1_IER HWREG8(UART1_BASE + 0x01)
#define UART1_IIR __REG8(UART1_BASE + 0x02) #define UART1_IIR HWREG8(UART1_BASE + 0x02)
#define UART1_FCR __REG8(UART1_BASE + 0x02) #define UART1_FCR HWREG8(UART1_BASE + 0x02)
#define UART1_LCR __REG8(UART1_BASE + 0x03) #define UART1_LCR HWREG8(UART1_BASE + 0x03)
#define UART1_MCR __REG8(UART1_BASE + 0x04) #define UART1_MCR HWREG8(UART1_BASE + 0x04)
#define UART1_LSR __REG8(UART1_BASE + 0x05) #define UART1_LSR HWREG8(UART1_BASE + 0x05)
#define UART1_MSR __REG8(UART1_BASE + 0x06) #define UART1_MSR HWREG8(UART1_BASE + 0x06)
#define UART1_LSB __REG8(UART1_BASE + 0x00) #define UART1_LSB HWREG8(UART1_BASE + 0x00)
#define UART1_MSB __REG8(UART1_BASE + 0x01) #define UART1_MSB HWREG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */ /* UART interrupt enable register value */
#define UARTIER_IME (1 << 3) #define UARTIER_IME (1 << 3)
......
bsp/ls1cdev/drivers/net/synopGMAC_plat.h
浏览文件 @ c73c3491
...@@ -39,14 +39,6 @@ ...@@ -39,14 +39,6 @@
typedef int bool; typedef int bool;
//typedef unsigned long dma_addr_t; //typedef unsigned long dma_addr_t;
//sw
/* write/read MMIO register */
#define writeb(val, addr) (*(volatile u8*)(addr) = (val))
#define writew(val, addr) (*(volatile u16*)(addr) = (val))
#define writel(val, addr) (*(volatile u32*)(addr) = (val))
#define readb(addr) (*(volatile u8*)(addr))
#define readw(addr) (*(volatile u16*)(addr))
#define readl(addr) (*(volatile u32*)(addr))
#define KUSEG_ADDR 0x0 #define KUSEG_ADDR 0x0
......
bsp/ls1cdev/drivers/selfboot.h 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __RT_LS1C_SELFBOOT_H
#define __RT_LS1C_SELFBOOT_H
/* SDRAM PARAM macro */
#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
/* SDRAM ROW */
#define ROW_1K 0x7
#define ROW_2K 0x0
#define ROW_4K 0x1
#define ROW_8K 0x2
#define ROW_16K 0x3
/* SDRAM COL */
#define COL_256 0x7
#define COL_512 0x0
#define COL_1K 0x1
#define COL_2K 0x2
#define COL_4K 0x3
/* SDRAM WIDTH */
#define WIDTH_8 0x0
#define WIDTH_16 0x1
#define WIDTH_32 0x2
#define TRCD 3
#define TCL 3
#define TRP 3
#define TRFC 8
#define TRAS 6
#define TREF 0x818
#define TWR 2
#define DEF_SEL 0x1
#define DEF_SEL_N 0x0
#define HANG_UP 0x1
#define HANG_UP_N 0x0
#define CFG_VALID 0x1
#include "board.h"
#define SD_PARA0 (0x7f<<25 | \
(TRAS << 21) | \
(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
SDRAM_ROW)
#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define LS1C_CBUS_FIRST1 0xBFE011C4
#define LS1C_UART2_BASE 0xBFE48000
/* UART register offset*/
#define LS1C_UART_DAT_OFFSET (0)
#define LS1C_UART_IER_OFFSET (1)
#define LS1C_UART_IIR_OFFSET (2)
#define LS1C_UART_FCR_OFFSET (2)
#define LS1C_UART_LCR_OFFSET (3)
#define LS1C_UART_MCR_OFFSET (4)
#define LS1C_UART_LSR_OFFSET (5)
#define LS1C_UART_MSR_OFFSET (6)
#define LS1C_UART_LSB_OFFSET (0)
#define LS1C_UART_MSB_OFFSET (1)
/* interrupt enable register */
#define IER_IRxE 0x1
#define IER_ITxE 0x2
#define IER_ILE 0x4
#define IER_IME 0x8
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
/* External clock frequency */
#define AHB_CLK (24000000)
#define APB_CLK (AHB_CLK)
/* START_FREQ register bits */
#define M_PLL_SHIFT (8)
#define M_PLL (0xff << M_PLL_SHIFT)
#define FRAC_N_SHIFT (16)
#define FRAC_N (0xff << FRAC_N_SHIFT)
#define DIV_SDRAM_SHIFT (0)
#define DIV_SDRAM (0x3 << DIV_SDRAM_SHIFT)
/* CLK_DIV_PARAM register bits */
#define DIV_PIX_EN (0x1 << 31)
#define DIV_PIX (0x7f << 24)
#define DIV_CAM_EN (0x1 << 23)
#define DIV_CAM (0x7f << 16)
#define DIV_CPU_EN (0x1 << 15)
#define DIV_CPU (0x7f << 8)
#define DIV_PIX_VALID (0x1 << 5)
#define DIV_PIX_SEL (0x1 << 4)
#define DIV_CAM_VALID (0x1 << 3)
#define DIV_CAM_SEL (0x1 << 2)
#define DIV_CPU_VALID (0x1 << 1)
#define DIV_CPU_SEL (0x1 << 0)
#define DIV_PIX_SHIFT (24)
#define DIV_CAM_SHIFT (16)
#define DIV_CPU_SHIFT (8)
#endif
bsp/ls1cdev/drivers/selfboot_gcc.S 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Origin Authors: Loongson Technology Corporation Limited,
* caogos <1207280597@qq.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>,
*
* Also thanks to Liu Shiwei <liushiwei@gmail.com> and other Loongson
* Community developers.
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#include <rtconfig.h>
#ifdef RT_USING_SELF_BOOT
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
#include "selfboot.h"
#include "ls1c.h"
#include "cache.h"
/*
* Register usage:
*
* s0 link versus load offset, used to relocate absolute adresses.
* s1 free
* s2 memory size
* s3 free
* s4 free
* s5 dbg
* s6 sdCfg
* s7 rasave
* s8 free
*/
#define tmpsize s1
#define msize s2
#define bonito s4
#define dbg s5
#define sdCfg s6
/* Macros */
#ifdef RT_SELF_BOOT_DEBUG
#define PRINTSTR(str) \
.pushsection .selfboot_data; .align 4; 98: .asciz str; .popsection; la a0, 98b; bal stringserial; nop
#else
#define PRINTSTR(x)
#endif
#define DELAY(count) \
li v0, count; \
99: \
bnez v0, 99b;\
addiu v0, -1
.section ".selfboot", "ax"
.set noreorder
.set mips32
.globl _start
.extern start
_start:
/* NMI/Reset vector starts here*/
mtc0 zero, CP0_STATUS /* set cp0 status register to zero */
mtc0 zero, CP0_CAUSE /* set cp0 cause register to zero */
li t0, ST0_BEV /* set exception vector to in flash location */
mtc0 t0, CP0_STATUS
/* Speed up SPI reading */
li t0, 0xbfe80000 /* load SPI0 controler base address to t0 */
li t1, 0x17 /* load "div 4, fast_read + burst_en + memory_en double I/O" to
* to t0 for write, not all the flash chips support this mode */
sb t1, 0x4(t0) /* set sfc_param register */
li t1, 0x05
sb t1, 0x6(t0) /* set sfc_timing register */
bal locate /* branch out of vector and get current address to ra */
nop
/* in-flash exception vectors start here */
/* save the exception types to a0 and print out PANIC message in exc_common */
#define EXC_TLB_REFILL 0x0
#define EXC_CACHE_ERR 0x1
#define EXC_GEN 0x2
#define EXC_INT 0x3
.org 0x200 /* 0xbfc00200 TLB_REFILL exception */
li a0, EXC_TLB_REFILL
b exc_common
nop
.org 0x300 /* 0xbfc00300 Cache Error exception */
li a0, EXC_CACHE_ERR
b exc_common
nop
.org 0x380 /* 0xbfc00300 General exception */
li a0,EXC_GEN
b exc_common
nop
.org 0x400 /* 0xbfc00400 Interrupt exception */
li a0, EXC_INT
b exc_common
nop
1: /* impossible to reach here, so make a dead loop */
b 1b
nop
exc_common: /* try one cause and pass to next */
li s1, EXC_TLB_REFILL
bne a0, s1, 1f
nop
PRINTSTR("\r\nEARLY_PANIC: Exception TLB Refill")
b print_cause
nop
1:
li s1, EXC_CACHE_ERR
bne a0, s1, 1f
nop
PRINTSTR("\r\nEARLY_PANIC: CACHE Error: ")
mfc0 a0, CP0_CACHEERR
bal hexserial
nop
b print_cause
nop
1:
li s1, EXC_GEN
bne a0, s1, 1f
nop
PRINTSTR("\r\nEARLY_PANIC: General Exception")
b print_cause
nop
1:
li s1, EXC_INT
bne a0, s1, print_cause /* if all exceptions in a0 not reached,
* print_cause directly*/
nop
PRINTSTR("\r\nEARLY_PANIC: Interrupt Exception")
print_cause:
PRINTSTR("\r\nCAUSE=")
mfc0 a0, CP0_CAUSE
bal hexserial
nop
PRINTSTR("\r\nSTATUS=")
mfc0 a0, CP0_STATUS
bal hexserial
nop
PRINTSTR("\r\nERRORPC=")
mfc0 a0, CP0_ERROREPC
bal hexserial
nop
PRINTSTR("\r\nEPC=")
mfc0 a0, CP0_EPC
bal hexserial
nop
PRINTSTR("\r\nBADADDR=")
mfc0 a0, CP0_BADVADDR
bal hexserial
nop
PRINTSTR("\r\nEARLY: LOOP! Noting to do")
1: /* Make a dead loop here, wait user to reset the MCU */
b 1b
nop
/* locate here, continue the start progress */
locate:
/* fix the absolute address by ra */
la s0, start /* s0 = start */
subu s0, ra, s0 /* s0 = ra - s0 */
and s0, 0xffff0000 /* s0 = s0 & 0xffff0000 */
li t0, 0xbfe78030 /* load PLL/SDRAM freq config register base to t0 */
li t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV) /* Set PLL
* MULT and PLL DIV */
li t3, (0x00008003 | (CPU_DIV << 8)) /* set CPU DEV */
li t1, 0x2
sw t1, 0x4(t0) /* disable CPU_DIV_VALID firstly for adjustment */
sw t2, 0x0(t0) /* write START_FREQ */
sw t3, 0x4(t0) /* write CLK_DIV_PARAM */
/* start to initialize debug uart port */
la v0, LS1C_UART2_BASE /* load UART2 base to v0, only UART2 can be debug port */
1:
li v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4 /* clear Rx,Tx FIFO
* declear 4 bit int trigger */
sb v1, LS1C_UART_FCR_OFFSET(v0) /* write FCR (FIFO control register) */
li v1, CFCR_DLAB /* reach freq div register */
sb v1, LS1C_UART_LCR_OFFSET(v0) /* write LCR (Line control register)*/
/* Set UART2 reuse with GPIO36,37*/
li a0, LS1C_CBUS_FIRST1 /* load CBUS_FIRST1 offset to a0 */
lw a1, 0x10(a0) /* load value from CBUS_SECOND1 to a1 */
ori a1, 0x30 /* a1 |= 0x30, GPIO36,37 as secondary function */
sw a1, 0x10(a0) /* write back modified CBUS_SECOND1 from a1 */
/* Caculate PLL and bit rate */
li a0, 0xbfe78030 /* load START_FREQ register address to a0 */
lw a1, 0(a0) /* load value from START_FREQ to a1*/
srl a1, 8 /* a1 >>= 8 */
andi a1, 0xff /* a1 &= 0xff, as a1=PLL_MULT */
li a2, APB_CLK /* a2 = APB_CLK = 24Mhz (External Clock Freq) */
srl a2, 2 /* a2 = a2 >> 2 = APB_CLK/4 */
multu a1, a2 /* hilo = a1 * a2 = PLL_MULT * APB_CLK /4 */
mflo v1 /* v1 = lo. put low 32 bit of a1 * a2 to v1 as PLL freq */
/* Determine if we need to devide the clock */
lw a1, 4(a0) /* load value frm CLK_DIV_PARAM to a1 */
andi a2, a1, DIV_CPU_SEL /* a2 = a1 & DIV_CPU_SEL, if CPU_SEL=1, devide the clock,
* if CPU_SEL=0, bypass the clock */
bnez a2, 1f /* if (a2 != 0), branch to next tag 1 */
nop
li v1, APB_CLK /* v1 = APB_CLK */
b 3f
nop
1: /* Determine if the CPU_DIV is valid*/
andi a2, a1, DIV_CPU_EN /* a2 = a1 & DIV_CPU_EN */
bnez a2, 2f /* if (a2 != 0), branch to next tag 2 */
nop
srl v1, 1 /* v1 >>= 1, so v1 = APB_CLK/4 * PLL_MULT/2 */
b 3f
nop
2: /* caculate CPU freq */
andi a1, DIV_CPU /* a1 &= DIV_CPU */
srl a1, DIV_CPU_SHIFT /* a1 >>= DIV_CPU_SHIFT */
divu v1, a1 /* lo = v1/a1, hi = v1 % a1 */
mflo v1 /* v1 = lo, CPU Freq */
3:
li a1, (16 * EARLY_DEBUG_BAUD) /* a1 = 16 * BIT RATE */
divu v1, v1, a1 /* v1 = v1 / a1 */
srl v1, 1 /* v1 >>= 1 */
sb v1, LS1C_UART_LSB_OFFSET(v0) /* write 8bit low into LSB */
srl v1, 8 /* v1 >>= 8 */
sb v1, LS1C_UART_MSB_OFFSET(v0) /* write 8bit low into MSB */
li v1, CFCR_8BITS /* 8n1, no check */
sb v1, LS1C_UART_LCR_OFFSET(v0) /* write to LCR (Line Control Register) */
#ifdef EARLY_DEBUG_UART_FLOW_CTRL
li v1, MCR_DTR|MCR_RTS /* valid DTR and RTS */
sb v1, LS1C_UART_MCR_OFFSET(v0) /* write to MCR (MODEM Control Register) */
#endif
li v1, 0x0 /* disable all the interruptions */
sb v1, LS1C_UART_IER_OFFSET(v0) /* write to IER (Interruptions Enable Registers) */
PRINTSTR("\r\INFO: Loongson 1C300 Starting :) \r\n")
/* disable all GPIOs for conflict functions */
li a0,0xbfd00000
sw zero,0x10c0(a0) /* disable GPIO 0-31 */
sw zero,0x10c4(a0) /* disable GPIO 32-63 */
sw zero,0x10c8(a0) /* disable GPIO 64-95 */
sw zero,0x10cc(a0)
li t0, 0xffffffff
sw t0, 0x10d0(a0)
sw t0, 0x10d4(a0)
sw t0, 0x10d8(a0)
sw t0, 0x10dc(a0)
sw t0, 0x10f0(a0)
sw t0, 0x10f4(a0)
sw t0, 0x10f8(a0)
sw t0, 0x10fc(a0)
PRINTSTR("\r\INFO: All GPIOs are disabled\r\n")
/* SDRAM initialize starts here */
li msize, MEM_SIZE
#ifdef EJTAG_SEL_AS_SDRAM_CS1
li a0, 0xbfd011c0
lw a1, 0x40(a0)
ori a1, 0x01
sw a1, 0x40(a0)
PRINTSTR("\r\INFO: EJTAG_SEL PIN as SDRAM_CS1\r\n")
#endif
/*
* recommanded by user manual, we should write SD_CONFIG[31:0] first, then
* write SD_CONFIG[63:32]. Repeat writing for three times, valid the config in
* the last time.
*/
/* write first time */
li t1, 0xbfd00410 /* load SD_CONFIG[31:0] address to t1 */
li a1, SD_PARA0 /* get the memory config from macro SD_PARA0 */
sw a1, 0x0(t1) /* write to SD_CONFIG[31:0] */
li a1, SD_PARA1
sw a1, 0x4(t1) /* write to SD_CONFIG[63:32] with offset */
PRINTSTR("\r\INFO: SDRAM Config Pass1\r\n")
/* write second time,the same */
li a1, SD_PARA0
sw a1, 0x0(t1)
li a1, SD_PARA1
sw a1, 0x4(t1)
PRINTSTR("\r\INFO: SDRAM Config Pass2\r\n")
/* write third time, enable controller this time */
li a1, SD_PARA0
sw a1, 0x0(t1)
li a1, SD_PARA1_EN /* enable it */
sw a1, 0x4(t1)
PRINTSTR("\r\INFO: SDRAM initialize compeleted\r\n")
/* initialize cache */
bal cache_init /* branch to cache_init */
nop
/* enable cache */
mfc0 a0, CP0_CONFIG /* load cp0 config to a0 */
and a0, a0, ~((1<<12) | 7) /* a0 = a0 & ~((1<<12) | 7) */
or a0, a0, 2 /* a0 |= 2 */
mtc0 a0, CP0_CONFIG /* write back to CP0 config */
/*
* relocate: copy selfboot code to memory in kseg0, fix PC and jump to kseg0.
* in order to speed up the copy progress, we will execute copy code in kseg0
*/
PRINTSTR("\r\INFO: Relocating")
la t0, text_copy_start /* load the adress of start tag to t0 */
move t2, t0
addu t0, s0 /* correct t0 address in rom by s0 */
la t1, text_copy_end
selfboot_copy_loop:
lw v0, (t0) /* copy from memory address in t0 to register v0 */
sw v0, (t2) /* write data in register v0 to memory address t0 */
addiu t0, 0x4 /* t0 moves forward 4 bytes */
addiu t2, 0x4 /* t2 moves forward 4 bytes */
ble t2, t1, selfboot_copy_loop /* if t1 <= t2 loop to continue the copy */
nop
la t0, text_copy_start /* load start address to t0 */
jr t0 /* jump to 122 in kseg0 to start copy code progress */
nop
text_copy_start:
/* Copy code to memory*/
la a0, start /* load address of start symbol to a0 */
addu a1, a0, s0 /* correct a0 to address in flash */
la a2, _edata /* load symbol _edata address to a2 */
subu t1, a2, a0 /* t1 = a2 - a0, the space of text area */
move t0, a0 /* the start address in ram */
move t1, a1 /* the start address in rom */
move t2, a2 /* the end address in rom (symbol _edata) */
/* copy text section */
1:
and t3, t0, 0x0000ffff /* t3 = t0 & 0x0000ffff, get low 16 bit */
bnez t3, 2f /* if t3 != 0, jump to next tag 2 */
nop
2:
lw t3, 0(t1) /* copy 4 bit from memory address t1 to register t3 */
nop
sw t3, 0(t0) /* copy 4 bit from register t3 to memory address in t0 */
addu t0, 4 /* t0 move forward 4 bytes */
addu t1, 4 /* t1 move forward 4 bytes */
bne t2, t0, 1b /* if t2 != t0, branch to last tag 1 to continue copy */
nop
/* copy text section done. */
move a0, msize /* a0 = msize, will be passed to main */
srl a0, 20 /* a0 >>= 20, convert to unit in MB */
/* execute main */
la v0, _rtthread_entry /* load address of function main to v0 */
jalr v0 /* call address in v0, congrats! all low_level things done!
* switch brain out of assembly */
nop
text_copy_end: /* end of self-copy in memory */
loop: /* impossible to reach here, make a dead loop */
b loop
nop
/* functions here */
LEAF(stringserial) /* print out the string in address passed in a0 */
nop
move a2, ra /* save the return address to a2 */
addu a1, a0, s0 /* correct the address in ROM */
lbu a0, 0(a1) /* read the first byte in memory address a1 to a0 */
1:
beqz a0, 2f /* if a0 == 0, jump to next tag 2, empty char */
nop
bal tgt_putchar /* print a char */
addiu a1, 1 /* a1 += 1 move forward to next byte */
b 1b /* branch to the last tag 1, continue */
lbu a0, 0(a1) /* load the next bit from address a1 to a0, in delay solt,
* will be execuated before branch */
2:
j a2 /* return */
nop
END(stringserial)
LEAF(hexserial) /* print out single hex char passed in register a0 */
nop
move a2, ra /* move return address from ra to a2 */
move a1, a0 /* move hex char from register a0 to a1 */
li a3, 7 /* load 7 to a3 */
1:
rol a0, a1, 4 /* rotate left ward shift for 4 bit in a1 to a0 */
move a1, a0
and a0, 0xf
la v0, hexchar
.pushsection .selfboot_data
.align 4
hexchar:
.ascii "0123456789abcdef"
.popsection
.align 4
addu v0, s0
addu v0, a0
bal tgt_putchar
lbu a0, 0(v0)
bnez a3, 1b
addu a3, -1
j a2
nop
END(hexserial)
LEAF(tgt_putchar) /* print out a char in a0 */
la v0, LS1C_UART2_BASE /* load UART register address to a0 */
lbu v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 */
1:
and v1, LSR_TXRDY /* v1 &= LSR_TXRDY determine wether we can send by TFE bit */
beqz v1, 1b /* if (v1 == 0) jump to last 1 tag, waiting until TFE is 1 */
lbu v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 again, in delay solt */
sb a0, LS1C_UART_DAT_OFFSET(v0) /* write a0 into DAT, send out */
j ra /* */
nop
END(tgt_putchar)
LEAF(CPU_SetSR) /* modify SR value, arg 1 = set bits, arg 2 = clear bits. */
mfc0 v0, CP0_STATUS
not v1, a1
and v1, v0
or v1, a0
mtc0 v1, CP0_STATUS
nop
nop
nop
nop
nop
nop
nop
nop
j ra
nop
END(CPU_SetSR)
cache_init:
move t1, ra
####part 2####
cache_detect_4way:
mfc0 t4, CP0_CONFIG,1 /* move CP0 CONFIG to t4 */
lui v0, 0x7 /* v0 = 0x7 << 16 */
and v0, t4, v0 /* v0 = t4 & v0 */
srl t3, v0, 16 /* t3 = v0 >> 16 Icache组相联数 IA */
li t5, 0x800 //32*64
srl v1, t4,22 //v1 = t4 >> 22
andi v1, 7 //Icache每路的组数 64x2^S IS
sll t5, v1 //InstCacheSetSize
sll t5, t3 //t5 InstCacheSize
andi v0, t4, 0x0380
srl t7, v0, 7 //DA
li t6, 0x800 // 32*64
srl v1, t4,13
andi v1, 7 //DS
sll t6, v1 // DataCacheSetSize
sll t6, t7 // t5 DataCacheSize
####part 3####
lui a0, 0x8000 //a0 = 0x8000 << 16
addu a1, $0, t5
addu a2, $0, t6
cache_init_d2way:
/* a0=0x80000000, a1=icache_size, a2=dcache_size */
/* a3, v0 and v1 used as local registers */
mtc0 $0, CP0_TAGHI
addu v0, $0, a0 /* v0 = 0 + a0 */
addu v1, a0, a2 /* v1 = a0 + a2 */
1: slt a3, v0, v1 /* a3 = v0 < v1 ? 1 : 0 */
beq a3, $0, 1f /* if (a3 == 0) goto 1f */
nop
mtc0 $0, CP0_TAGLO
cache Index_Store_Tag_D, 0x0(v0) /* 1 way */
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_i2way:
addu v0, $0, a0
addu v1, a0, a1
1:
slt a3, v0, v1
beq a3, $0, 1f
nop
cache Index_Invalidate_I, 0x0(v0) /* 1 way */
4:
beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_d2way:
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
cache Index_Writeback_Inv_D, 0x0(v0) /* 1 way */
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_init_finish:
jr t1
nop
#endif
bsp/ls1cdev/ls1c_ram.lds
浏览文件 @ c73c3491
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
* 2010-05-17 swkyer first version * 2010-05-17 swkyer first version
* 2010-09-04 bernard move the beginning entry to 0x80200000 * 2010-09-04 bernard move the beginning entry to 0x80200000
* 2018-05-12 zhuangwei use -Ttext * 2018-05-12 zhuangwei use -Ttext
* 2019-12-04 Jiaxun Yang Adapt new memory layout
*/ */
OUTPUT_ARCH(mips) OUTPUT_ARCH(mips)
...@@ -20,13 +21,19 @@ GROUP(-lgcc -lc) ...@@ -20,13 +21,19 @@ GROUP(-lgcc -lc)
ENTRY(_start) ENTRY(_start)
SECTIONS SECTIONS
{ {
. = 0x80000000 ;
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
start = ABSOLUTE(.); start = ABSOLUTE(.);
*(.start); *(.selfboot);
*(.selfboot_data);
. = ALIGN(4);
__selfboot_end = .;
. = ALIGN(0x1000);
__ebase_entry = .;
KEEP(*(.exc_vectors))
__ebase_end = .;
*(.start);
*(.text) *(.text)
*(.text.*) *(.text.*)
*(.rodata) *(.rodata)
...@@ -74,6 +81,15 @@ SECTIONS ...@@ -74,6 +81,15 @@ SECTIONS
*(.sdata) *(.sdata)
*(.sdata.*) *(.sdata.*)
} }
_edata = .;
.stack :
{
. = ALIGN(8);
_system_stack_start = .;
. = . + 0x400; /* 1kb system stack */
_system_stack = .;
}
.sbss : .sbss :
{ {
......
bsp/ls1cdev/rtconfig.h
浏览文件 @ c73c3491
...@@ -8,28 +8,16 @@ ...@@ -8,28 +8,16 @@
#define RT_NAME_MAX 10 #define RT_NAME_MAX 10
#define RT_ALIGN_SIZE 8 #define RT_ALIGN_SIZE 8
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32 #define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000 #define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK #define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK #define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4 #define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024 #define IDLE_THREAD_STACK_SIZE 1024
/* RT_USING_TIMER_SOFT is not set */
#define RT_DEBUG #define RT_DEBUG
#define RT_DEBUG_COLOR #define RT_DEBUG_COLOR
/* RT_DEBUG_INIT_CONFIG is not set */
/* RT_DEBUG_THREAD_CONFIG is not set */
/* RT_DEBUG_SCHEDULER_CONFIG is not set */
/* RT_DEBUG_IPC_CONFIG is not set */
/* RT_DEBUG_TIMER_CONFIG is not set */
/* RT_DEBUG_IRQ_CONFIG is not set */
/* RT_DEBUG_MEM_CONFIG is not set */
/* RT_DEBUG_SLAB_CONFIG is not set */
/* RT_DEBUG_MEMHEAP_CONFIG is not set */
/* RT_DEBUG_MODULE_CONFIG is not set */
/* Inter-Thread communication */ /* Inter-Thread communication */
...@@ -38,27 +26,22 @@ ...@@ -38,27 +26,22 @@
#define RT_USING_EVENT #define RT_USING_EVENT
#define RT_USING_MAILBOX #define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE #define RT_USING_MESSAGEQUEUE
/* RT_USING_SIGNALS is not set */
/* Memory Management */ /* Memory Management */
#define RT_USING_MEMPOOL #define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP #define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
#define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM
/* RT_USING_SLAB is not set */
/* RT_USING_MEMHEAP_AS_HEAP is not set */
/* RT_USING_MEMTRACE is not set */
#define RT_USING_HEAP #define RT_USING_HEAP
/* Kernel Device Object */ /* Kernel Device Object */
#define RT_USING_DEVICE #define RT_USING_DEVICE
/* RT_USING_DEVICE_OPS is not set */
#define RT_USING_INTERRUPT_INFO #define RT_USING_INTERRUPT_INFO
#define RT_USING_CONSOLE #define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart2" #define RT_CONSOLE_DEVICE_NAME "uart2"
#define RT_VER_NUM 0x40002
/* RT-Thread Components */ /* RT-Thread Components */
...@@ -69,7 +52,6 @@ ...@@ -69,7 +52,6 @@
/* C++ features */ /* C++ features */
/* RT_USING_CPLUSPLUS is not set */
/* Command shell */ /* Command shell */
...@@ -79,14 +61,11 @@ ...@@ -79,14 +61,11 @@
#define FINSH_HISTORY_LINES 5 #define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB #define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION #define FINSH_USING_DESCRIPTION
/* FINSH_ECHO_DISABLE_DEFAULT is not set */
#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80 #define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH #define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT #define FINSH_USING_MSH_DEFAULT
/* FINSH_USING_MSH_ONLY is not set */
#define FINSH_ARG_MAX 10 #define FINSH_ARG_MAX 10
/* Device virtual file system */ /* Device virtual file system */
...@@ -96,29 +75,6 @@ ...@@ -96,29 +75,6 @@
#define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 4 #define DFS_FD_MAX 4
/* RT_USING_DFS_MNTTABLE is not set */
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 936
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_0
/* RT_DFS_ELM_USE_LFN_1 is not set */
/* RT_DFS_ELM_USE_LFN_2 is not set */
/* RT_DFS_ELM_USE_LFN_3 is not set */
#define RT_DFS_ELM_USE_LFN 0
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* RT_DFS_ELM_USE_ERASE is not set */
#define RT_DFS_ELM_REENTRANT
/* RT_USING_DFS_DEVFS is not set */
/* RT_USING_DFS_ROMFS is not set */
/* RT_USING_DFS_RAMFS is not set */
/* RT_USING_DFS_UFFS is not set */
/* RT_USING_DFS_JFFS2 is not set */
/* RT_USING_DFS_NFS is not set */
/* Device Drivers */ /* Device Drivers */
...@@ -126,200 +82,95 @@ ...@@ -126,200 +82,95 @@
#define RT_PIPE_BUFSZ 512 #define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL #define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA #define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN #define RT_USING_CAN
/* RT_CAN_USING_HDR is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_CPUTIME is not set */
#define RT_USING_I2C #define RT_USING_I2C
#define RT_USING_I2C_BITOPS #define RT_USING_I2C_BITOPS
#define RT_USING_PIN #define RT_USING_PIN
/* RT_USING_PWM is not set */
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
/* RT_USING_MTD is not set */
/* RT_USING_PM is not set */
/* RT_USING_RTC is not set */
/* RT_USING_SDIO is not set */
#define RT_USING_SPI #define RT_USING_SPI
#define RT_USING_SPI_MSD #define RT_USING_SPI_MSD
/* RT_USING_SFUD is not set */
/* RT_USING_W25QXX is not set */
/* RT_USING_GD is not set */
/* RT_USING_ENC28J60 is not set */
/* RT_USING_SPI_WIFI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_AUDIO is not set */
/* Using WiFi */
/* RT_USING_WIFI is not set */
/* Using USB */ /* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */ /* POSIX layer and C standard library */
#define RT_USING_LIBC #define RT_USING_LIBC
#define RT_USING_PTHREADS #define RT_USING_PTHREADS
/* RT_USING_POSIX is not set */ #define PTHREAD_NUM_MAX 8
/* RT_USING_MODULE is not set */
/* Network */ /* Network */
/* Socket abstraction layer */ /* Socket abstraction layer */
/* RT_USING_SAL is not set */
/* Network interface device */
/* light weight TCP/IP stack */ /* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP141
/* RT_USING_LWIP202 is not set */
/* RT_USING_LWIP210 is not set */
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
/* RT_LWIP_SNMP is not set */
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.254"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
/* RT_LWIP_RAW is not set */
/* RT_LWIP_PPP is not set */
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 4096
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
/* LWIP_NO_RX_THREAD is not set */
/* LWIP_NO_TX_THREAD is not set */
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
/* RT_LWIP_REASSEMBLY_FRAG is not set */
#define LWIP_NETIF_STATUS_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
/* RT_LWIP_NETIF_LOOPBACK is not set */
#define LWIP_NETIF_LOOPBACK 0
/* RT_LWIP_STATS is not set */
/* RT_LWIP_DEBUG is not set */
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* AT commands */ /* AT commands */
/* RT_USING_AT is not set */
/* LWIP_USING_DHCPD is not set */
/* VBUS(Virtual Software BUS) */ /* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */ /* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* RT_USING_ULOG is not set */
/* RT-Thread online packages */ /* RT-Thread MIPS CPU */
/* system packages */
/* RT-Thread GUI Engine */
/* PKG_USING_GUIENGINE is not set */ /* RT-Thread online packages */
/* PKG_USING_LWEXT4 is not set */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* IoT - internet of things */ /* IoT - internet of things */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_LJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* PKG_USING_GAGENT_CLOUD is not set */
/* Wi-Fi */ /* Wi-Fi */
/* Marvell WiFi */ /* Marvell WiFi */
/* PKG_USING_WLANMARVELL is not set */
/* Wiced WiFi */ /* Wiced WiFi */
/* PKG_USING_WLAN_WICED is not set */
/* PKG_USING_COAP is not set */ /* IoT Cloud */
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
/* security packages */ /* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* PKG_USING_TINYCRYPT is not set */
/* language packages */ /* language packages */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */ /* multimedia packages */
/* PKG_USING_OPENMV is not set */
/* tools packages */ /* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYLOGGER is not set */ /* system packages */
/* PKG_USING_SYSTEMVIEW is not set */
/* PKG_USING_IPERF is not set */
/* peripheral libraries and drivers */
/* miscellaneous packages */ /* miscellaneous packages */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* PKG_USING_QUICKLZ is not set */
/* PKG_USING_MULTIBUTTON is not set */
/* example package: hello */ /* samples: kernel and components samples */
/* PKG_USING_HELLO is not set */ #define SOC_1C300
/* RT_USING_SELF_BOOT is not set */ #define RT_LS1C_BAICAIBOARD
#define RT_USING_SELF_BOOT
#define RT_SELF_BOOT_DEBUG
#define RT_USING_UART2 #define RT_USING_UART2
#define RT_USING_UART1
#define RT_UART_RX_BUFFER_SIZE 64 #define RT_UART_RX_BUFFER_SIZE 64
#define RT_USING_GMAC_INT_MODE #define RT_USING_GMAC_INT_MODE
/* RT_USING_FPU is not set */
/* RT_USING_SPI0 is not set */
/* RT_USING_SPI1 is not set */
#define RT_USING_I2C1 #define RT_USING_I2C1
#define RT_USING_I2C2 #define RT_USING_I2C2
#define USING_BXCAN0 #define NO_TOUCH
#define USING_BXCAN1
#endif #endif
bsp/ls1cdev/rtconfig.py
浏览文件 @ c73c3491
...@@ -2,7 +2,7 @@ import os ...@@ -2,7 +2,7 @@ import os
# CPU options # CPU options
ARCH='mips' ARCH='mips'
CPU ='loongson_1c' CPU ='gs232'
# toolchains options # toolchains options
CROSS_TOOL = 'gcc' CROSS_TOOL = 'gcc'
...@@ -12,8 +12,8 @@ if os.getenv('RTT_CC'): ...@@ -12,8 +12,8 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc': if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc' PLATFORM = 'gcc'
# EXEC_PATH = "/opt/mips-2015.05/bin" EXEC_PATH = "/opt/mips-2016.05/bin"
EXEC_PATH = r'D:\mgc\embedded\codebench\bin' # EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
else: else:
print('================ERROR===========================') print('================ERROR===========================')
print('Not support %s yet!' % CROSS_TOOL) print('Not support %s yet!' % CROSS_TOOL)
...@@ -41,7 +41,7 @@ READELF = PREFIX + 'readelf' ...@@ -41,7 +41,7 @@ READELF = PREFIX + 'readelf'
DEVICE = ' -mips32 -msoft-float -mfp32' DEVICE = ' -mips32 -msoft-float -mfp32'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer' CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8' AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1c_ram.lds' LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1c_ram.lds'
CPATH = '' CPATH = ''
......
bsp/mipssim/Kconfig 0 → 100644
浏览文件 @ c73c3491
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/libcpu/mips/common/Kconfig"
source "$PKGS_DIR/Kconfig"
config MIPSSIM
bool
select ARCH_MIPS
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select RT_USING_DEVICE
default y
bsp/mipssim/README.md 0 → 100644
浏览文件 @ c73c3491
MIPSSIM 板级支持包
---
## 1. 简介
本BSP用于在MIPSSIM或QEMU的MIPSSIM Machine模拟器中运行RT-Thread。
使用mips-sde-elf工具链编译。
在QEMU中使用如下命令运行：
```
qemu-system-mipsel -M mipssim -cpu P5600 -nographic -kernel ./rtthread.elf
```
MIPSSIM拥有一个8250串口和一个MIPSNET网卡外设，本BSP目前仅实现了串口。
\ No newline at end of file
bsp/mipssim/SConscript 0 → 100644
浏览文件 @ c73c3491
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/mipssim/SConstruct 0 → 100644
浏览文件 @ c73c3491
import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
rtconfig.AFLAGS += ' -I' + str(Dir('#'))
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
env.Replace(LINKFLAGS = rtconfig.LFLAGS)
if GetDepend('RT_USING_FPU'):
env['CCFLAGS'] = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')
env['ASFLAGS'] = env['ASFLAGS'].replace('-msoft-float', '-mhard-float')
env['CXXFLAGS'] = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float')
env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float')
# make a building
DoBuilding(TARGET, objs)
bsp/mipssim/applications/SConscript 0 → 100644
浏览文件 @ c73c3491
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''])
Return('group')
bsp/mipssim/applications/main.c 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-10 zhuangwei first version
*/
#include <rtthread.h>
int main(int argc, char** argv)
{
return 0;
}
bsp/mipssim/drivers/SConscript 0 → 100644
浏览文件 @ c73c3491
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/mipssim/drivers/board.c 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
/**
* @addtogroup mipssim
*/
/*@{*/
#include <rtthread.h>
#include <rthw.h>
#include "mips_regs.h"
#include "exception.h"
#include "drv_uart.h"
#define CPU_HZ (100 * 1000 * 1000)
#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
extern unsigned char __bss_end;
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
mips_unmask_cpu_irq(7);
}
/**
* Board level initialization
*/
void rt_hw_board_init(void)
{
rt_hw_exception_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
#ifdef RT_USING_FPU
/* init hardware fpu */
rt_hw_fpu_init();
#endif
#ifdef RT_USING_SERIAL
/* init hardware UART device */
rt_hw_uart_init();
/* set console device */
rt_console_set_device("uart");
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
/* init operating system timer */
rt_hw_timer_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
rt_kprintf("Current SR: 0x%08x\n", read_c0_status());
}
/*@}*/
bsp/mipssim/drivers/cpuinit_gcc.S 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
.section ".text", "ax"
.set noreorder
.globl rt_cpu_early_init
rt_cpu_early_init:
mfc0 t0, CP0_CONFIG
ori t0, 3
mtc0 t0, CP0_CONFIG
ehb
jr ra
\ No newline at end of file
bsp/mipssim/drivers/drv_uart.c 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
/**
* @addtogroup mipssim
*/
/*@{*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "drv_uart.h"
#define TRUE 1
#define FALSE 0
struct rt_uart_mipssim
{
void *base;
rt_uint32_t IRQ;
};
static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct rt_uart_mipssim *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
UART_IER(uart_dev->base) = 0; /* clear interrupt */
UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart_dev->base) = 0x3;
UART_MCR(uart_dev->base) = 0x3;
UART_LSR(uart_dev->base) = 0x60;
UART_MSR(uart_dev->base) = 0xb0;
return RT_EOK;
}
static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct rt_uart_mipssim *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */
rt_hw_interrupt_mask(uart_dev->IRQ);
break;
case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */
rt_hw_interrupt_umask(uart_dev->IRQ);
UART_IER(uart_dev->base) |= (IER_IRxE|IER_ILE);
break;
default:
break;
}
return RT_EOK;
}
static rt_bool_t uart_is_transmit_empty(struct rt_uart_mipssim *uart_dev)
{
unsigned char status = UART_LSR(uart_dev->base);
if (status & (UARTLSR_TE | UARTLSR_TFE))
{
return TRUE;
}
else
{
return FALSE;
}
}
static int mipssim_uart_putc(struct rt_serial_device *serial, char c)
{
struct rt_uart_mipssim *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
while (FALSE == uart_is_transmit_empty(uart_dev))
;
UART_DAT(uart_dev->base) = c;
return 1;
}
static int mipssim_uart_getc(struct rt_serial_device *serial)
{
struct rt_uart_mipssim *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
if (LSR_RXRDY & UART_LSR(uart_dev->base))
{
return UART_DAT(uart_dev->base);
}
return -1;
}
/* UART interrupt handler */
static void uart_irq_handler(int vector, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device *)param;
struct rt_uart_mipssim *uart_dev = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
unsigned char iir = UART_IIR(uart_dev->base);
/* Find out interrupt reason */
if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
{
rt_interrupt_enter();
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
rt_interrupt_leave();
}
}
static const struct rt_uart_ops mipssim_uart_ops =
{
mipssim_uart_configure,
mipssim_uart_control,
mipssim_uart_putc,
mipssim_uart_getc,
};
struct rt_uart_mipssim uart_dev0 =
{
(void *)UART0_BASE,
4,
};
struct rt_serial_device serial;
void rt_hw_uart_init(void)
{
struct rt_uart_mipssim *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
uart = &uart_dev0;
serial.ops = &mipssim_uart_ops;
serial.config = config;
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
/* register UART device */
rt_hw_serial_register(&serial,
"uart",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
}
/*@}*/
bsp/mipssim/drivers/drv_uart.h 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef _MIPSSIM_DRV_UART_H__
#define _MIPSSIM_DRV_UART_H__
#include "mipssim.h"
#include <rthw.h>
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* interrupt enable register */
#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
#define IER_IME 0x8 /* Modem状态中断使能 */
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
// 线路控制寄存器
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
#endif
\ No newline at end of file
bsp/mipssim/drivers/interrupt.c 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
/**
* @addtogroup mipssim
*/
/*@{*/
#include <rtthread.h>
#include <rthw.h>
#include <exception.h>
#define MAX_INTR 32
static struct rt_irq_desc irq_handle_table[MAX_INTR];
static void rt_hw_interrupt_handler(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_uint32_t idx;
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (idx = 0; idx < MAX_INTR; idx ++)
{
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
}
}
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector >= 0 && vector < MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
return old_handler;
}
void rt_hw_timer_handler(void);
void rt_do_mips_cpu_irq(rt_uint32_t ip)
{
void *param;
rt_isr_handler_t irq_func;
if (ip == 7) {
rt_hw_timer_handler();
} else {
irq_func = irq_handle_table[ip].handler;
param = irq_handle_table[ip].param;
/* do interrupt */
irq_func(ip, param);
}
}
void rt_hw_interrupt_umask(int irq)
{
mips_unmask_cpu_irq(irq);
}
void rt_hw_interrupt_mask(int irq)
{
mips_mask_cpu_irq(irq);
}
/*@}*/
bsp/mipssim/drivers/mipssim.h 0 → 100644
浏览文件 @ c73c3491
#ifndef _MIPSSIM_H__
#define _MIPSSIM_H__
#include <mips.h>
#define ISA_MMIO_BASE 0x1fd00000
#define UART0_ISA_OFF 0x3f8
#define UART0_BASE KSEG1ADDR(ISA_MMIO_BASE + UART0_ISA_OFF)
void rt_hw_timer_handler(void);
void rt_hw_uart_init(void);
#endif
\ No newline at end of file
bsp/mipssim/mipssim_ram.lds 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
OUTPUT_ARCH(mips)
GROUP(-lgcc -lc)
ENTRY(_start)
SECTIONS
{
. = 0x80000000 ;
.text :
{
__ebase_entry = .;
KEEP(*(.exc_vectors))
__ebase_end = .;
start = .;
*(.start);
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.rodata1)
*(.rodata1.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(4);
}
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
.stack :
{
. = ALIGN(8);
_system_stack_start = .;
. = . + 0x1000;
_system_stack = .;
}
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
}
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/mipssim/rtconfig.h 0 → 100644
浏览文件 @ c73c3491
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 2048
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40002
#define ARCH_MIPS
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
/* RT-Thread MIPS CPU */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
#define MIPSSIM
#endif
bsp/mipssim/rtconfig.py 0 → 100644
浏览文件 @ c73c3491
import os
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = '../..'
# CPU options
ARCH='mips'
CPU ='common'
# toolchains options
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = "/opt/mips-2016.05/bin"
# EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
else:
print('================ERROR===========================')
print('Not support %s yet!' % CROSS_TOOL)
print('=================================================')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
PREFIX = 'mips-sde-elf-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -mips32r2 -msoft-float -mfp32'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds'
CXXFLAGS = CFLAGS
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
libcpu/mips/SConscript
浏览文件 @ c73c3491
...@@ -13,6 +13,7 @@ list = os.listdir(cwd) ...@@ -13,6 +13,7 @@ list = os.listdir(cwd)
group = group + SConscript(os.path.join('common', 'SConscript')) group = group + SConscript(os.path.join('common', 'SConscript'))
# cpu porting code files # cpu porting code files
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) if rtconfig.CPU != 'common':
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
Return('group') Return('group')
libcpu/mips/common/Kconfig 0 → 100644
浏览文件 @ c73c3491
menu "RT-Thread MIPS CPU"
config RT_USING_FPU
bool "Using Float Point Unit"
default n
help
Using Float Point Unit in code.
endmenu
libcpu/mips/common/asm.h
浏览文件 @ c73c3491
/* /*
* This file is subject to the terms and conditions of the GNU General Public * Assembly Macros For MIPS
* License. See the file "COPYING" in the main directory of this archive
* for more details.
* *
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
* *
* Some useful macros for MIPS assembler code * SPDX-License-Identifier: Apache-2.0
* *
* Some of the routines below contain useless nops that will be optimized * Change Logs:
* away by gas in -O mode. These nops are however required to fill delay * Date Author Notes
* slots in noreorder mode. * 2019-12-04 Jiaxun Yang Initial version
*/ */
#ifndef __ASM_H__ #ifndef __ASM_H__
#define __ASM_H__ #define __ASM_H__
...@@ -21,94 +18,94 @@ ...@@ -21,94 +18,94 @@
* LEAF - declare leaf routine * LEAF - declare leaf routine
*/ */
#define LEAF(symbol) \ #define LEAF(symbol) \
.globl symbol; \ .globl symbol; \
.align 2; \ .align 2; \
.type symbol,@function; \ .type symbol,@function; \
.ent symbol,0; \ .ent symbol,0; \
symbol: .frame sp,0,ra symbol: .frame sp,0,ra
/* /*
* NESTED - declare nested routine entry point * NESTED - declare nested routine entry point
*/ */
#define NESTED(symbol, framesize, rpc) \ #define NESTED(symbol, framesize, rpc) \
.globl symbol; \ .globl symbol; \
.align 2; \ .align 2; \
.type symbol,@function; \ .type symbol,@function; \
.ent symbol,0; \ .ent symbol,0; \
symbol: .frame sp, framesize, rpc symbol: .frame sp, framesize, rpc
/* /*
* END - mark end of function * END - mark end of function
*/ */
#define END(function) \ #define END(function) \
.end function; \ .end function; \
.size function,.-function .size function,.-function
/* /*
* EXPORT - export definition of symbol * EXPORT - export definition of symbol
*/ */
#define EXPORT(symbol) \ #define EXPORT(symbol) \
.globl symbol; \ .globl symbol; \
symbol: symbol:
/* /*
* FEXPORT - export definition of a function symbol * FEXPORT - export definition of a function symbol
*/ */
#define FEXPORT(symbol) \ #define FEXPORT(symbol) \
.globl symbol; \ .globl symbol; \
.type symbol,@function; \ .type symbol,@function; \
symbol: symbol:
/* /*
* Global data declaration with size. * Global data declaration with size.
*/ */
#define EXPORTS(name,sz) \ #define EXPORTS(name,sz) \
.globl name; \ .globl name; \
.type name,@object; \ .type name,@object; \
.size name,sz; \ .size name,sz; \
name: name:
/* /*
* Weak data declaration with size. * Weak data declaration with size.
*/ */
#define WEXPORT(name,sz) \ #define WEXPORT(name,sz) \
.weakext name; \ .weakext name; \
.type name,@object; \ .type name,@object; \
.size name,sz; \ .size name,sz; \
name: name:
/* /*
* Global data reference with size. * Global data reference with size.
*/ */
#define IMPORT(name, size) \ #define IMPORT(name, size) \
.extern name,size .extern name,size
/* /*
* Global zeroed data. * Global zeroed data.
*/ */
#define BSS(name,size) \ #define BSS(name,size) \
.type name,@object; \ .type name,@object; \
.comm name,size .comm name,size
/* /*
* Local zeroed data. * Local zeroed data.
*/ */
#define LBSS(name,size) \ #define LBSS(name,size) \
.lcomm name,size .lcomm name,size
/* /*
* ABS - export absolute symbol * ABS - export absolute symbol
*/ */
#define ABS(symbol,value) \ #define ABS(symbol,value) \
.globl symbol; \ .globl symbol; \
symbol = value symbol = value
#define TEXT(msg) \ #define TEXT(msg) \
.pushsection .data; \ .pushsection .data; \
8: .asciiz msg; \ 8: .asciiz msg; \
.popsection; .popsection;
#define ENTRY(name) \ #define ENTRY(name) \
......
libcpu/mips/loongson_1b/context_gcc.S → libcpu/mips/common/context_gcc.S
浏览文件 @ c73c3491
...@@ -5,42 +5,19 @@ ...@@ -5,42 +5,19 @@
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2010-05-17 swkyer first version * 2019-12-04 Jiaxun Yang Initial version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
* 2019-07-19 Zhou Yanjie clean up code
*/ */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#define __ASSEMBLY__ #define __ASSEMBLY__
#endif #endif
#include "../common/mips_def.h" #include "mips_regs.h"
#include "../common/stackframe.h" #include "stackframe.h"
.section ".text", "ax" .section ".text", "ax"
.set noreorder .set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/* /*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from * a0 --> from
...@@ -63,7 +40,6 @@ rt_hw_context_switch: ...@@ -63,7 +40,6 @@ rt_hw_context_switch:
.globl rt_hw_context_switch_to .globl rt_hw_context_switch_to
rt_hw_context_switch_to: rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */ lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET RESTORE_ALL_AND_RET
/* /*
...@@ -94,57 +70,54 @@ _reswitch: ...@@ -94,57 +70,54 @@ _reswitch:
*/ */
.globl rt_interrupt_enter .globl rt_interrupt_enter
.globl rt_interrupt_leave .globl rt_interrupt_leave
.globl rt_general_exc_dispatch
.globl mips_irq_handle .globl mips_irq_handle
mips_irq_handle: mips_irq_handle:
SAVE_ALL SAVE_ALL
mfc0 t0, CP0_CAUSE /* let k0 keep the current context sp */
and t1, t0, 0xff move k0, sp
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */ /* switch to kernel stack */
li sp, SYSTEM_STACK la sp, _system_stack
jal rt_interrupt_enter jal rt_interrupt_enter
nop nop
jal rt_interrupt_dispatch /* Get Old SP from k0 as paremeter in a0 */
move a0, k0
jal rt_general_exc_dispatch
nop nop
jal rt_interrupt_leave jal rt_interrupt_leave
nop nop
/* switch sp back to thread's context */ /* switch sp back to thread context */
move sp, k0 move sp, k0
/* /*
* if rt_thread_switch_interrupt_flag set, jump to * if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return * rt_hw_context_switch_interrupt_do and do not return
*/ */
la k0, rt_thread_switch_interrupt_flag la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0) lw k1, 0(k0)
beqz k1, spurious_interrupt beqz k1, spurious_interrupt
nop nop
sw zero, 0(k0) /* clear flag */ sw zero, 0(k0) /* clear flag */
nop nop
/* /*
* switch to the new thread * switch to the new thread
*/ */
la k0, rt_interrupt_from_thread la k0, rt_interrupt_from_thread
lw k1, 0(k0) lw k1, 0(k0)
nop nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */ sw sp, 0(k1) /* store sp in preempted task TCB */
la k0, rt_interrupt_to_thread la k0, rt_interrupt_to_thread
lw k1, 0(k0) lw k1, 0(k0)
nop nop
lw sp, 0(k1) /* get new task's stack pointer */ lw sp, 0(k1) /* get new task stack pointer */
j spurious_interrupt j spurious_interrupt
nop nop
spurious_interrupt: spurious_interrupt:
RESTORE_ALL_AND_RET RESTORE_ALL_AND_RET
.set reorder .set reorder
libcpu/mips/common/entry_gcc.S 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
#include <rtconfig.h>
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _rtthread_entry
_rtthread_entry:
#ifndef RT_USING_SELF_BOOT
.globl _start
_start:
#endif
la ra, _rtthread_entry
/* disable interrupt */
mtc0 zero, CP0_CAUSE
mtc0 zero, CP0_STATUS # Set CPU to disable interrupt.
ehb
/* setup stack pointer */
la sp, _system_stack
la gp, _gp
bal rt_cpu_early_init
nop
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
libcpu/mips/common/exception.c 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#include <rtthread.h>
#include <rthw.h>
#include "exception.h"
#include "mips_regs.h"
/**
* @addtogroup MIPS
*/
/*@{*/
extern rt_uint32_t __ebase_entry;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
rt_base_t rt_hw_interrupt_disable(void)
{
rt_base_t status = read_c0_status();
clear_c0_status(ST0_IE);
return status;
}
void rt_hw_interrupt_enable(rt_base_t level)
{
write_c0_status(level);
}
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 31
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void mips_dump_regs(struct pt_regs *regs) {
int i, j;
for(i = 0; i < 32 / 4; i++) {
for(j = 0; j < 4; j++) {
int reg = 4 * i + j;
rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]);
}
rt_kprintf("\n");
}
}
void tlb_refill_handler(void)
{
rt_kprintf("TLB-Miss Happens, EPC: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("Cache Exception Happens, EPC: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(struct pt_regs *regs)
{
rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc());
mips_dump_regs(regs);
rt_hw_cpu_shutdown();
}
static void install_default_exception_handler(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
int rt_hw_exception_init(void)
{
rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
write_c0_ebase(ebase);
clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
clear_c0_status(ST0_IM | ST0_IE);
set_c0_status(ST0_CU0);
/* install the default exception handler */
install_default_exception_handler();
return RT_EOK;
}
void rt_general_exc_dispatch(struct pt_regs *regs)
{
rt_uint32_t cause, exccode;
exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
if (exccode == 0) {
rt_uint32_t status, pending;
status = read_c0_status();
pending = (cause & CAUSEF_IP) & (status & ST0_IM);
if (pending & CAUSEF_IP0)
rt_do_mips_cpu_irq(0);
if (pending & CAUSEF_IP1)
rt_do_mips_cpu_irq(1);
if (pending & CAUSEF_IP2)
rt_do_mips_cpu_irq(2);
if (pending & CAUSEF_IP3)
rt_do_mips_cpu_irq(3);
if (pending & CAUSEF_IP4)
rt_do_mips_cpu_irq(4);
if (pending & CAUSEF_IP5)
rt_do_mips_cpu_irq(5);
if (pending & CAUSEF_IP6)
rt_do_mips_cpu_irq(6);
if (pending & CAUSEF_IP7)
rt_do_mips_cpu_irq(7);
} else {
if (sys_exception_handlers[exccode])
sys_exception_handlers[exccode](regs);
}
}
/* Mask means disable the interrupt */
void mips_mask_cpu_irq(rt_uint32_t irq)
{
clear_c0_status(1 << (STATUSB_IP0 + irq));
}
/* Unmask means enable the interrupt */
void mips_unmask_cpu_irq(rt_uint32_t irq)
{
set_c0_status(1 << (STATUSB_IP0 + irq));
}
/*@}*/
libcpu/mips/common/exception.h
浏览文件 @ c73c3491
/* /*
* File : cpu.c * Copyright (c) 2006-2019, RT-Thread Development Team
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
* *
* The license and distribution terms for this file may be * SPDX-License-Identifier: Apache-2.0
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2010-05-17 swkyer first version * 2019-12-04 Jiaxun Yang Initial version
*/ */
#ifndef __EXCEPTION_H__ #ifndef __EXCEPTION_H__
#define __EXCEPTION_H__ #define __EXCEPTION_H__
#include "ptrace.h"
/* #ifndef __ASSEMBLY__
* important register numbers
*/
#define REG_EPC 37
#define REG_FP 72
#define REG_SP 29
/*
* Stack layout for the GDB exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
#define NUMREGS 90
#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
///*
// * Saved floating point registers
// */
//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
//
//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
//
//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
//
///*
// * Again, CP0 registers
// */
//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */
#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */
#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
/*
* This is the same as above, but for the high-level
* part of the INT stub.
*/
typedef struct pt_regs_s
{
/* Saved main processor registers. */
rt_base_t regs[32];
/* Saved special registers. */
rt_base_t cp0_status;
rt_base_t hi;
rt_base_t lo;
rt_base_t cp0_badvaddr;
rt_base_t cp0_cause;
rt_base_t cp0_epc;
} pt_regs_t;
typedef void (* exception_func_t)(pt_regs_t *regs); typedef void (* exception_func_t)(struct pt_regs *regs);
extern int rt_hw_exception_init(void);
extern exception_func_t sys_exception_handlers[]; extern exception_func_t sys_exception_handlers[];
extern void rt_do_mips_cpu_irq(rt_uint32_t ip);
exception_func_t rt_set_except_vector(int n, exception_func_t func); exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void); extern void mips_mask_cpu_irq(rt_uint32_t irq);
extern void mips_unmask_cpu_irq(rt_uint32_t irq);
#endif
#endif /* end of __EXCEPTION_H__ */ #endif /* end of __EXCEPTION_H__ */
libcpu/mips/common/exception_gcc.S 0 → 100644
浏览文件 @ c73c3491
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
.section ".exc_vectors", "ax"
.extern tlb_refill_handler
.extern cache_error_handler
.extern mips_irq_handle
/* 0x0 - TLB refill handler */
.global tlb_refill_exception
.type tlb_refill_exception,@function
ebase_start:
tlb_refill_exception:
b _general_exception_handler
nop
/* 0x100 - Cache error handler */
.org ebase_start + 0x100
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.global general_exception
.type general_exception,@function
.org ebase_start + 0x180
general_exception:
b _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.global irq_exception
.type irq_exception,@function
.org ebase_start + 0x200
irq_exception:
b _general_exception_handler
nop
/* general exception handler */
_general_exception_handler:
.set noreorder
la $k0, mips_irq_handle
jr $k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la $k0, mips_irq_handle
jr $k0
nop
.set reorder
libcpu/mips/common/mips.h
浏览文件 @ c73c3491
...@@ -12,14 +12,12 @@ ...@@ -12,14 +12,12 @@
#define _COMMON_MIPS_H_ #define _COMMON_MIPS_H_
#include "mips_cfg.h" #include "mips_cfg.h"
#include "ptrace.h"
#include "mips_types.h" #include "mips_types.h"
#include "mips_asm.h" #include "asm.h"
#include "mips_def.h"
#include "mips_regs.h" #include "mips_regs.h"
#include "mips_addrspace.h" #include "mips_addrspace.h"
#include "mips_cache.h" #include "mips_cache.h"
#include "mips_context.h" #include "exception.h"
#include "mips_excpt.h"
#endif /* _COMMON_MIPS_H_ */ #endif /* _COMMON_MIPS_H_ */
libcpu/mips/common/mips_addrspace.h
浏览文件 @ c73c3491
/* /*
* File : mips_addrspace.h * Copyright (c) 2006-2019, RT-Thread Development Team
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
* *
* This program is free software; you can redistribute it and/or modify * SPDX-License-Identifier: Apache-2.0
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2016912 Urey the first version * 2019-12-04 Jiaxun Yang Initial version
*/ */
#ifndef _MIPS_ADDRSPACE_H_ #ifndef _MIPS_ADDRSPACE_H_
...@@ -108,11 +94,11 @@ ...@@ -108,11 +94,11 @@
* Memory segments (32bit kernel mode addresses) * Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe. * These are the traditional names used in the 32-bit universe.
*/ */
//#define KUSEGBASE 0x00000000 #define KUSEGBASE 0x00000000
//#define KSEG0BASE 0x80000000 #define KSEG0BASE 0x80000000
//#define KSEG1BASE 0xa0000000 #define KSEG1BASE 0xa0000000
//#define KSEG2BASE 0xc0000000 #define KSEG2BASE 0xc0000000
//#define KSEG3BASE 0xe0000000 #define KSEG3BASE 0xe0000000
#define CKUSEG 0x00000000 #define CKUSEG 0x00000000
#define CKSEG0 0x80000000 #define CKSEG0 0x80000000
...@@ -147,14 +133,6 @@ ...@@ -147,14 +133,6 @@
* Returns the uncached address of a sdram address * Returns the uncached address of a sdram address
*/ */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
/* /*
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
...@@ -162,46 +140,19 @@ ...@@ -162,46 +140,19 @@
* R8000 implements most with its 48-bit physical address space. * R8000 implements most with its 48-bit physical address space.
*/ */
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
#ifndef CONFIG_CPU_R8000
/*
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
* in order to catch bugs in the source code.
*/
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) #define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
#endif
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#endif
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* #define REG8( addr ) (*(volatile u8 *) (addr))
* Change virtual addresses to physical addresses and vv. #define REG16( addr ) (*(volatile u16 *)(addr))
* These are trivial on the 1:1 Linux/MIPS mapping #define REG32( addr ) (*(volatile u32 *)(addr))
*/ #define REG64( addr ) (*(volatile u64 *)(addr))
static inline phys_addr_t virt_to_phys(volatile void * address)
{
#ifndef CONFIG_64BIT
return CPHYSADDR(address);
#else
return XPHYSADDR(address);
#endif #endif
}
static inline void * phys_to_virt(unsigned long address)
{
#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
#else
return (void *)CKSEG0ADDR(address);
#endif
}
#endif
#endif /* _MIPS_ADDRSPACE_H_ */ #endif /* _MIPS_ADDRSPACE_H_ */
libcpu/mips/common/mips_asm.h 已删除 100644 → 0
浏览文件 @ 4e295d00
此差异已折叠。
libcpu/mips/common/mips_cache.c
浏览文件 @ c73c3491
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 201697 Urey the first version * 2016-09-07 Urey the first version
*/ */
#include <rtthread.h> #include <rtthread.h>
......
libcpu/mips/common/mips_cache.h
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...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2016910 Urey the first version * 2016-09-07 Urey the first version
*/ */
#ifndef _MIPS_CACHE_H_ #ifndef _MIPS_CACHE_H_
...@@ -38,11 +38,7 @@ ...@@ -38,11 +38,7 @@
#define INDEX_LOAD_TAG_D 0x05 #define INDEX_LOAD_TAG_D 0x05
#define INDEX_STORE_TAG_I 0x08 #define INDEX_STORE_TAG_I 0x08
#define INDEX_STORE_TAG_D 0x09 #define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
#define HIT_INVALIDATE_I 0x00
#else
#define HIT_INVALIDATE_I 0x10 #define HIT_INVALIDATE_I 0x10
#endif
#define HIT_INVALIDATE_D 0x11 #define HIT_INVALIDATE_D 0x11
#define HIT_WRITEBACK_INV_D 0x15 #define HIT_WRITEBACK_INV_D 0x15
......
libcpu/mips/common/mips_cfg.h
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...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2016Äê9ÔÂ10ÈÕ Urey the first version * 2016-09-07 Urey the first version
*/ */
#ifndef _MIPS_CFG_H_ #ifndef _MIPS_CFG_H_
...@@ -30,12 +30,12 @@ ...@@ -30,12 +30,12 @@
typedef struct mips32_core_cfg typedef struct mips32_core_cfg
{ {
uint16_t icache_line_size; uint16_t icache_line_size;
// uint16_t icache_lines_per_way; uint16_t icache_lines_per_way;
// uint16_t icache_ways; uint16_t icache_ways;
uint16_t icache_size; uint16_t icache_size;
uint16_t dcache_line_size; uint16_t dcache_line_size;
// uint16_t dcache_lines_per_way; uint16_t dcache_lines_per_way;
// uint16_t dcache_ways; uint16_t dcache_ways;
uint16_t dcache_size; uint16_t dcache_size;
uint16_t max_tlb_entries; /* number of tlb entry */ uint16_t max_tlb_entries; /* number of tlb entry */
......
libcpu/mips/common/mips_context.h 已删除 100644 → 0
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libcpu/mips/common/mips_def.h 已删除 100644 → 0
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libcpu/mips/common/mips_excpt.h 已删除 100644 → 0
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/*
* File : mips_excpt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ7ÈÕ Urey the first version
*/
#ifndef _MIPS_EXCPT_H_
#define _MIPS_EXCPT_H_
#include "mips_regs.h"
#ifndef __ASSEMBLY__
typedef void (* exception_func_t)(mips_reg_ctx *regs);
//extern exception_func_t mips_exception_handlers[];
int rt_hw_exception_init(void);
exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void);
#endif /* __ASSEMBLY__ */
#endif /* _MIPS_EXCPT_H_ */
libcpu/mips/common/mips_fpu.h 0 → 100644
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef _MIPS_FPU_H_
#define _MIPS_FPU_H_
#ifndef __ASSEMBLY__
#include <mips_regs.h>
/**
* init hardware FPU
*/
#ifdef RT_USING_FPU
inline void rt_hw_fpu_init(void)
{
rt_uint32_t c0_status = 0;
rt_uint32_t c1_status = 0;
/* Enable CU1 */
c0_status = read_c0_status();
c0_status |= (ST0_CU1 | ST0_FR);
write_c0_status(c0_status);
/* FCSR Configs */
c1_status = read_c1_status();
c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); /* Set FS, FO, FN */
c1_status &= ~(FPU_CSR_ALL_E); /* Disable exception */
c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; /* Set RN */
write_c1_status(c1_status);
return ;
}
#else
inline void rt_hw_fpu_init(void){} /* Do nothing */
#endif
#endif
#endif
libcpu/mips/common/mips_regs.h
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libcpu/mips/common/mips_types.h
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libcpu/mips/common/ptrace.h 0 → 100644
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libcpu/mips/common/stack.c 0 → 100644
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libcpu/mips/common/stackframe.h
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libcpu/mips/gs232/cpuinit_gcc.S 0 → 100644
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
.section ".start", "ax"
.set noreorder
.globl rt_cpu_early_init
rt_cpu_early_init:
jr ra
nop
\ No newline at end of file
libcpu/mips/gs232/cpuport.c 0 → 100644
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libcpu/mips/gs232/gs232.h 0 → 100644
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libcpu/mips/gs232/mipscfg.c 0 → 100644
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libcpu/mips/gs232/timer.c 0 → 100644
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libcpu/mips/loongson_1c/context_gcc.S 已删除 100644 → 0
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libcpu/mips/loongson_1c/cpuport.c 已删除 100644 → 0
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libcpu/mips/loongson_1c/sdram_cfg.h 已删除 100644 → 0
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