提交 bf4a51b5 编写于 作者: armink_ztl's avatar armink_ztl

Update the kernel and components to master version.

上级 94e3f77f
......@@ -25,36 +25,42 @@ env:
- RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='imxrt/imxrt1050-evk' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
# - RTT_BSP='bf533' # no scons
- RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='es32f0334' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
# - RTT_BSP='es32f0654' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
- RTT_BSP='gd32e230k-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='gd32303e-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='imxrt/imxrt1050-evk' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='lpc824' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
- RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc5410x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc54114-lite' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='m16c62p' # m32c
- RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='microblaze' # no scons
- RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='mini4020' # no scons
- RTT_BSP='mm32l07x'
# - RTT_BSP='nios_ii' # no scons
- RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
......@@ -63,25 +69,17 @@ env:
- RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='simulator' # x86
- RTT_BSP='stm32f0x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32l072' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f107' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f10x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f10x-HAL' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f40x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-dofly-M3S' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
......@@ -89,15 +87,27 @@ env:
- RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f446-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f469-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f746-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f10x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f10x-HAL' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
# - RTT_BSP='upd70f3454' # iar
......@@ -107,6 +117,7 @@ env:
- RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
stage: compile
script:
......
......@@ -17,13 +17,13 @@ RT-Thread RTOS like a traditional real-time operating system. The kernel has rea
* Device Driver;
* Component;
* Dyanmic Module
* Dynamic Module
The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features.
The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
The Dyanmic Module, formerly named as User Applicaion (UA) is a dyanmic loaded module or library, it can be compiled standalone without Kernel. Each Dyanmic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
The Dynamic Module, formerly named as User Applicaion (UA) is a dynamic loaded module or library, it can be compiled standalone without Kernel. Each Dynamic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
## Board Support Package ##
......
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */
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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
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if ARCH_ARM_CORTEX_M
menu "ARM CMSIS"
config RT_USING_CMSIS_OS
bool "Using CMSIS RTOS API"
default n
help
Enable CMSIS RTOS API, which is implemented above RT-Thread.
config RT_USING_RTT_CMSIS
bool "Using CMSIS Header files in RT-Thread"
default n
help
Use CMSIS header files in RT-Thread/components/CMSIS. Otherwise, use the
CMSIS header files in BSP.
endmenu
endif
* -------------------------------------------------------------------
* Copyright (C) 2011-2012 ARM Limited. All rights reserved.
*
* Date: 07 March 2012
* Revision: V3.01
*
* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
* Title: Release Note for CMSIS
*
* -------------------------------------------------------------------
NOTE - Open the index.html file to access CMSIS documentation
The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
and reduces time-to-market for new embedded applications.
CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
Any user of the software package is bound to the terms and conditions of the end user license agreement.
You will find the following sub-directories:
Documentation - Contains CMSIS documentation.
DSP_Lib - MDK project files, Examples and source files etc.. to build the
CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
Include - CMSIS Core Support and CMSIS DSP Include Files.
Lib - CMSIS DSP Libraries.
RTOS - CMSIS RTOS API template header file.
SVD - CMSIS SVD Schema files and Conversion Utility.
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('CMSIS_OS', src, depend = ['RT_USING_CMSIS_OS'], CPPPATH = CPPPATH)
Return('group')
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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
......@@ -37,6 +37,4 @@ source "$RTT_DIR/components/vbus/Kconfig"
source "$RTT_DIR/components/utilities/Kconfig"
source "$RTT_DIR/components/CMSIS/Kconfig"
endmenu
......@@ -28,7 +28,7 @@ template<typename T, uint32_t queue_sz>
class Mail {
public:
/** Create and Initialise Mail queue. */
Mail(const char* name = "")
Mail(const char *name = "")
{
rt_mb_init(&mID, name, mPool, queue_sz, RT_IPC_FLAG_FIFO);
}
......
......@@ -21,7 +21,7 @@ namespace rtthread {
class Mutex {
public:
/** Create and Initialize a Mutex object */
Mutex(const char* name = "mutex");
Mutex(const char *name = "mutex");
~Mutex();
/** Wait until a Mutex becomes available.
......
......@@ -68,7 +68,7 @@ public:
private:
struct rt_messagequeue mID;
char mPool[(sizeof(struct rt_messagequeue)+sizeof(T)) * queue_sz];
char mPool[(sizeof(struct rt_messagequeue) + sizeof(T)) * queue_sz];
};
}
......@@ -20,7 +20,7 @@ namespace rtthread
class Thread
{
public:
typedef void (*thread_func_t) (void *param);
typedef void (*thread_func_t)(void *param);
/** Allocate a new thread without starting execution
@param priority initial priority of the thread function. (default: osPriorityNormal).
......@@ -28,14 +28,14 @@ public:
@param stack_pointer pointer to the stack area to be used by this thread (default: NULL).
*/
Thread(rt_uint32_t stack_size = 2048,
rt_uint8_t priority = (RT_THREAD_PRIORITY_MAX * 2)/3,
rt_uint8_t priority = (RT_THREAD_PRIORITY_MAX * 2) / 3,
rt_uint32_t tick = 20,
const char *name = "th");
Thread(void (*entry)(void *p),
void *p = RT_NULL,
rt_uint32_t stack_size = 2048,
rt_uint8_t priority = (RT_THREAD_PRIORITY_MAX * 2)/3,
rt_uint8_t priority = (RT_THREAD_PRIORITY_MAX * 2) / 3,
rt_uint32_t tick = 20,
const char *name = "th");
......
......@@ -26,7 +26,7 @@ void operator delete(void *ptr)
rt_free(ptr);
}
void operator delete[] (void *ptr)
void operator delete[](void *ptr)
{
return rt_free(ptr);
}
......
......@@ -18,7 +18,7 @@ void *operator new(size_t size);
void *operator new[](size_t size);
void operator delete(void * ptr);
void operator delete[] (void *ptr);
void operator delete[](void *ptr);
extern "C" void __cxa_pure_virtual(void);
extern "C" int cplusplus_system_init(void);
......
......@@ -50,11 +50,11 @@ RT_WEAK int cplusplus_system_init(void)
for (; base != lim; base++)
{
PROC *proc = (PROC*)((const char*)base + *base);
PROC *proc = (PROC *)((const char *)base + *base);
(*proc)();
}
#elif defined(__GNUC__)
typedef void(*pfunc) ();
typedef void(*pfunc)();
extern pfunc __ctors_start__[];
extern pfunc __ctors_end__[];
pfunc *p;
......
......@@ -113,6 +113,7 @@ if RT_USING_DFS
config RT_USING_DFS_RAMFS
bool "Enable RAM file system"
select RT_USING_MEMHEAP
default n
config RT_USING_DFS_UFFS
......
......@@ -97,7 +97,7 @@ int dfs_device_fs_close(struct dfs_fd *file)
root_dirent = (struct device_dirent *)file->data;
RT_ASSERT(root_dirent != RT_NULL);
/* release dirent */
rt_free(root_dirent);
return RT_EOK;
......@@ -133,7 +133,7 @@ int dfs_device_fs_open(struct dfs_fd *file)
struct rt_object_information *information;
struct device_dirent *root_dirent;
rt_uint32_t count = 0;
/* lock scheduler */
rt_enter_critical();
......@@ -145,8 +145,8 @@ int dfs_device_fs_open(struct dfs_fd *file)
count ++;
}
root_dirent = (struct device_dirent *)rt_malloc(sizeof(struct device_dirent) +
count * sizeof(rt_device_t));
root_dirent = (struct device_dirent *)rt_malloc(sizeof(struct device_dirent) +
count * sizeof(rt_device_t));
if (root_dirent != RT_NULL)
{
root_dirent->devices = (rt_device_t *)(root_dirent + 1);
......@@ -165,7 +165,7 @@ int dfs_device_fs_open(struct dfs_fd *file)
/* set data */
file->data = root_dirent;
return RT_EOK;
}
......@@ -178,7 +178,7 @@ int dfs_device_fs_open(struct dfs_fd *file)
{
/* use device fops */
file->fops = device->fops;
file->data = (void*)device;
file->data = (void *)device;
/* use fops */
if (file->fops->open)
......@@ -214,7 +214,7 @@ int dfs_device_fs_stat(struct dfs_filesystem *fs, const char *path, struct stat
st->st_dev = 0;
st->st_mode = S_IFREG | S_IRUSR | S_IRGRP | S_IROTH |
S_IWUSR | S_IWGRP | S_IWOTH;
S_IWUSR | S_IWGRP | S_IWOTH;
st->st_mode &= ~S_IFREG;
st->st_mode |= S_IFDIR | S_IXUSR | S_IXGRP | S_IXOTH;
......@@ -233,7 +233,7 @@ int dfs_device_fs_stat(struct dfs_filesystem *fs, const char *path, struct stat
st->st_dev = 0;
st->st_mode = S_IRUSR | S_IRGRP | S_IROTH |
S_IWUSR | S_IWGRP | S_IWOTH;
S_IWUSR | S_IWGRP | S_IWOTH;
if (dev_id->type == RT_Device_Class_Char)
st->st_mode |= S_IFCHR;
......@@ -293,7 +293,7 @@ static int dfs_device_fs_poll(struct dfs_fd *fd, struct rt_pollreq *req)
return mask;
}
static const struct dfs_file_ops _device_fops =
static const struct dfs_file_ops _device_fops =
{
dfs_device_fs_open,
dfs_device_fs_close,
......@@ -306,7 +306,7 @@ static const struct dfs_file_ops _device_fops =
dfs_device_fs_poll,
};
static const struct dfs_filesystem_ops _device_fs =
static const struct dfs_filesystem_ops _device_fs =
{
"devfs",
DFS_FS_FLAG_DEFAULT,
......
......@@ -21,14 +21,14 @@ int dfs_ramfs_mount(struct dfs_filesystem *fs,
unsigned long rwflag,
const void *data)
{
struct dfs_ramfs* ramfs;
struct dfs_ramfs *ramfs;
if (data == NULL)
return -EIO;
ramfs = (struct dfs_ramfs *)data;
fs->data = ramfs;
return RT_EOK;
}
......@@ -48,8 +48,8 @@ int dfs_ramfs_statfs(struct dfs_filesystem *fs, struct statfs *buf)
RT_ASSERT(buf != NULL);
buf->f_bsize = 512;
buf->f_blocks = ramfs->memheap.pool_size/512;
buf->f_bfree = ramfs->memheap.available_size/512;
buf->f_blocks = ramfs->memheap.pool_size / 512;
buf->f_bfree = ramfs->memheap.available_size / 512;
return RT_EOK;
}
......@@ -119,7 +119,7 @@ int dfs_ramfs_write(struct dfs_fd *fd, const void *buf, size_t count)
struct ramfs_dirent *dirent;
struct dfs_ramfs *ramfs;
dirent = (struct ramfs_dirent*)fd->data;
dirent = (struct ramfs_dirent *)fd->data;
RT_ASSERT(dirent != NULL);
ramfs = dirent->fs;
......@@ -260,7 +260,7 @@ int dfs_ramfs_open(struct dfs_fd *file)
file->size = dirent->size;
if (file->flags & O_APPEND)
file->pos = file->size;
else
else
file->pos = 0;
return 0;
......@@ -381,7 +381,7 @@ int dfs_ramfs_rename(struct dfs_filesystem *fs,
return RT_EOK;
}
static const struct dfs_file_ops _ram_fops =
static const struct dfs_file_ops _ram_fops =
{
dfs_ramfs_open,
dfs_ramfs_close,
......@@ -418,7 +418,7 @@ int dfs_ramfs_init(void)
}
INIT_COMPONENT_EXPORT(dfs_ramfs_init);
struct dfs_ramfs* dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size)
struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size)
{
struct dfs_ramfs *ramfs;
rt_uint8_t *data_ptr;
......@@ -435,7 +435,7 @@ struct dfs_ramfs* dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size)
if (result != RT_EOK)
return NULL;
/* detach this memheap object from the system */
rt_object_detach((rt_object_t)&(ramfs->memheap));
rt_object_detach((rt_object_t) & (ramfs->memheap));
/* initialize ramfs object */
ramfs->magic = RAMFS_MAGIC;
......
......@@ -24,7 +24,7 @@ struct ramfs_dirent
struct dfs_ramfs *fs; /* file system ref */
char name[RAMFS_NAME_MAX]; /* dirent name */
rt_uint8_t* data;
rt_uint8_t *data;
rt_size_t size; /* file size */
};
......@@ -41,7 +41,7 @@ struct dfs_ramfs
};
int dfs_ramfs_init(void);
struct dfs_ramfs* dfs_ramfs_create(rt_uint8_t* pool, rt_size_t size);
struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
#endif
......@@ -105,7 +105,7 @@ struct romfs_dirent *dfs_romfs_lookup(struct romfs_dirent *root_dirent, const ch
if (dirent[index].type == ROMFS_DIRENT_DIR)
{
/* enter directory */
dirent = (struct romfs_dirent*)dirent[index].data;
dirent = (struct romfs_dirent *)dirent[index].data;
found = 1;
break;
}
......@@ -226,7 +226,7 @@ int dfs_romfs_stat(struct dfs_filesystem *fs, const char *path, struct stat *st)
st->st_dev = 0;
st->st_mode = S_IFREG | S_IRUSR | S_IRGRP | S_IROTH |
S_IWUSR | S_IWGRP | S_IWOTH;
S_IWUSR | S_IWGRP | S_IWOTH;
if (dirent->type == ROMFS_DIRENT_DIR)
{
......
......@@ -13,8 +13,8 @@
#include <rtthread.h>
#define ROMFS_DIRENT_FILE 0x00
#define ROMFS_DIRENT_DIR 0x01
#define ROMFS_DIRENT_FILE 0x00
#define ROMFS_DIRENT_DIR 0x01
struct romfs_dirent
{
......
......@@ -83,7 +83,7 @@ extern const uffs_FlashOps nand_ops;
extern void uffs_setup_storage(
struct uffs_StorageAttrSt *attr,
struct rt_mtd_nand_device * nand);
struct rt_mtd_nand_device *nand);
extern int dfs_uffs_init(void);
#endif /* DFS_UFFS_H_ */
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此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
此差异已折叠。
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