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体验新版 GitCode,发现更多精彩内容 >>
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bec8b3f5
编写于
4月 23, 2015
作者:
B
Bernard Xiong
浏览文件
操作
浏览文件
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差异文件
Merge pull request #463 from ArdaFu/master
[cpu][sam926] Using MMU to map vector table before init INT controller.
上级
37b3c878
b77a1cde
变更
13
隐藏空白更改
内联
并排
Showing
13 changed file
with
254 addition
and
620 deletion
+254
-620
bsp/at91sam9260/applications/startup.c
bsp/at91sam9260/applications/startup.c
+33
-67
bsp/at91sam9260/drivers/board.c
bsp/at91sam9260/drivers/board.c
+6
-3
bsp/at91sam9260/link_scripts/at91sam9260_ram.icf
bsp/at91sam9260/link_scripts/at91sam9260_ram.icf
+4
-30
bsp/at91sam9260/link_scripts/at91sam9260_ram.scat
bsp/at91sam9260/link_scripts/at91sam9260_ram.scat
+21
-39
bsp/at91sam9260/platform/rt_low_level_gcc.inc
bsp/at91sam9260/platform/rt_low_level_gcc.inc
+0
-2
bsp/at91sam9260/platform/rt_low_level_iar.inc
bsp/at91sam9260/platform/rt_low_level_iar.inc
+0
-2
bsp/at91sam9260/platform/rt_low_level_keil.inc
bsp/at91sam9260/platform/rt_low_level_keil.inc
+0
-2
libcpu/arm/arm926/context_gcc.S
libcpu/arm/arm926/context_gcc.S
+13
-13
libcpu/arm/arm926/cpuport.c
libcpu/arm/arm926/cpuport.c
+20
-55
libcpu/arm/arm926/mmu.c
libcpu/arm/arm926/mmu.c
+99
-315
libcpu/arm/arm926/start_gcc.S
libcpu/arm/arm926/start_gcc.S
+20
-23
libcpu/arm/arm926/start_iar.S
libcpu/arm/arm926/start_iar.S
+15
-17
libcpu/arm/arm926/start_rvds.S
libcpu/arm/arm926/start_rvds.S
+23
-52
未找到文件。
bsp/at91sam9260/applications/startup.c
浏览文件 @
bec8b3f5
...
...
@@ -29,16 +29,6 @@
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
extern
void
rt_hw_interrupt_init
(
void
);
extern
void
rt_hw_board_init
(
void
);
extern
void
rt_system_timer_init
(
void
);
extern
void
rt_system_scheduler_init
(
void
);
extern
void
rt_thread_idle_init
(
void
);
extern
void
mmu_invalidate_icache
();
extern
void
rt_hw_cpu_icache_enable
(
void
);
extern
void
rt_show_version
(
void
);
extern
void
rt_system_heap_init
(
void
*
,
void
*
);
extern
void
rt_hw_finsh_init
(
void
);
extern
void
rt_application_init
(
void
);
/**
...
...
@@ -48,65 +38,38 @@ extern void rt_application_init(void);
/*@{*/
#if defined(__CC_ARM)
extern
int
Image
$$
ER_ZI
$$
ZI
$$
Limit
;
#define HEAP_
START ((void*)
&Image$$ER_ZI$$ZI$$Limit)
#define HEAP_
BEGIN (
&Image$$ER_ZI$$ZI$$Limit)
#elif (defined (__GNUC__))
extern
unsigned
char
__bss_end__
;
#define HEAP_
START ((void*)
&__bss_end__)
#define HEAP_
BEGIN (
&__bss_end__)
#elif (defined (__ICCARM__))
#pragma section="HEAP"
#define HEAP_START (__section_begin("HEAP"))
#endif
#define HEAP_END ((void*)0x24000000)
#ifdef RT_USING_FINSH
extern
void
finsh_system_init
(
void
);
#pragma section=".noinit"
#define HEAP_BEGIN (__section_end(".noinit"))
#endif
#define HEAP_END (0x24000000)
/**
* This function will startup RT-Thread RTOS.
*/
void
rtthread_startup
(
void
)
static
void
rtthread_startup
(
void
)
{
/* disable interrupt first */
rt_hw_interrupt_disable
();
/* enable cpu cache */
rt_hw_cpu_icache_disable
();
mmu_invalidate_icache
();
rt_hw_cpu_icache_enable
();
/* initialize hardware interrupt */
rt_hw_interrupt_init
();
/* initialize board */
rt_hw_board_init
();
/* show version */
rt_show_version
();
/* initialize tick */
rt_system_tick_init
();
/* initialize kernel object */
rt_system_object_init
();
/* initialize board */
rt_hw_board_init
();
/* initialize timer system
*/
rt_system_timer_init
();
/* show version
*/
rt_show_version
();
/* initialize heap memory system */
rt_system_heap_init
(
HEAP_START
,
HEAP_END
);
#ifdef RT_USING_MODULE
/* initialize module system*/
rt_system_module_init
();
#ifdef RT_USING_HEAP
rt_system_heap_init
((
void
*
)
HEAP_BEGIN
,
(
void
*
)
HEAP_END
);
#endif
/* initialize scheduler system */
rt_system_scheduler_init
();
/* initialize application */
rt_application_init
();
/* initialize scheduler system */
rt_system_scheduler_init
();
/* initialize system timer*/
rt_system_timer_init
();
/* initialize application */
rt_application_init
();
#ifdef RT_USING_FINSH
/* initialize finsh */
...
...
@@ -115,26 +78,29 @@ void rtthread_startup(void)
finsh_set_device
(
RT_CONSOLE_DEVICE_NAME
);
#endif
#endif
/* initialize timer thread */
rt_system_timer_thread_init
();
/* initialize system timer thread */
rt_system_timer_thread_init
();
/* initialize idle thread */
rt_thread_idle_init
();
/* initialize idle thread */
rt_thread_idle_init
();
/* start scheduler */
rt_system_scheduler_start
();
/* start scheduler */
rt_system_scheduler_start
();
/* never reach here */
return
;
/* never reach here */
return
;
}
int
main
(
void
)
{
/* startup RT-Thread RTOS */
rtthread_startup
();
/* disable interrupt first */
rt_hw_interrupt_disable
();
/* startup RT-Thread RTOS */
rtthread_startup
();
return
0
;
return
0
;
}
/*@}*/
bsp/at91sam9260/drivers/board.c
浏览文件 @
bec8b3f5
...
...
@@ -33,7 +33,7 @@
*/
/*@{*/
extern
void
rt_hw_interrupt_init
(
void
);
extern
void
rt_hw_clock_init
(
void
);
extern
void
rt_hw_get_clock
(
void
);
...
...
@@ -143,6 +143,10 @@ static void at91sam926x_pit_init(void)
*/
void
rt_hw_board_init
()
{
/* initialize mmu */
rt_hw_mmu_init
(
at91_mem_desc
,
sizeof
(
at91_mem_desc
)
/
sizeof
(
at91_mem_desc
[
0
]));
/* initialize hardware interrupt */
rt_hw_interrupt_init
();
/* initialize the system clock */
rt_hw_clock_init
();
...
...
@@ -150,8 +154,7 @@ void rt_hw_board_init()
rt_hw_uart_init
();
rt_console_set_device
(
RT_CONSOLE_DEVICE_NAME
);
/* initialize mmu */
rt_hw_mmu_init
(
at91_mem_desc
,
sizeof
(
at91_mem_desc
)
/
sizeof
(
at91_mem_desc
[
0
]));
/* initialize timer0 */
rt_hw_timer_init
();
...
...
bsp/at91sam9260/link_scripts/at91sam9260_ram.icf
浏览文件 @
bec8b3f5
//*****************************************************************************
//
// blinky.icf - Linker configuration file for blinky.
//
// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
//
//*****************************************************************************
//------------------------------------------------------------------------------
// Linker scatter for running in external SDRAM on the AT91SAM9260
//------------------------------------------------------------------------------
//
// Define a memory region that covers the entire 4 GB addressible space of the
...
...
@@ -38,12 +18,6 @@ define region FLASH = mem:[from 0x20000000 to 0x207FFFFF];
//
define region SRAM = mem:[from 0x20800000 to 0x23FFFFFF];
//
// Define a block for the heap. The size should be set to something other
// than zero if things in the C library that require the heap are used.
//
define block HEAP with alignment = 8, size = 0x02000000 { };
//
// Indicate that the read/write values should be initialized by copying from
// flash.
...
...
@@ -75,7 +49,7 @@ place at start of SRAM { section VTABLE };
//
// Place all read/write items into SRAM.
//
place in SRAM { readwrite
, block HEAP
};
place in SRAM { readwrite};
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
bsp/at91sam9260/link_scripts/at91sam9260_ram.scat
浏览文件 @
bec8b3f5
; * ----------------------------------------------------------------------------
; * ATMEL Microcontroller Software Support
; * ----------------------------------------------------------------------------
; * Copyright (c) 2008, Atmel Corporation
; *
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
; *
; * - Redistributions of source code must retain the above copyright notice,
; * this list of conditions and the disclaimer below.
; *
; * Atmel's name may not be used to endorse or promote products derived from
; * this software without specific prior written permission.
; *
; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; * ----------------------------------------------------------------------------
; *------------------------------------------------------------------------------
; * Linker scatter for running in external SDRAM on the AT91SAM9260
; *----------------------------------------------------------------------------*/
;*------------------------------------------------------------------------------
;* Linker scatter for running in external SDRAM on the AT91SAM9260
;*----------------------------------------------------------------------------*/
Load_region 0x20000000 0x00800000
{
...
...
@@ -38,21 +10,31 @@ Load_region 0x20000000 0x00800000
* (RESET +First)
.ANY (+RO +RW)
}
ARM_LIB_HEAP +0 EMPTY 0x1000
{
}
ARM_LIB_STACK +0 EMPTY 0x1000
{
}
; Application ZI data (.bss)
ER_ZI +0
{
* (+ZI)
}
; Application ZI data (.bss)
}
;Relocate_region 0x200000 0x1000
;{
; *.o (VECTOR, +First)
;}
ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000
{
}
ARM_LIB_STACK 0x22000000 EMPTY -0x1000
{
}
;
ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000
;
{
;
}
;
ARM_LIB_STACK 0x22000000 EMPTY -0x1000
;
{
;
}
}
bsp/at91sam9260/platform/rt_low_level_gcc.inc
浏览文件 @
bec8b3f5
...
...
@@ -29,5 +29,3 @@
.
equ
IRQ_STK_SIZE
,
4096
.
equ
FIQ_STK_SIZE
,
4096
.
equ
SYS_STK_SIZE
,
2048
/* vector table start should be 0x00000000 or 0xFFFF0000 */
.
equ
VECTOR_TABLE_START
,
0x00000000
bsp/at91sam9260/platform/rt_low_level_iar.inc
浏览文件 @
bec8b3f5
...
...
@@ -29,5 +29,3 @@
#define IRQ_STK_SIZE 1024
#define FIQ_STK_SIZE 1024
#define SYS_STK_SIZE 512
/* vector table start should be 0x00000000 or 0xFFFF0000 */
#define VECTOR_TABLE_START 0x00000000
bsp/at91sam9260/platform/rt_low_level_keil.inc
浏览文件 @
bec8b3f5
...
...
@@ -29,6 +29,4 @@ ABT_STK_SIZE EQU 512
IRQ_STK_SIZE
EQU
1024
FIQ_STK_SIZE
EQU
1024
SYS_STK_SIZE
EQU
512
;
/* vector table start should be 0x00000000 or 0xFFFF0000 */
VECTOR_TABLE_START
EQU
0x00000000
END
libcpu/arm/arm926/context_gcc.S
浏览文件 @
bec8b3f5
...
...
@@ -49,15 +49,15 @@ rt_hw_interrupt_enable:
*/
.
globl
rt_hw_context_switch
rt_hw_context_switch
:
stmfd
sp
!,
{
lr
}
@
; push pc (lr should be pushed in place of pc)
stmfd
sp
!,
{
r0
-
r12
,
lr
}
@
; push lr & register file
mrs
r4
,
cpsr
stmfd
sp
!,
{
r
4
}
@
; push cpsr
str
sp
,
[
r
0
]
@
; store sp in preempted tasks tcb
ldr
sp
,
[
r
1
]
@
; get new task stack pointer
ldmfd
sp
!,
{
r
4
}
@
; pop new task spsr
msr
spsr_cxsf
,
r
4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
@
; pop new task r0-r12, lr & pc
STMFD
SP
!,
{
LR
}
@
; push pc (lr should be pushed in place of pc)
STMFD
SP
!,
{
R0
-
R12
,
LR
}
@
; push lr & register file
MRS
R4
,
CPSR
STMFD
SP
!,
{
R
4
}
@
; push cpsr
STR
SP
,
[
R
0
]
@
; store sp in preempted tasks tcb
LDR
SP
,
[
R
1
]
@
; get new task stack pointer
LDMFD
SP
!,
{
R
4
}
@
; pop new task spsr
MSR
SPSR_cxsf
,
R
4
LDMFD
SP
!,
{
R0
-
R12
,
LR
,
PC
}^
@
; pop new task r0-r12, lr & pc
/*
*
void
rt_hw_context_switch_to
(
rt_uint32
to
)
;
...
...
@@ -65,10 +65,10 @@ rt_hw_context_switch:
*/
.
globl
rt_hw_context_switch_to
rt_hw_context_switch_to
:
ldr
sp
,
[
r
0
]
@
; get new task stack pointer
ldmfd
sp
!,
{
r
4
}
@
; pop new task cpsr
msr
spsr_cxsf
,
r
4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
@
; pop new task r0-r12, lr & pc
LDR
SP
,
[
R
0
]
@
; get new task stack pointer
LDMFD
SP
!,
{
R
4
}
@
; pop new task cpsr
MSR
SPSR_cxsf
,
R
4
LDMFD
SP
!,
{
R0
-
R12
,
LR
,
PC
}^
@
; pop new task r0-r12, lr & pc
/*
*
void
rt_hw_context_switch_interrupt
(
rt_uint32
from
,
rt_uint32
to
)
;
...
...
libcpu/arm/arm926/cpuport.c
浏览文件 @
bec8b3f5
...
...
@@ -32,18 +32,18 @@
extern
void
machine_reset
(
void
);
extern
void
machine_shutdown
(
void
);
#if
def __GNUC__
#if
defined(__GNUC__) || defined(__ICCARM__)
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
__asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
return
i
;
}
rt_inline
void
cache_enable
(
rt_uint32_t
bit
)
{
__asm
__
__volatile__
(
\
__asm
volatile
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"orr r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
...
...
@@ -54,7 +54,7 @@ rt_inline void cache_enable(rt_uint32_t bit)
rt_inline
void
cache_disable
(
rt_uint32_t
bit
)
{
__asm
__
__volatile__
(
\
__asm
volatile
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"bic r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
...
...
@@ -64,12 +64,12 @@ rt_inline void cache_disable(rt_uint32_t bit)
}
#endif
#if
def __CC_ARM
#if
defined(__CC_ARM)
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
i
,
c1
,
c0
,
0
}
...
...
@@ -81,7 +81,7 @@ rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
bit
...
...
@@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
bit
...
...
@@ -102,38 +102,6 @@ rt_inline void cache_disable(rt_uint32_t bit)
}
#endif
#ifdef __ICCARM__
rt_inline
rt_uint32_t
cp15_rd
(
void
)
{
rt_uint32_t
i
;
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
return
i
;
}
rt_inline
void
cache_enable
(
rt_uint32_t
bit
)
{
asm
volatile
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"orr r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
}
rt_inline
void
cache_disable
(
rt_uint32_t
bit
)
{
asm
volatile
(
\
"mrc p15,0,r0,c1,c0,0
\n\t
"
\
"bic r0,r0,%0
\n\t
"
\
"mcr p15,0,r0,c1,c0,0"
\
:
\
:
"r"
(
bit
)
\
:
"memory"
);
}
#endif
/**
* enable I-Cache
*
...
...
@@ -249,27 +217,24 @@ int __rt_ffs(int value)
return
x
;
}
#elif defined(__ICCARM__)
#elif defined(__
GNUC__) || defined(__
ICCARM__)
int
__rt_ffs
(
int
value
)
{
if
(
value
==
0
)
return
value
;
register
rt_uint32_t
x
;
__ASM
(
"RSB r4, r0, #0"
);
__ASM
(
"AND r4, r4, r0"
);
__ASM
(
"CLZ r4, r4"
);
__ASM
(
"RSB r0, r4, #32"
);
}
#elif defined(__GNUC__)
int
__rt_ffs
(
int
value
)
{
if
(
value
==
0
)
return
value
;
value
&=
(
-
value
);
asm
(
"clz %0, %1"
:
"=r"
(
value
)
:
"r"
(
value
));
return
(
32
-
value
);
__asm
(
"rsb %[temp], %[val], #0
\n
"
"and %[temp], %[temp], %[val]
\n
"
"clz %[temp], %[temp]
\n
"
"rsb %[temp], %[temp], #32
\n
"
:
[
temp
]
"=r"
(
x
)
:
[
val
]
"r"
(
value
)
);
return
x
;
}
#endif
...
...
libcpu/arm/arm926/mmu.c
浏览文件 @
bec8b3f5
...
...
@@ -24,6 +24,7 @@
#include "mmu.h"
/*----- Keil -----------------------------------------------------------------*/
#ifdef __CC_ARM
void
mmu_setttbase
(
rt_uint32_t
i
)
{
...
...
@@ -35,32 +36,22 @@ void mmu_setttbase(rt_uint32_t i)
* set by page table entry
*/
value
=
0
;
__asm
{
mcr
p15
,
0
,
value
,
c8
,
c7
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
value
,
c8
,
c7
,
0
}
value
=
0x55555555
;
__asm
{
mcr
p15
,
0
,
value
,
c3
,
c0
,
0
mcr
p15
,
0
,
i
,
c2
,
c0
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
value
,
c3
,
c0
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
i
,
c2
,
c0
,
0
}
}
void
mmu_set_domain
(
rt_uint32_t
i
)
{
__asm
{
mcr
p15
,
0
,
i
,
c3
,
c0
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
i
,
c3
,
c0
,
0
}
}
void
mmu_enable
()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
#
0x01
...
...
@@ -72,7 +63,7 @@ void mmu_disable()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
#
0x01
...
...
@@ -84,7 +75,7 @@ void mmu_enable_icache()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
#
0x1000
...
...
@@ -96,7 +87,7 @@ void mmu_enable_dcache()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
#
0x04
...
...
@@ -108,7 +99,7 @@ void mmu_disable_icache()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
#
0x1000
...
...
@@ -120,7 +111,7 @@ void mmu_disable_dcache()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
#
0x04
...
...
@@ -132,7 +123,7 @@ void mmu_enable_alignfault()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
orr
value
,
value
,
#
0x02
...
...
@@ -144,7 +135,7 @@ void mmu_disable_alignfault()
{
register
rt_uint32_t
value
;
__asm
__asm
volatile
{
mrc
p15
,
0
,
value
,
c1
,
c0
,
0
bic
value
,
value
,
#
0x02
...
...
@@ -154,10 +145,7 @@ void mmu_disable_alignfault()
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
__asm
{
mcr
p15
,
0
,
index
,
c7
,
c14
,
2
}
__asm
volatile
{
mcr
p15
,
0
,
index
,
c7
,
c14
,
2
}
}
void
mmu_clean_invalidated_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
...
...
@@ -168,10 +156,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
__asm
{
MCR
p15
,
0
,
ptr
,
c7
,
c14
,
1
}
__asm
volatile
{
MCR
p15
,
0
,
ptr
,
c7
,
c14
,
1
}
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -184,10 +169,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
__asm
{
MCR
p15
,
0
,
ptr
,
c7
,
c10
,
1
}
__asm
volatile
{
MCR
p15
,
0
,
ptr
,
c7
,
c10
,
1
}
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -200,10 +182,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
__asm
{
MCR
p15
,
0
,
ptr
,
c7
,
c6
,
1
}
__asm
volatile
{
MCR
p15
,
0
,
ptr
,
c7
,
c6
,
1
}
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -213,10 +192,7 @@ void mmu_invalidate_tlb()
register
rt_uint32_t
value
;
value
=
0
;
__asm
{
mcr
p15
,
0
,
value
,
c8
,
c7
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
value
,
c8
,
c7
,
0
}
}
void
mmu_invalidate_icache
()
...
...
@@ -225,10 +201,7 @@ void mmu_invalidate_icache()
value
=
0
;
__asm
{
mcr
p15
,
0
,
value
,
c7
,
c5
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
value
,
c7
,
c5
,
0
}
}
...
...
@@ -238,12 +211,10 @@ void mmu_invalidate_dcache_all()
value
=
0
;
__asm
{
mcr
p15
,
0
,
value
,
c7
,
c6
,
0
}
__asm
volatile
{
mcr
p15
,
0
,
value
,
c7
,
c6
,
0
}
}
#elif defined(__GNUC__)
/*----- GNU ------------------------------------------------------------------*/
#elif defined(__GNUC__) || defined(__ICCARM__)
void
mmu_setttbase
(
register
rt_uint32_t
i
)
{
register
rt_uint32_t
value
;
...
...
@@ -254,311 +225,117 @@ void mmu_setttbase(register rt_uint32_t i)
* set by page table entry
*/
value
=
0
;
asm
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0x55555555
;
asm
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_icache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_dcache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_icache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_dcache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_clean_invalidated_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
{
unsigned
int
ptr
;
ptr
=
buffer
&
~
(
CACHE_LINE_SIZE
-
1
);
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
void
mmu_clean_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
{
unsigned
int
ptr
;
ptr
=
buffer
&
~
(
CACHE_LINE_SIZE
-
1
);
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
void
mmu_invalidate_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
{
unsigned
int
ptr
;
ptr
=
buffer
&
~
(
CACHE_LINE_SIZE
-
1
);
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
void
mmu_invalidate_tlb
()
{
asm
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
asm
volatile
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
void
mmu_invalidate_dcache_all
()
{
asm
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
}
#elif defined(__ICCARM__)
void
mmu_setttbase
(
register
rt_uint32_t
i
)
{
register
rt_uint32_t
value
;
asm
volatile
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value
=
0
;
asm
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0x55555555
;
asm
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"orr r0, r0, #0x1
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
}
void
mmu_disable
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
0x1
;
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"bic r0, r0, #0x1
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_icache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"orr r0, r0, #(1<<12)
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
}
void
mmu_enable_dcache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
2
);
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"orr r0, r0, #(1<<2)
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_icache
()
{
register
rt_uint32_t
i
;
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"bic r0, r0, #(1<<12)
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_dcache
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"bic r0, r0, #(1<<2)
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
i
&=
~
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"orr r0, r0, #1
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
i
|=
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
{
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
asm
volatile
(
"mrc p15, 0, r0, c1, c0, 0
\n
"
"bic r0, r0, #1
\n
"
"mcr p15, 0, r0, c1, c0, 0
\n
"
:::
"r0"
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_clean_invalidated_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
...
...
@@ -569,7 +346,8 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -583,7 +361,8 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -596,35 +375,40 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
void
mmu_invalidate_tlb
()
{
asm
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_dcache_all
()
{
asm
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
}
#endif
/* level1 page table */
#if defined(__ICCARM__)
#pragma data_alignment=(16*1024)
static
volatile
unsigned
int
_page_table
[
4
*
1024
];
;
static
volatile
rt_uint32_t
_page_table
[
4
*
1024
]
;
#else
static
volatile
unsigned
in
t
_page_table
[
4
*
1024
]
\
__attribute__
((
aligned
(
16
*
1024
)));
static
volatile
rt_uint32_
t
_page_table
[
4
*
1024
]
\
__attribute__
((
aligned
(
16
*
1024
)));
#endif
void
mmu_setmtt
(
rt_uint32_t
vaddrStart
,
rt_uint32_t
vaddrEnd
,
rt_uint32_t
paddrStart
,
rt_uint32_t
attr
)
{
...
...
libcpu/arm/arm926/start_gcc.S
浏览文件 @
bec8b3f5
...
...
@@ -21,6 +21,7 @@
*
Date
Author
Notes
*
2011
-
01
-
13
weety
first
version
*
2015
-
04
-
15
ArdaFu
Split
from
AT91SAM9260
BSP
*
2015
-
04
-
21
ArdaFu
Remove
remap
code
.
Using
mmu
to
map
vector
table
*/
#define S_FRAME_SIZE (18*4) //72
...
...
@@ -63,31 +64,30 @@
.
global
UND_STACK_START
UND_STACK_START
:
.
space
SVC_STK_SIZE
.
align
2
.
global
SVC_STACK_START
SVC_STACK_START
:
.
space
ABT_STK_SIZE
.
align
2
.
global
ABT_STACK_START
ABT_STACK_START
:
.
space
IRQ_STK_SIZE
.
align
2
.
global
IRQ_STACK_START
IRQ_STACK_START
:
.
space
FIQ_STK_SIZE
.
align
2
.
global
FIQ_STACK_START
FIQ_STACK_START
:
.
space
IRQ_STK_SIZE
.
align
2
.
global
IRQ_STACK_START
IRQ_STACK_START
:
.
skip
SYS_STK_SIZE
.
align
2
.
global
SYS_STACK_START
SYS_STACK_START
:
.
space
SVC_STK_SIZE
.
align
2
.
global
SVC_STACK_START
SVC_STACK_START
:
@
;--------------Jump vector table-----------------------------------------------
.
section
.
init
,
"ax"
...
...
@@ -132,24 +132,21 @@ Reset_Handler:
MRS
R0
,
CPSR
BIC
R0
,
R0
,
#
MODEMASK
ORR
R0
,
R0
,
#
MODE_SVC
|
NOINT
MSR
CPSR
,
R0
LDR
SP
,
=
SVC_STACK_START
MSR
CPSR_cxsf
,
R0
@
; Set CO-Processor
@
; little-end,disbale I/D Cache MMU, vector table is 0x00000000
MRC
P15
,
0
,
R0
,
C1
,
C0
,
0
@
; Read CP15
LDR
R1
,
=
0x00003085
@
; set clear bits
BIC
R0
,
R0
,
R1
MCR
P15
,
0
,
R0
,
C1
,
C0
,
0
@
; Write CP15
@
; Call low level init function,
@
; disable and clear all IRQs and remap internal ram to 0x00000000.
@
; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
LDR
SP
,
=
SVC_STACK_START
LDR
R0
,
=
rt_low_level_init
BLX
R0
@
; Copy Exception Vectors to Internal RAM
LDR
R8
,
=
entry
@
; Source
LDR
R9
,
=
VECTOR_TABLE_START
@
; Destination
CMP
R8
,
R9
BEQ
Setup_Stack
LDMIA
R8
!,
{
R0
-
R7
}
@
; Load Vectors
STMIA
R9
!,
{
R0
-
R7
}
@
; Store Vectors
LDMIA
R8
!,
{
R0
-
R7
}
@
; Load Handler Addresses
STMIA
R9
!,
{
R0
-
R7
}
@
; Store Handler Addresses
Setup_Stack
:
@
; Setup Stack for each mode
MRS
R0
,
CPSR
...
...
libcpu/arm/arm926/start_iar.S
浏览文件 @
bec8b3f5
...
...
@@ -21,6 +21,7 @@
; * Date Author Notes
; * 2011-01-13 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
; */
#define S_FRAME_SIZE (18*4) ;72
...
...
@@ -80,16 +81,16 @@ FIQ_STACK_START:
PUBLIC
IRQ_STACK_START
IRQ_STACK_START
:
ALIGNRAM
2
DS8
SVC_STK_SIZE
PUBLIC
SVC_STACK_START
SVC_STACK_START
:
ALIGNRAM
2
DS8
SYS_STK_SIZE
PUBLIC
SYS_STACK_START
SYS_STACK_START
:
ALIGNRAM
2
DS8
SVC_STK_SIZE
PUBLIC
SVC_STACK_START
SVC_STACK_START
:
;--------------Jump vector table------------------------------------------------
SECTION
.
intvec
:
CODE
:
ROOT
(
2
)
ARM
...
...
@@ -134,22 +135,19 @@ Reset_Handler:
BIC
R0
,
R0
,
#
MODEMASK
ORR
R0
,
R0
,
#
MODE_SVC
|
NOINT
MSR
CPSR_cxsf
,
R0
LDR
SP
,
=
SVC_STACK_START
; Set CO-Processor
; little-end,disbale I/D Cache MMU, vector table is 0x00000000
MRC
P15
,
0
,
R0
,
C1
,
C0
,
0
; Read CP15
LDR
R1
,
=
0x00003085
; set clear bits
BIC
R0
,
R0
,
R1
MCR
P15
,
0
,
R0
,
C1
,
C0
,
0
; Write CP15
; Call low level init function,
; disable and clear all IRQs and remap internal ram to 0x00000000.
; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
LDR
SP
,
=
SVC_STACK_START
LDR
R0
,
=
rt_low_level_init
BLX
R0
; Copy Exception Vectors to Internal RAM
LDR
R8
,
=
Entry_Point
; Source
LDR
R9
,
=
VECTOR_TABLE_START
; Destination
CMP
R8
,
R9
BEQ
Setup_Stack
LDMIA
R8
!,
{
R0
-
R7
}
; Load Vectors
STMIA
R9
!,
{
R0
-
R7
}
; Store Vectors
LDMIA
R8
!,
{
R0
-
R7
}
; Load Handler Addresses
STMIA
R9
!,
{
R0
-
R7
}
; Store Handler Addresses
Setup_Stack
:
; Setup Stack for each mode
...
...
libcpu/arm/arm926/start_rvds.S
浏览文件 @
bec8b3f5
...
...
@@ -20,7 +20,8 @@
; * Change Logs:
; * Date Author Notes
; * 2011-08-14 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
; */
S_FRAME_SIZE
EQU
(
18
*
4
)
;72
...
...
@@ -59,46 +60,38 @@ NOINT EQU 0xC0
GET
rt_low_level_keil.inc
;----------------------- Stack and Heap Definitions ----------------------------
AREA
STACK
,
NOINIT
,
READWRITE
,
ALIGN
=
3
AREA
STACK
,
NOINIT
,
READWRITE
,
ALIGN
=
2
Stack_Mem
SPACE
UND_STK_SIZE
EXPORT
UND_STACK_START
UND_STACK_START
ALIGN
8
ALIGN
4
SPACE
ABT_STK_SIZE
EXPORT
ABT_STACK_START
ABT_STACK_START
ALIGN
8
ALIGN
4
SPACE
FIQ_STK_SIZE
EXPORT
FIQ_STACK_START
FIQ_STACK_START
ALIGN
8
ALIGN
4
SPACE
IRQ_STK_SIZE
EXPORT
IRQ_STACK_START
IRQ_STACK_START
ALIGN
8
SPACE
SVC_STK_SIZE
EXPORT
SVC_STACK_START
SVC_STACK_START
ALIGN
8
ALIGN
4
SPACE
SYS_STK_SIZE
EXPORT
SYS_STACK_START
SYS_STACK_START
Stack_Top
Heap_Size
EQU
0x00000000
AREA
HEAP
,
NOINIT
,
READWRITE
,
ALIGN
=
3
__heap_base
Heap_Mem
SPACE
Heap_Size
__heap_limit
ALIGN
4
SPACE
SVC_STK_SIZE
EXPORT
SVC_STACK_START
SVC_STACK_START
Stack_Top
PRESERVE8
;--------------Jump vector table------------------------------------------------
EXPORT
Entry_Point
...
...
@@ -139,25 +132,22 @@ Reset_Handler
; set the cpu to SVC32 mode
MRS
R0
,
CPSR
BIC
R0
,
R0
,#
MODEMASK
ORR
R0
,
R0
,#
MODE_SVC
MSR
CPSR_CXSF
,
R0
LDR
SP
,
=
SVC_STACK_START
ORR
R0
,
R0
,#
MODE_SVC
:OR:
NOINT
MSR
CPSR_cxsf
,
R0
; Set CO-Processor
; little-end,disbale I/D Cache MMU, vector table is 0x00000000
MRC
p15
,
0
,
R0
,
c1
,
c0
,
0
; Read CP15
LDR
R1
,
=
0x00003085
; set clear bits
BIC
R0
,
R0
,
R1
MCR
p15
,
0
,
R0
,
c1
,
c0
,
0
; Write CP15
; Call low level init function,
; disable and clear all IRQs and remap internal ram to 0x00000000.
; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
LDR
SP
,
=
SVC_STACK_START
LDR
R0
,
=
rt_low_level_init
BLX
R0
; Copy Exception Vectors to Internal RAM
LDR
R8
,
=
Entry_Point
; Source
LDR
R9
,
=
VECTOR_TABLE_START
; Destination
CMP
R8
,
R9
BEQ
Setup_Stack
LDMIA
R8
!,
{
R0
-
R7
}
; Load Vectors
STMIA
R9
!,
{
R0
-
R7
}
; Store Vectors
LDMIA
R8
!,
{
R0
-
R7
}
; Load Handler Addresses
STMIA
R9
!,
{
R0
-
R7
}
; Store Handler Addresses
Setup_Stack
; Setup Stack for each mode
MRS
R0
,
CPSR
...
...
@@ -301,23 +291,4 @@ rt_hw_context_switch_interrupt_do PROC
LDMFD
SP
!,
{
R0
-
R12
,
LR
,
PC
}^
; pop new task's R0-R12,LR & PC SPSR to CPSR
ENDP
IF
:DEF:
__MICROLIB
EXPORT
__heap_base
EXPORT
__heap_limit
ELSE
; User Initial Stack & Heap
AREA
|.text|
,
CODE
,
READONLY
IMPORT
__use_two_region_memory
EXPORT
__user_initial_stackheap
__user_initial_stackheap
LDR
R0
,
=
Heap_Mem
LDR
R1
,
=
(
Stack_Mem
+
SYS_STK_SIZE
)
LDR
R2
,
=
(
Heap_Mem
+
Heap_Size
)
LDR
R3
,
=
Stack_Mem
BX
LR
ENDIF
END
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