[bsp] add bl808 lp core (#7069)

* Add riscv_32e support

* add bl808 lp core

* update README.md

bsp/README.md

@@ -146,7 +146,7 @@ RT-THREAD bsp company list
 - 紫芯
   - [asm9260t](asm9260t)
 - 博流
-  - [bl808](bl808)
+  - [bouffalo_lab](bouffalo_lab) series
 - 航顺
   - [hk32](hk32) series
 - 辉芒微

bsp/bouffalo_lab/README.md

@@ -116,7 +116,7 @@ Windows下推荐使用[env工具][1]，在console下进入bsp/bouffalo_lab/bl61x
 
 ### 3.1. GUI方式下载
 
-当前bsp必须使用`bouffalo_flash_cube-1.0.4](https://pan.baidu.com/s/1eG9pkxf3riAqQAu9aXiOjw?pwd=miv1)工具进行烧录，否则无法正常运行。
+当前bsp必须使用[bouffalo_flash_cube-1.0.4](https://pan.baidu.com/s/1eG9pkxf3riAqQAu9aXiOjw?pwd=miv1)工具进行烧录，否则无法正常运行。
 
 1. 连接好串口并在工具上选择对应的串口号
 

bsp/bouffalo_lab/bl808/flash_prog_cfg.ini

@@ -9,3 +9,7 @@ boot2_isp_mode = 0
 [FW1]
 filedir = ./m0/rtthread_m0.bin
 address = 0x000000
+
+[FW2]
+filedir = ./lp/rtthread_lp.bin
+address = 0xC0000

bsp/bouffalo_lab/bl808/lp/Kconfig

+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"

bsp/bouffalo_lab/bl808/lp/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/bouffalo_lab/bl808/lp/SConstruct

+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/../libraries'):
+    libraries_path_prefix = SDK_ROOT + '/../libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/bouffalo_lab/bl808/lp/applications/SConscript

+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/bouffalo_lab/bl808/lp/applications/main.c

+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ */
+
+#include <rtthread.h>
+#include <stdio.h>
+
+int main(void)
+{
+    while(1)
+    {
+        rt_kprintf("Hello, RISC-V!\n");
+        rt_thread_delay(5000);
+    }
+
+    return 0;
+}

bsp/bouffalo_lab/bl808/lp/board/Kconfig

+config BSP_USING_BL808
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select BL808_CORE_LP
+    default y
+
+config BL808_CORE_LP
+    bool
+    default y
\ No newline at end of file

bsp/bouffalo_lab/bl808/lp/board/SConscript

+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/bouffalo_lab/bl808/lp/board/board.c

+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#define RT_HEAP_SIZE 1024
+static uint32_t user_heap[RT_HEAP_SIZE];     // heap default size: 4K(1024 * 4)
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_irq_initialize();
+
+    CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+    bflb_mtimer_config(HW_MTIMER_CLOCK * 2 / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init((void *)user_heap, (void *)user_heap + RT_HEAP_SIZE);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);

bsp/bouffalo_lab/bl808/lp/board/board.h

+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <rtconfig.h>
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl808_glb.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_ef_cfg.h"
+#include "bl808_uhs_phy.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif

bsp/bouffalo_lab/bl808/lp/board/fw_header.c

+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x07, /*!<  0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.mcu_clk = 0x04,   /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
+    .clk_cfg.cfg.mcu_clk_div = 0x00,
+    .clk_cfg.cfg.mcu_bclk_div = 0x00,
+
+    .clk_cfg.cfg.mcu_pbclk_div = 0x03,
+    .clk_cfg.cfg.lp_div = 0x01,
+    .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
+    .clk_cfg.cfg.dsp_clk_div = 0x00,
+
+    .clk_cfg.cfg.dsp_bclk_div = 0x01,
+    .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
+    .clk_cfg.cfg.dsp_pbclk_div = 0x00,
+    .clk_cfg.cfg.emi_clk = 0x02, /*!<  0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+
+    .clk_cfg.cfg.emi_clk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.cfg.wifipll_pu = 0x01,
+
+    .clk_cfg.cfg.aupll_pu = 0x01,
+    .clk_cfg.cfg.cpupll_pu = 0x01,
+    .clk_cfg.cfg.mipipll_pu = 0x01,
+    .clk_cfg.cfg.uhspll_pu = 0x01,
+
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* basic cfg */
+    .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
+    .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
+    .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
+    .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
+    .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
+    .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
+    .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
+    .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
+    .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
+    .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
+    .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
+    .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
+    .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
+    .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
+    .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+    .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+    .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
+    .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+    .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+    .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
+
+#ifdef BFLB_BOOT2
+    .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
+#else
+    .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+#endif
+    .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
+
+    .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+    .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
+
+    /* cpu cfg */
+    .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
+    .cpu_cfg[0].halt_cpu = 0x0,       /* halt this cpu */
+    .cpu_cfg[0].cache_enable = 0x0,   /* cache setting :only for BL Cache */
+    .cpu_cfg[0].cache_wa = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wb = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wt = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].rsvd = 0x0,
+
+    .cpu_cfg[0].cache_range_h = 0x00000000,
+    .cpu_cfg[0].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[0].image_address_offset = 0x0,
+    .cpu_cfg[0].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[0].msp_val = 0x00000000, /* msp value */
+
+    /* cpu cfg */
+    .cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
+    .cpu_cfg[1].halt_cpu = 0x0,      /* halt this cpu */
+    .cpu_cfg[1].cache_enable = 0x0,  /* cache setting :only for BL Cache */
+    .cpu_cfg[1].cache_wa = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wb = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wt = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].rsvd = 0x0,
+
+    .cpu_cfg[1].cache_range_h = 0x00000000,
+    .cpu_cfg[1].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[1].image_address_offset = 0x0,
+    .cpu_cfg[1].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[1].msp_val = 0x00000000, /* msp value */
+
+    /* address of partition table 0 */ /* 4 */
+    .boot2_pt_table_0_rsvd = 0x00000000,
+    /* address of partition table 1 */ /* 4 */
+    .boot2_pt_table_1_rsvd = 0x00000000,
+
+    /* address of flashcfg table list */ /* 4 */
+    .flash_cfg_table_addr = 0x00000000,
+    /* flashcfg table list len */ /* 4 */
+    .flash_cfg_table_len = 0x00000000,
+
+    .rsvd1[0] = 0x20000320,
+    .rsvd1[1] = 0x00000000,
+    .rsvd1[2] = 0x2000F038,
+    .rsvd1[3] = 0x18000000,
+
+    .crc32 = 0xdeadbeef /* 4 */
+};

bsp/bouffalo_lab/bl808/lp/board/fw_header.h

+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t mcu_clk;
+    uint8_t mcu_clk_div;
+    uint8_t mcu_bclk_div;
+
+    uint8_t mcu_pbclk_div;
+    uint8_t lp_div;
+    uint8_t dsp_clk;
+    uint8_t dsp_clk_div;
+
+    uint8_t dsp_bclk_div;
+    uint8_t dsp_pbclk;
+    uint8_t dsp_pbclk_div;
+    uint8_t emi_clk;
+
+    uint8_t emi_clk_div;
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t wifipll_pu;
+
+    uint8_t aupll_pu;
+    uint8_t cpupll_pu;
+    uint8_t mipipll_pu;
+    uint8_t uhspll_pu;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t rsvd_0             : 1; /* [9]      boot2 enable(rsvd_0) */
+    uint32_t rsvd_1             : 1; /* [10]     boot2 rollback(rsvd_1) */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t rsvd_3             : 1; /* [31] rsvd_3 */
+
+    uint32_t group_image_offset; /* flash controller offset */
+    uint32_t aes_region_len;     /* aes region length */
+
+    uint32_t img_len_cnt;  /* image length or segment count */
+    uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+    uint8_t config_enable;     /* coinfig this cpu */
+    uint8_t halt_cpu;          /* halt this cpu */
+    uint8_t cache_enable  : 1; /* cache setting */
+    uint8_t cache_wa      : 1; /* cache setting */
+    uint8_t cache_wb      : 1; /* cache setting */
+    uint8_t cache_wt      : 1; /* cache setting */
+    uint8_t cache_way_dis : 4; /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t cache_range_h; /* cache range high */
+    uint32_t cache_range_l; /* cache range low */
+
+    uint32_t image_address_offset; /* image_address_offset */
+    uint32_t rsvd0;                /* rsvd0 */
+    uint32_t msp_val;              /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /* 4 */
+    uint32_t rivison;   /* 4 */
+
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 20 + 4 */
+
+    struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+    struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
+
+    uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+    uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+    uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+    uint32_t flash_cfg_table_len; /* flashcfg table list len */         /* 4 */
+
+    uint32_t rsvd0[8]; /* rsvd */
+    uint32_t rsvd1[8]; /* rsvd */
+
+    uint32_t rsvd3[5]; /* 20 */
+
+    uint32_t crc32; /* 4 */
+};
+
+#define BFLB_FW_LENGTH_OFFSET 140
+#define BFLB_FW_HASH_OFFSET   144
+
+#endif

bsp/bouffalo_lab/bl808/lp/board/linker_scripts/bl808_flash_lp.ld

+/****************************************************************************************
+* @file flash.ld
+*
+* @brief This file is the link script file (gnuarm or armgcc).
+*
+* Copyright (C) BouffaloLab 2021
+*
+****************************************************************************************
+*/
+
+/* configure the CPU type */
+OUTPUT_ARCH( "riscv" )
+/* link with the standard c library */
+INPUT(-lc)
+/* link with the standard GCC library */
+INPUT(-lgcc)
+/* configure the entry point */
+ENTRY(__start)
+
+StackSize    = 0x0400; /*  1KB */
+HeapMinSize  = 0x1000; /*  4KB */
+
+MEMORY
+{
+    fw_header_memory  (rx)  : ORIGIN = 0x580C0000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0x580C0000, LENGTH = 1M
+    itcm_memory (rx)  : ORIGIN = 0x2202C000, LENGTH = 16K
+    dtcm_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 16K
+    nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
+    ram_memory  (!rx) : ORIGIN = 0x22034000, LENGTH = 16K
+    xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
+}
+
+SECTIONS
+{
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
+
+    .text :
+    {
+        . = ALIGN(4);
+        __text_code_start__ = .;
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
+
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        
+        /* section information for usb usbh_class_info */
+        . = ALIGN(4);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        . = ALIGN(4);
+        __usbh_class_info_end__ = .;
+
+        /*put .rodata**/
+        *(EXCLUDE_FILE( *bl808_glb*.o* \
+                        *bl808_glb_gpio*.o* \
+                        *bl808_pds*.o* \
+                        *bl808_aon*.o* \
+                        *bl808_hbn*.o* \
+                        *bl808_l1c*.o* \
+                        *bl808_common*.o* \
+                        *bl808_clock*.o* \
+                        *bl808_ef_ctrl*.o* \
+                        *bl808_sf_cfg*.o* \
+                        *bl808_sf_ctrl*.o* \
+                        *bl808_sflash*.o* \
+                        *bl808_xip_sflash*.o* \
+                        *bl808_romapi_patch*.o* ) .rodata*)
+        *(.srodata)
+        *(.srodata.*)
+
+        . = ALIGN(4);
+        __text_code_end__ = .;
+    } > xip_memory
+
+    . = ALIGN(4);
+    __itcm_load_addr = .;
+
+    .itcm_region : AT (__itcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_code_start__ = .;
+
+        *(.tcm_code.*)
+        *(.tcm_const.*)
+        *(.sclock_rlt_code.*)
+        *(.sclock_rlt_const.*)
+
+        *bl808_glb*.o*(.rodata*)
+        *bl808_glb_gpio*.o*(.rodata*)
+        *bl808_pds*.o*(.rodata*)
+        *bl808_aon*.o*(.rodata*)
+        *bl808_hbn*.o*(.rodata*)
+        *bl808_l1c*.o*(.rodata*)
+        *bl808_common*.o*(.rodata*)
+        *bl808_clock*.o*(.rodata*)
+        *bl808_ef_ctrl*.o*(.rodata*)
+        *bl808_sf_cfg*.o*(.rodata*)
+        *bl808_sf_ctrl*.o*(.rodata*)
+        *bl808_sflash*.o*(.rodata*)
+        *bl808_xip_sflash*.o*(.rodata*)
+        *bl808_romapi_patch*.o*(.rodata*)
+
+        . = ALIGN(4);
+        __tcm_code_end__ = .;
+    } > itcm_memory
+
+    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .dtcm_region : AT (__dtcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_data_start__ = .;
+
+        *(.tcm_data)
+        /* *finger_print.o(.data*) */
+
+        . = ALIGN(4);
+        __tcm_data_end__ = .;
+    } > dtcm_memory
+
+    /*************************************************************************/
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + StackSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
+    PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+
+    /*************************************************************************/
+
+    __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
+    .nocache_ram_region  : AT (__nocache_ram_load_addr)
+    {
+        . = ALIGN(4);
+        __nocache_ram_data_start__ = .;
+
+        *(.nocache_ram)
+
+        . = ALIGN(4);
+        __nocache_ram_data_end__ = .;
+    } > nocache_ram_memory
+
+    __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
+
+    /* Data section */
+    RAM_DATA : AT (__ram_load_addr)
+    {
+        . = ALIGN(4);
+        __ram_data_start__ = .;
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.data)
+        *(.data.*)
+        *(.sdata)
+        *(.sdata.*)
+        *(.sdata2)
+        *(.sdata2.*)
+
+        . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
+        __ram_data_end__ = .;
+    } > ram_memory
+
+    __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
+    ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
+
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+
+        *(.bss*)
+        *(.sbss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram_memory
+
+    .noinit_data (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __noinit_data_start__ = .;
+
+        *(.noinit_data*)
+
+        . = ALIGN(4);
+        __noinit_data_end__ = .;
+    } > ram_memory
+
+    .nocache_noinit_ram_region (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __nocache_noinit_ram_data_start__ = .;
+
+        *(.nocache_noinit_ram)
+        *(.noncacheable)
+
+        . = ALIGN(4);
+        __nocache_noinit_ram_data_end__ = .;
+    } > nocache_ram_memory
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(4);
+        __HeapBase = .;
+
+        /*__end__ = .;*/
+        /*end = __end__;*/
+        KEEP(*(.heap*))
+
+        . = ALIGN(4);
+        __HeapLimit = .;
+    } > ram_memory
+
+    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
+    ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
+
+}
+

bsp/bouffalo_lab/bl808/lp/board/trap_gcc.S

+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file

bsp/bouffalo_lab/bl808/lp/combine.sh

+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=../config
+TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file

bsp/bouffalo_lab/bl808/lp/rtconfig.h

+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 512
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL808
+#define BL808_CORE_LP
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO18
+#define UART1_RX_USING_GPIO19
+
+#endif

bsp/bouffalo_lab/bl808/lp/rtconfig.py

+import os
+
+# toolchains options
+ARCH        ='risc-v'
+VENDOR      ='t-head'
+CPU         ='e9xx'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32emcxtheadse -mabi=ilp32e -mtune=e902'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl808_flash_lp.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_lp.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl808 ./rtthread_lp.bin\n'
\ No newline at end of file

libcpu/risc-v/common/context_gcc.S

@@ -9,6 +9,7 @@
  * 2018/12/27     Jesven       Add SMP support
  * 2020/11/20     BalanceTWK   Add FPU support
  * 2022/12/28     WangShun     Add macro to distinguish whether FPU is supported
+ * 2023/03/19     Flyingcys    Add riscv_32e support
  */
 
 #define __ASSEMBLY__
@@ -115,7 +116,12 @@ rt_hw_context_switch:
     FSTORE  f31, 31 * FREGBYTES(sp)
 
 #endif
+#ifndef __riscv_32e
     addi  sp,  sp, -32 * REGBYTES
+#else
+    addi  sp,  sp, -16 * REGBYTES
+#endif
+
     STORE sp,  (a0)
 
     STORE x1,   0 * REGBYTES(sp)
@@ -140,6 +146,7 @@ save_mpie:
     STORE x13, 13 * REGBYTES(sp)
     STORE x14, 14 * REGBYTES(sp)
     STORE x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     STORE x16, 16 * REGBYTES(sp)
     STORE x17, 17 * REGBYTES(sp)
     STORE x18, 18 * REGBYTES(sp)
@@ -156,7 +163,7 @@ save_mpie:
     STORE x29, 29 * REGBYTES(sp)
     STORE x30, 30 * REGBYTES(sp)
     STORE x31, 31 * REGBYTES(sp)
-
+#endif
     /* restore to thread context
      * sp(0) -> epc;
      * sp(1) -> ra;
@@ -237,6 +244,7 @@ rt_hw_context_switch_exit:
     LOAD x13, 13 * REGBYTES(sp)
     LOAD x14, 14 * REGBYTES(sp)
     LOAD x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     LOAD x16, 16 * REGBYTES(sp)
     LOAD x17, 17 * REGBYTES(sp)
     LOAD x18, 18 * REGBYTES(sp)
@@ -255,6 +263,9 @@ rt_hw_context_switch_exit:
     LOAD x31, 31 * REGBYTES(sp)
 
     addi sp,  sp, 32 * REGBYTES
+#else
+    addi sp,  sp, 16 * REGBYTES
+#endif
 
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)

libcpu/risc-v/common/interrupt_gcc.S

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2023/01/17     WangShun    The first version
+ * 2023/03/19     Flyingcys    Add riscv_32e support
  */
 #define __ASSEMBLY__
 #include "cpuport.h"
@@ -58,7 +59,11 @@ SW_handler:
     FSTORE  f31, 31 * FREGBYTES(sp)
 #endif
     /* save all from thread context */
+#ifndef __riscv_32e
     addi sp, sp, -32 * REGBYTES
+#else
+    addi sp, sp, -16 * REGBYTES
+#endif
     STORE x5,   5 * REGBYTES(sp)
     STORE x1,   1 * REGBYTES(sp)
     /* Mandatory set the MPIE of mstatus */
@@ -75,6 +80,7 @@ SW_handler:
     STORE x13, 13 * REGBYTES(sp)
     STORE x14, 14 * REGBYTES(sp)
     STORE x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     STORE x16, 16 * REGBYTES(sp)
     STORE x17, 17 * REGBYTES(sp)
     STORE x18, 18 * REGBYTES(sp)
@@ -91,7 +97,7 @@ SW_handler:
     STORE x29, 29 * REGBYTES(sp)
     STORE x30, 30 * REGBYTES(sp)
     STORE x31, 31 * REGBYTES(sp)
-
+#endif
     /* switch to interrupt stack */
     csrrw sp,mscratch,sp
     /* interrupt handle */
@@ -104,22 +110,22 @@ SW_handler:
     csrrw sp,mscratch,sp
 
     /* Determine whether to trigger scheduling at the interrupt function */
-    la    s0, rt_thread_switch_interrupt_flag
-    lw    s2, 0(s0)
-    beqz  s2, 1f
+    la    t0, rt_thread_switch_interrupt_flag
+    lw    t2, 0(t0)
+    beqz  t2, 1f
     /* clear the flag of rt_thread_switch_interrupt_flag */
-    sw    zero, 0(s0)
+    sw    zero, 0(t0)
 
     csrr  a0, mepc
     STORE a0, 0 * REGBYTES(sp)
 
-    la    s0, rt_interrupt_from_thread
-    LOAD  s1, 0(s0)
-    STORE sp, 0(s1)
+    la    t0, rt_interrupt_from_thread
+    LOAD  t1, 0(t0)
+    STORE sp, 0(t1)
 
-    la    s0, rt_interrupt_to_thread
-    LOAD  s1, 0(s0)
-    LOAD  sp, 0(s1)
+    la    t0, rt_interrupt_to_thread
+    LOAD  t1, 0(t0)
+    LOAD  sp, 0(t1)
 
     LOAD  a0,  0 * REGBYTES(sp)
     csrw  mepc, a0
@@ -145,6 +151,7 @@ SW_handler:
     LOAD  x13, 13 * REGBYTES(sp)
     LOAD  x14, 14 * REGBYTES(sp)
     LOAD  x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     LOAD  x16, 16 * REGBYTES(sp)
     LOAD  x17, 17 * REGBYTES(sp)
     LOAD  x18, 18 * REGBYTES(sp)
@@ -163,6 +170,10 @@ SW_handler:
     LOAD  x31, 31 * REGBYTES(sp)
 
     addi  sp, sp, 32 * REGBYTES
+#else
+    addi  sp, sp, 16 * REGBYTES
+#endif
+
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)
     FLOAD   f1, 1 * FREGBYTES(sp)

libcpu/risc-v/common/rt_hw_stack_frame.h

@@ -31,6 +31,7 @@ typedef struct rt_hw_stack_frame
     rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
     rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
     rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
+#ifndef __riscv_32e
     rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
     rt_ubase_t a7;         /* x17 - a7     - function argument 7                 */
     rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
@@ -47,6 +48,7 @@ typedef struct rt_hw_stack_frame
     rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
     rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
     rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+#endif
 #ifdef ARCH_RISCV_FPU
     rv_floatreg_t f0;      /* f0  */
     rv_floatreg_t f1;      /* f1  */

libcpu/risc-v/common/trap_common.c

@@ -96,10 +96,12 @@ rt_weak void rt_show_stack_frame(void)
     rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
     rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
     rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
+#ifndef __riscv_32e
     rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
     rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
     rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
     rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
     rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
     rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
+#endif
 }