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提交 7b5fd81d 编写于 作者: I iysheng
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[bsp][gd32450z-eval] Update firmware library and delete usb relate library codes

上级 0949986c
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Showing with 10794 addition and 15443 deletion
bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c
浏览文件 @ 7b5fd81d
......@@ -56,7 +56,10 @@
#define SEL_IRC16M 0x00U
#define SEL_HXTAL 0x01U
#define SEL_PLLP 0x02U
#define RCU_MODIFY {volatile uint32_t i; \
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
for(i=0;i<50000;i++);}
/* set the system clock frequency and declare the system clock configuration function */
#ifdef __SYSTEM_CLOCK_IRC16M
uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M;
......@@ -109,10 +112,12 @@ void SystemInit (void)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Reset the RCU clock configuration to the default reset state ------------*/
/* Set IRC16MEN bit */
RCU_CTL |= RCU_CTL_IRC16MEN;
RCU_MODIFY
/* Reset CFG0 register */
RCU_CFG0 = 0x00000000U;
......@@ -131,8 +136,6 @@ void SystemInit (void)
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
system_clock_config();
}
/*!
\brief configure the system clock
......@@ -186,13 +189,12 @@ static void system_clock_16m_irc16m(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
}
while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
while(1){
}
while(1){
}
}
/* AHB = SYSCLK */
......@@ -230,13 +232,12 @@ static void system_clock_hxtal(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
/* AHB = SYSCLK */
......@@ -274,13 +275,12 @@ static void system_clock_120m_irc16m(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
}
while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -294,7 +294,7 @@ static void system_clock_120m_irc16m(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
/* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_IRC16M) | (5U << 24U));
......@@ -307,14 +307,12 @@ static void system_clock_120m_irc16m(void)
/* Enable the high-drive to extend the clock frequency to 120 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -345,13 +343,12 @@ static void system_clock_120m_8m_hxtal(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -365,7 +362,7 @@ static void system_clock_120m_8m_hxtal(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
/* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_HXTAL) | (5U << 24U));
......@@ -378,14 +375,12 @@ static void system_clock_120m_8m_hxtal(void)
/* Enable the high-drive to extend the clock frequency to 120 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -416,13 +411,12 @@ static void system_clock_120m_25m_hxtal(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -436,7 +430,7 @@ static void system_clock_120m_25m_hxtal(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
/* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_HXTAL) | (5U << 24U));
......@@ -449,14 +443,12 @@ static void system_clock_120m_25m_hxtal(void)
/* Enable the high-drive to extend the clock frequency to 120 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -487,13 +479,12 @@ static void system_clock_168m_irc16m(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
}
while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -507,7 +498,7 @@ static void system_clock_168m_irc16m(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
/* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_IRC16M) | (7U << 24U));
......@@ -520,14 +511,12 @@ static void system_clock_168m_irc16m(void)
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -559,8 +548,8 @@ static void system_clock_168m_8m_hxtal(void)
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -573,7 +562,7 @@ static void system_clock_168m_8m_hxtal(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
/* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) |
(RCU_PLLSRC_HXTAL) | (7 << 24U));
......@@ -586,14 +575,12 @@ static void system_clock_168m_8m_hxtal(void)
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -624,13 +611,12 @@ static void system_clock_168m_25m_hxtal(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -644,7 +630,7 @@ static void system_clock_168m_25m_hxtal(void)
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
/* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_HXTAL) | (7U << 24U));
......@@ -657,14 +643,12 @@ static void system_clock_168m_25m_hxtal(void)
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -695,13 +679,12 @@ static void system_clock_200m_irc16m(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
}
while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -715,7 +698,7 @@ static void system_clock_200m_irc16m(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
/* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_IRC16M) | (9U << 24U));
......@@ -728,14 +711,12 @@ static void system_clock_200m_irc16m(void)
/* Enable the high-drive to extend the clock frequency to 200 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -766,13 +747,12 @@ static void system_clock_200m_8m_hxtal(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -786,7 +766,7 @@ static void system_clock_200m_8m_hxtal(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
/* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_HXTAL) | (9U << 24U));
......@@ -799,14 +779,12 @@ static void system_clock_200m_8m_hxtal(void)
/* Enable the high-drive to extend the clock frequency to 200 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......@@ -837,13 +815,12 @@ static void system_clock_200m_25m_hxtal(void)
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
while(1){
}
}
RCU_APB1EN |= RCU_APB1EN_PMUEN;
......@@ -857,7 +834,7 @@ static void system_clock_200m_25m_hxtal(void)
/* APB1 = AHB/4 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
/* Configure the main PLL, PLL_M = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
/* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
(RCU_PLLSRC_HXTAL) | (9U << 24U));
......@@ -870,14 +847,12 @@ static void system_clock_200m_25m_hxtal(void)
/* Enable the high-drive to extend the clock frequency to 200 Mhz */
PMU_CTL |= PMU_CTL_HDEN;
while(0U == (PMU_CS & PMU_CS_HDRF))
{
while(0U == (PMU_CS & PMU_CS_HDRF)){
}
/* select the high-drive mode */
PMU_CTL |= PMU_CTL_HDS;
while(0U == (PMU_CS & PMU_CS_HDSRF))
{
while(0U == (PMU_CS & PMU_CS_HDSRF)){
}
/* select PLL as system clock */
......
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_crc.h
\brief definitions for the CRC
\file gd32f4xx_crc.h
\brief definitions for the CRC
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
2016-08-15, V1.0.0, firmware for GD32F4xx
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_CRC_H
......@@ -37,19 +62,19 @@
/* deinit CRC calculation unit */
void crc_deinit(void);
/* reset data register to the value of initializaiton data register */
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
void crc_data_register_reset(void);
/* read the data register */
/* read the value of the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
/* read the value of the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
/* write data to the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* CRC calculate a 32-bit data */
/* calculate the CRC value of a 32-bit data */
uint32_t crc_single_data_calculate(uint32_t sdata);
/* CRC calculate a 32-bit data array */
/* calculate the CRC value of an array of 32-bit values */
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
#endif /* GD32F4XX_CRC_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_ctc.h
\brief definitions for the CTC
\file gd32f4xx_ctc.h
\brief definitions for the CTC
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_CTC_H
......@@ -25,7 +50,7 @@
/* bits definitions */
/* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
......@@ -90,19 +115,19 @@
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
/* CTC interrupt enable definitions */
#define CTC_INT_CKOKIE CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
#define CTC_INT_CKWARNIE CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
#define CTC_INT_ERRIE CTC_CTL0_ERRIE /*!< error interrupt enable */
#define CTC_INT_EREFIE CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
/* CTC interrupt source definitions */
#define CTC_INT_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
#define CTC_INT_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
#define CTC_INT_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
#define CTC_INT_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
#define CTC_INT_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_INT_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_INT_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
/* CTC flag definitions */
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
......@@ -116,45 +141,30 @@
/* function declarations */
/* reset ctc clock trim controller */
void ctc_deinit(void);
/* enable the CTC interrupt */
void ctc_interrupt_enable(uint32_t ctc_interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t ctc_interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t ctc_interrupt);
/* get CTC flag */
FlagStatus ctc_flag_get(uint32_t ctc_flag);
/* clear CTC flag */
void ctc_flag_clear(uint32_t ctc_flag);
/* enable CTC trim counter */
void ctc_counter_enable(void);
/* disable CTC trim counter */
void ctc_counter_disable(void);
/* configure the IRC48M trim value */
void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value);
void ctc_irc48m_trim_value_config(uint8_t trim_value);
/* generate software reference source sync pulse */
void ctc_software_refsource_pulse_generate(void);
/* configure hardware automatically trim mode */
void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode);
/* enable CTC counter */
void ctc_counter_enable(void);
/* disable CTC counter */
void ctc_counter_disable(void);
void ctc_hardware_trim_mode_config(uint32_t hardmode);
/* configure reference signal source polarity */
void ctc_refsource_polarity_config(uint32_t ctc_polarity);
void ctc_refsource_polarity_config(uint32_t polarity);
/* select USBFS or USBHS SOF signal */
void ctc_usbsof_signal_select(uint32_t ctc_usbsof);
void ctc_usbsof_signal_select(uint32_t usbsof);
/* select reference signal source */
void ctc_refsource_signal_select(uint32_t ctc_refs);
void ctc_refsource_signal_select(uint32_t refs);
/* configure reference signal source prescaler */
void ctc_refsource_prescaler_config(uint32_t ctc_prescaler);
void ctc_refsource_prescaler_config(uint32_t prescaler);
/* configure clock trim base limit value */
void ctc_clock_limit_value_config(uint8_t ctc_limit_value);
void ctc_clock_limit_value_config(uint8_t limit_value);
/* configure CTC counter reload value */
void ctc_counter_reload_value_config(uint16_t ctc_reload_value);
void ctc_counter_reload_value_config(uint16_t reload_value);
/* read CTC counter capture value when reference sync pulse occurred */
uint16_t ctc_counter_capture_value_read(void);
......@@ -165,4 +175,18 @@ uint16_t ctc_counter_reload_value_read(void);
/* read the IRC48M trim value */
uint8_t ctc_irc48m_trim_value_read(void);
/* interrupt & flag functions */
/* enable the CTC interrupt */
void ctc_interrupt_enable(uint32_t interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t int_flag);
/* get CTC flag */
FlagStatus ctc_flag_get(uint32_t flag);
/* clear CTC flag */
void ctc_flag_clear(uint32_t flag);
#endif /* GD32F4XX_CTC_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_dbg.h
\brief definitions for the DBG
\file gd32f4xx_dbg.h
\brief definitions for the DBG
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_DBG_H
......@@ -65,30 +90,43 @@
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
/* define the peripheral debug hold bit position and its register index offset */
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
/* register index */
enum dbg_reg_idx
{
DBG_IDX_CTL0 = 0x04U,
DBG_IDX_CTL1 = 0x08U,
DBG_IDX_CTL2 = 0x0CU
};
typedef enum
{
DBG_TIMER1_HOLD = BIT(0), /*!< hold TIMER1 counter when core is halted */
DBG_TIMER2_HOLD = BIT(1), /*!< hold TIMER2 counter when core is halted */
DBG_TIMER3_HOLD = BIT(2), /*!< hold TIMER3 counter when core is halted */
DBG_TIMER4_HOLD = BIT(3), /*!< hold TIMER4 counter when core is halted */
DBG_TIMER5_HOLD = BIT(4), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = BIT(5), /*!< hold TIMER6 counter when core is halted */
DBG_TIMER11_HOLD = BIT(6), /*!< hold TIMER11 counter when core is halted */
DBG_TIMER12_HOLD = BIT(7), /*!< hold TIMER12 counter when core is halted */
DBG_TIMER13_HOLD = BIT(8), /*!< hold TIMER13 counter when core is halted */
DBG_RTC_HOLD = BIT(10), /*!< hold RTC calendar and wakeup counter when core is halted */
DBG_WWDGT_HOLD = BIT(11), /*!< debug WWDGT kept when core is halted */
DBG_FWDGT_HOLD = BIT(12), /*!< debug FWDGT kept when core is halted */
DBG_I2C0_HOLD = BIT(21), /*!< hold I2C0 smbus when core is halted */
DBG_I2C1_HOLD = BIT(22), /*!< hold I2C1 smbus when core is halted */
DBG_I2C2_HOLD = BIT(23), /*!< hold I2C2 smbus when core is halted */
DBG_CAN0_HOLD = BIT(25), /*!< debug CAN0 kept when core is halted */
DBG_CAN1_HOLD = BIT(26), /*!< debug CAN1 kept when core is halted */
DBG_TIMER0_HOLD = (BIT(0) | BIT(30)), /*!< hold TIMER0 counter when core is halted */
DBG_TIMER7_HOLD = (BIT(1) | BIT(30)), /*!< hold TIMER7 counter when core is halted */
DBG_TIMER8_HOLD = (BIT(16) | BIT(30)), /*!< hold TIMER8 counter when core is halted */
DBG_TIMER9_HOLD = (BIT(17) | BIT(30)), /*!< hold TIMER9 counter when core is halted */
DBG_TIMER10_HOLD = (BIT(18) | BIT(30)), /*!< hold TIMER10 counter when core is halted */
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */
DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */
DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */
DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */
DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */
}dbg_periph_enum;
#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6))
......@@ -98,6 +136,8 @@ typedef enum
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
/* function declarations */
/* deinitialize the DBG */
void dbg_deinit(void);
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
......
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_dci.h
\brief definitions for the DCI
\file gd32f4xx_dci.h
\brief definitions for the DCI
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_DCI_H
......@@ -32,17 +57,17 @@
/* bits definitions */
/* DCI_CTL */
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
#define DCI_CTL_JM BIT(3) /*!< jpeg mode */
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
#define DCI_CTL_DCIEN BIT(14) /*!< dci enable */
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
#define DCI_CTL_JM BIT(3) /*!< JPEG mode */
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */
/* DCI_STAT0 */
#define DCI_STAT0_HS BIT(0) /*!< HS line status */
......@@ -98,16 +123,16 @@
#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
/* constants definitions */
/* DCI parameter struct definitions */
/* DCI parameter structure definitions */
typedef struct
{
{
uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
uint32_t clock_polarity; /*!< clock polarity selection */
uint32_t hsync_polarity; /*!< horizontal polarity selection */
uint32_t vsync_polarity; /*!< vertical polarity selection */
uint32_t frame_rate; /*!< frame capture rate */
uint32_t interface_format; /*!< digital camera interface format */
}dci_parameter_struct;
}dci_parameter_struct;
#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
......@@ -120,36 +145,44 @@ typedef struct
#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
/* DCI interrupt constants definitions */
#define DCI_INT_EF ((uint32_t)0x00000001U) /*!< end of frame interrupt */
#define DCI_INT_OVR ((uint32_t)0x00000002U) /*!< FIFO overrun interrupt */
#define DCI_INT_ESE ((uint32_t)0x00000004U) /*!< embedded synchronous error interrupt */
#define DCI_INT_VS ((uint32_t)0x00000008U) /*!< vsync interrupt */
#define DCI_INT_EL ((uint32_t)0x00000010U) /*!< end of line interrupt */
/* DCI flag definitions */
#define DCI_FLAG_HS ((uint8_t)0x01U) /*!< HS line status */
#define DCI_FLAG_VS ((uint8_t)0x02U) /*!< VS line status */
#define DCI_FLAG_FV ((uint8_t)0x03U) /*!< FIFO valid */
#define DCI_FLAG_EFF ((uint8_t)0x04U) /*!< end of frame flag */
#define DCI_FLAG_OVRF ((uint8_t)0x05U) /*!< FIFO overrun flag */
#define DCI_FLAG_ESEF ((uint8_t)0x06U) /*!< embedded synchronous error flag */
#define DCI_FLAG_VSF ((uint8_t)0x07U) /*!< vsync flag */
#define DCI_FLAG_ELF ((uint8_t)0x08U) /*!< end of line flag */
#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */
#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */
#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */
#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */
#define DCI_INT_EL BIT(4) /*!< end of line interrupt */
/* DCI interrupt flag definitions */
#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */
#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */
#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */
#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */
#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */
/* DCI flag definitions */
#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */
#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */
#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */
#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */
#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */
#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */
#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */
#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */
/* function declarations */
/* initialization functions */
/* DCI deinit */
void dci_deinit(void);
/* initialize DCI registers */
......@@ -157,44 +190,49 @@ void dci_init(dci_parameter_struct* dci_struct);
/* enable DCI function */
void dci_enable(void);
/* disble DCI function */
/* disable DCI function */
void dci_disable(void);
/* enable DCI capture */
void dci_capture_enable(void);
/* disble DCI capture */
/* disable DCI capture */
void dci_capture_disable(void);
/* enable DCI jpeg mode */
void dci_jpeg_enable(void);
/* disble DCI jpeg mode */
/* disable DCI jpeg mode */
void dci_jpeg_disable(void);
/* function configuration */
/* enable cropping window function */
void dci_crop_window_enable(void);
/* disble cropping window function */
/* disable cropping window function */
void dci_crop_window_disable(void);
/* config DCI cropping window */
/* configure DCI cropping window */
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
/* enable sync codes function */
void dci_sync_codes_enable(void);
/* disble sync codes function */
void dci_sync_codes_disable(void);
/* config sync codes */
/* enable embedded synchronous mode */
void dci_embedded_sync_enable(void);
/* disable embedded synchronous mode */
void dci_embedded_sync_disable(void);
/* configure synchronous codes in embedded synchronous mode */
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
/* config sync codes unmask */
/* configure synchronous codes unmask in embedded synchronous mode */
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
/* read DCI data register */
uint32_t dci_data_read(void);
/* interrupt & flag functions */
/* get specified flag */
FlagStatus dci_flag_get(uint32_t flag);
/* enable specified DCI interrupt */
void dci_interrupt_enable(uint32_t interrupt);
/* disble specified DCI interrupt */
/* disable specified DCI interrupt */
void dci_interrupt_disable(uint32_t interrupt);
/* clear specified interrupt */
void dci_interrupt_clear(uint32_t interrupt);
/* get specified flag */
FlagStatus dci_flag_get(uint32_t flag);
/* get specified interrupt flag */
FlagStatus dci_interrupt_flag_get(uint32_t interrupt);
FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
/* clear specified interrupt flag */
void dci_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32F4XX_DCI_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_dma.h
\brief definitions for the DMA
\file gd32f4xx_dma.c
\brief definitions for the DMA
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_DMA_H
......@@ -123,10 +148,10 @@
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
/* DMA_CHxM0ADDR,x=0..7 */
#define DMA_CHXM0ADDR_PADDR BITS(0,31) /*!< memory 0 base address */
#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */
/* DMA_CHxM1ADDR,x=0..7 */
#define DMA_CHXM1ADDR_PADDR BITS(0,31) /*!< memory 1 base address */
#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */
/* DMA_CHxFCTL,x=0..7 */
#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */
......@@ -136,7 +161,7 @@
/* constants definitions */
/* DMA channel select */
typedef enum
typedef enum
{
DMA_CH0 = 0, /*!< DMA Channel 0 */
DMA_CH1, /*!< DMA Channel 1 */
......@@ -149,7 +174,7 @@ typedef enum
} dma_channel_enum;
/* DMA peripheral select */
typedef enum
typedef enum
{
DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */
DMA_SUBPERI1, /*!< DMA Peripheral 1 */
......@@ -166,7 +191,7 @@ typedef struct
{
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t periph_inc; /*!< peripheral increasing mode */
uint32_t periph_inc; /*!< peripheral increasing mode */
uint32_t memory0_addr; /*!< memory 0 base address */
uint32_t memory_width; /*!< transfer data size of memory */
......@@ -176,7 +201,7 @@ typedef struct
uint32_t periph_burst_width; /*!< multi data mode enable */
uint32_t critical_value; /*!< FIFO critical */
uint32_t circular_mode;
uint32_t circular_mode; /*!< DMA circular mode */
uint32_t direction; /*!< channel data transfer direction */
uint32_t number; /*!< channel transfer number */
uint32_t priority; /*!< channel priority level */
......@@ -186,7 +211,7 @@ typedef struct
typedef struct
{
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_inc; /*!< peripheral increasing mode */
uint32_t periph_inc; /*!< peripheral increasing mode */
uint32_t memory0_addr; /*!< memory 0 base address */
uint32_t memory_inc; /*!< memory increasing mode */
......@@ -296,85 +321,108 @@ typedef struct
#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */
/* DMA reset value */
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */
#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */
#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */
/* DMA_INTF register */
/* interrupt flag bits */
#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
/* flag bits */
#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
/* function declarations */
/* DMA deinitialization and initialization functions */
/* deinitialize DMA a channel registers */
void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx);
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
/* initialize the DMA single data mode parameters struct with the default values */
void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct);
/* initialize the DMA multi data mode parameters struct with the default values */
void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct);
/* DMA single data mode initialize */
void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct);
void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct);
/* DMA multi data mode initialize */
void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct);
void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct);
/* DMA configuration functions */
/* set DMA peripheral base address */
void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address);
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
/* set DMA Memory base address */
void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address);
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address);
/* set the number of remaining data to be transferred by the DMA */
void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number);
void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number);
/* get the number of remaining data to be transferred by the DMA */
uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx);
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
/* configure priority level of DMA channel */
void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority);
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
/* configure transfer burst beats of memory */
void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat);
void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat);
/* configure transfer burst beats of peripheral */
void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat);
void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat);
/* configure transfer data size of memory */
void dma_memory_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize);
void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize);
/* configure transfer data size of peripheral */
void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize);
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize);
/* configure next address increasement algorithm of memory */
void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm);
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
/* configure next address increasement algorithm of peripheral */
void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm);
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
/* enable DMA circulation mode */
void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx);
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable DMA circulation mode */
void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx);
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable DMA channel */
void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx);
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable DMA channel */
void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx);
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* configure the direction of data transfer on the channel */
void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction);
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
/* DMA switch buffer mode config */
void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select);
void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select);
/* DMA using memory get */
uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx);
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx);
/* DMA channel peripheral select */
void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph);
void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph);
/* DMA flow controller configure */
void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller);
void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller);
/* DMA flow controller enable */
void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue);
void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue);
/* DMA FIFO status get */
uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx);
uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx);
/* flag and interrupt functions */
/* check DMA flag is set or not */
FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag);
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* clear DMA a channel flag */
void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag);
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* check DMA flag is set or not */
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt);
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
/* clear DMA a channel flag */
void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt);
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
/* enable DMA interrupt */
void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source);
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
/* disable DMA interrupt */
void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source);
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
#endif /* GD32F4XX_DMA_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_exti.h
\brief definitions for the EXTI
\file gd32f4xx_exti.h
\brief definitions for the EXTI
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.1, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
2016-08-15, V1.0.0, firmware for GD32F4xx
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_EXTI_H
......@@ -97,6 +122,7 @@
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */
......@@ -121,6 +147,7 @@
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */
......@@ -145,6 +172,7 @@
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
......@@ -169,13 +197,14 @@
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */
/* constants definitions */
/* EXTI line number */
typedef enum
{
{
EXTI_0 = BIT(0), /*!< EXTI line 0 */
EXTI_1 = BIT(1), /*!< EXTI line 1 */
EXTI_2 = BIT(2), /*!< EXTI line 2 */
......@@ -196,7 +225,7 @@ typedef enum
EXTI_17 = BIT(17), /*!< EXTI line 17 */
EXTI_18 = BIT(18), /*!< EXTI line 18 */
EXTI_19 = BIT(19), /*!< EXTI line 19 */
EXTI_20 = BIT(20), /*!< EXTI line 20 */
EXTI_20 = BIT(20), /*!< EXTI line 20 */
EXTI_21 = BIT(21), /*!< EXTI line 21 */
EXTI_22 = BIT(22), /*!< EXTI line 22 */
}exti_line_enum;
......@@ -210,10 +239,11 @@ typedef enum
/* interrupt trigger mode */
typedef enum
{
{
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
EXTI_TRIG_NONE /*!< none EXTI edge trigger */
}exti_trig_type_enum;
/* function declarations */
......@@ -223,13 +253,18 @@ void exti_deinit(void);
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
/* enable the interrupts from EXTI line x */
void exti_interrupt_enable(exti_line_enum linex);
/* enable the events from EXTI line x */
void exti_event_enable(exti_line_enum linex);
/* disable the interrupts from EXTI line x */
void exti_interrupt_disable(exti_line_enum linex);
/* enable the events from EXTI line x */
void exti_event_enable(exti_line_enum linex);
/* disable the events from EXTI line x */
void exti_event_disable(exti_line_enum linex);
/* EXTI software interrupt event enable */
void exti_software_interrupt_enable(exti_line_enum linex);
/* EXTI software interrupt event disable */
void exti_software_interrupt_disable(exti_line_enum linex);
/* interrupt & flag functions */
/* get EXTI lines pending flag */
FlagStatus exti_flag_get(exti_line_enum linex);
/* clear EXTI lines pending flag */
......@@ -238,9 +273,5 @@ void exti_flag_clear(exti_line_enum linex);
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
/* clear EXTI lines pending flag */
void exti_interrupt_flag_clear(exti_line_enum linex);
/* EXTI software interrupt event enable */
void exti_software_interrupt_enable(exti_line_enum linex);
/* EXTI software interrupt event disable */
void exti_software_interrupt_disable(exti_line_enum linex);
#endif /* GD32F4XX_EXTI_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_fmc.h
\brief definitions for the FMC
\file gd32f4xx_fmc.h
\brief definitions for the FMC
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_FMC_H
#define GD32F4XX_FMC_H
......@@ -18,15 +45,15 @@
#define OB OB_BASE /*!< option byte base address */
/* registers definitions */
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option byte unlock key register */
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
#define FMC_OBCTL0 REG32((FMC) + 0x14U) /*!< FMC option byte control register 0 */
#define FMC_OBCTL1 REG32((FMC) + 0x18U) /*!< FMC option byte control register 1 */
#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */
#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */
#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */
#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */
#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */
#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */
#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */
#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */
#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */
#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/
......@@ -98,7 +125,6 @@ typedef enum
FMC_WPERR, /*!< erase/program protection error */
FMC_OPERR, /*!< operation error */
FMC_PGERR, /*!< program error */
FMC_TOERR /*!< timeout error */
}fmc_state_enum;
/* unlock key */
......@@ -108,9 +134,6 @@ typedef enum
#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */
#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */
/* FMC time out */
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000) /*!< enable FMC error timeout */
/* option byte write protection */
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
......@@ -146,7 +169,7 @@ typedef enum
#define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */
#define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */
/* option byte software/hardware free watch dog timer */
/* option byte software/hardware free watch dog timer */
#define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5)
#define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */
#define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */
......@@ -179,19 +202,19 @@ typedef enum
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
#define OB_WP_12 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 12 */
#define OB_WP_13 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 13 */
#define OB_WP_14 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 14 */
#define OB_WP_15 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 15 */
#define OB_WP_16 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 16 */
#define OB_WP_17 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 17 */
#define OB_WP_18 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 18 */
#define OB_WP_19 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 19 */
#define OB_WP_20 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 20 */
#define OB_WP_21 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 21 */
#define OB_WP_22 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 22 */
#define OB_WP_23_30 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 23~30 */
#define OB_WP_ALL ((uint32_t)0x00000FFFU) /*!< erase/program protection of all sectors */
#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */
#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */
#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */
#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */
#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */
#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */
#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */
#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */
#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */
#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */
#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */
#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */
#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */
/* option bytes D-bus read protection */
#define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */
......@@ -206,26 +229,25 @@ typedef enum
#define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */
#define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */
#define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */
#define OB_DRP_12 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 12 */
#define OB_DRP_13 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 13 */
#define OB_DRP_14 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 14 */
#define OB_DRP_15 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 15 */
#define OB_DRP_16 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 16 */
#define OB_DRP_17 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 17 */
#define OB_DRP_18 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 18 */
#define OB_DRP_19 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 19 */
#define OB_DRP_20 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 20 */
#define OB_DRP_21 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 21 */
#define OB_DRP_22 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 22 */
#define OB_DRP_23_30 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 23~30 */
#define OB_DRP_ALL ((uint32_t)0x00000FFFU) /*!< D-bus read protection protection of all sectors */
/* double banks or single bank selection when flash size is 1M bytes */
#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */
#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */
#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */
#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */
#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */
#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */
#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */
#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */
#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */
#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */
#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */
#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */
/* double banks or single bank selection when flash size is 1M bytes */
#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30))
#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */
#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */
/* option bytes D-bus read protection mode */
/* option bytes D-bus read protection mode */
#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31))
#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */
#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */
......@@ -260,19 +282,17 @@ typedef enum
#define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */
#define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */
#define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */
#define CTL_SECTOR_NUMBER_28 CTL_SN(28) /*!< sector 28 */
#define CTL_SECTOR_NUMBER_29 CTL_SN(29) /*!< sector 29 */
#define CTL_SECTOR_NUMBER_30 CTL_SN(30) /*!< sector 30 */
/* FMC program size */
/* FMC program size */
#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8)
#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */
#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */
#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */
/* FMC interrupt enable */
#define FMC_INTEN_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */
#define FMC_INTEN_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */
#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */
#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */
/* FMC flags */
#define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */
......@@ -281,7 +301,7 @@ typedef enum
#define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */
#define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */
#define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */
#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */
#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */
/* function declarations */
/* FMC main memory programming functions */
......@@ -313,25 +333,17 @@ void ob_unlock(void);
void ob_lock(void);
/* send option byte change command */
void ob_start(void);
/* erase option byte */
void ob_erase(void);
/* enable write protect */
void ob_write_protection0_enable(uint32_t ob_wp);
/* disable write protect */
void ob_write_protection0_disable(uint32_t ob_wp);
/* enable write protect */
void ob_write_protection1_enable(uint32_t ob_wp);
void ob_write_protection_enable(uint32_t ob_wp);
/* disable write protect */
void ob_write_protection1_disable(uint32_t ob_wp);
/* configure the erase/program protection mode */
void ob_drp_config(uint32_t ob_drp);
/* enable the erase/program protection mode */
void ob_drp0_enable(uint32_t ob_drp);
/* disable the erase/program protection mode */
void ob_drp0_disable(uint32_t ob_drp);
/* enable the erase/program protection mode */
void ob_drp1_enable(uint32_t ob_drp);
/* disable the erase/program protection mode */
void ob_drp1_disable(uint32_t ob_drp);
/* set the option byte security protection level */
void ob_write_protection_disable(uint32_t ob_wp);
/* enable erase/program protection and D-bus read protection */
void ob_drp_enable(uint32_t ob_drp);
/* disable erase/program protection and D-bus read protection */
void ob_drp_disable(uint32_t ob_drp);
/* set the option byte security protection level */
void ob_security_protection_config(uint8_t ob_spc);
/* write the FMC option byte user */
void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby);
......@@ -366,6 +378,6 @@ void fmc_flag_clear(uint32_t fmc_flag);
/* return the FMC state */
fmc_state_enum fmc_state_get(void);
/* check FMC ready or not */
fmc_state_enum fmc_ready_wait(uint32_t count);
fmc_state_enum fmc_ready_wait(void);
#endif /* GD32F4XX_FMC_H */
bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h
浏览文件 @ 7b5fd81d
/*!
\file gd32f4xx_fwdgt.h
\brief definitions for the FWDGT
\file gd32f4xx_fwdgt.h
\brief definitions for the FWDGT
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F4XX_FWDGT_H
......@@ -58,7 +83,13 @@
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
/* function declarations */
/* enable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_enable(void);
/* disable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_disable(void);
/* start the free watchdog timer counter */
......
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