Merge remote-tracking branch 'rtt_gitee/gitee_master'

bsp/v85xxp/.ignore_format.yml

+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- Libraries/VangoV85xxP_standard_peripheral

bsp/v85xxp/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default: "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_SERIES_V85XXP
+    bool
+    default y
+
+config SOC_V85XXP
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select SOC_SERIES_V85XXP
+    default y
+
+menu "On-chip Peripheral Drivers"
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "using uart0"
+                default n
+            config BSP_USING_UART1
+                bool "using uart1"
+                default n
+            config BSP_USING_UART2
+                bool "using uart2"
+                default y
+            config BSP_USING_UART3
+                bool "using uart3"
+                default n
+            config BSP_USING_UART4
+                bool "using uart4"
+                default n
+            config BSP_USING_UART5
+                bool "using uart5"
+                default n
+        endif
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC0
+                bool "using adc0"
+                default n
+        endif
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable hwtimer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_HWTIMER0
+                bool "using hwtimer0"
+                default n
+            config BSP_USING_HWTIMER1
+                bool "using hwtimer1"
+                default n
+            config BSP_USING_HWTIMER2
+                bool "using hwtimer2"
+                default n
+            config BSP_USING_HWTIMER3
+                bool "using hwtimer3"
+                default n
+        endif
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    config BSP_USING_RTC
+        bool "using internal rtc"
+        default n
+        select RT_USING_RTC
+
+endmenu

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_CodeRAM.h

+/**
+  ******************************************************************************
+  * @file    lib_CodeRAM.h 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Codes executed in SRAM.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_CODERAM_H
+#define __LIB_CODERAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"   
+
+#ifndef __GNUC__
+
+#ifdef __ICCARM__          /* EWARM */
+  #define __RAM_FUNC       __ramfunc
+#endif
+
+#ifdef __CC_ARM            /* MDK-ARM */
+  #define __RAM_FUNC       __attribute__((used))
+#endif
+
+/* Exported Functions ------------------------------------------------------- */
+
+__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
+
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CODERAM_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_LoadNVR.h

+/**
+  ******************************************************************************
+  * @file    lib_LoadNVR.h 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Load information from NVR.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_LOADNVR_H
+#define __LIB_LOADNVR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"
+
+/* Power Measure Result */
+typedef struct
+{
+  uint32_t  AVCCMEAResult;  // LDO33 Measure Result
+  uint32_t  DVCCMEAResult;  // LDO15 Measure Result
+  uint32_t  BGPMEAResult;    // BGP Measure Result
+  uint32_t  RCLMEAResult;    // RCL Measure Result
+  uint32_t  RCHMEAResult;    // RCH Measure Result
+} NVR_MISCGain;
+
+/* Chip ID */
+typedef struct
+{
+  uint32_t  ChipID0;        // ID word 0
+  uint32_t  ChipID1;        // ID word 1
+} NVR_CHIPID;
+
+/* Temperature information */
+typedef struct
+{
+  float  TempOffset; 
+} NVR_TEMPINFO;
+
+/* LCD information */
+typedef struct
+{
+  uint32_t  MEALCDLDO;     // Measure LCD LDO pre trim value
+  uint32_t  MEALCDVol;     // VLCD setting
+} NVR_LCDINFO;
+
+/* RTC(temp) information */
+typedef struct
+{
+  int16_t RTCTempP0; //P0
+  int16_t RTCTempP1; //P1
+  int32_t RTCTempP2; //P2
+  int16_t RTCTempP4; //P4
+  int16_t RTCTempP5; //P5
+  int16_t RTCTempP6; //P6
+  int16_t RTCTempP7; //P7 
+  int16_t RTCTempK0; //K0
+  int16_t RTCTempK1; //K1
+  int16_t RTCTempK2; //K2
+  int16_t RTCTempK3; //K3
+  int16_t RTCTempK4; //K4
+  int16_t RTCACTI;      //Center temperature
+  uint32_t RTCACKTemp;  //section X temperature
+  int32_t RTCTempDelta; //Temperature delta
+  uint32_t RTCACF200;   //RTC_ACF200
+} NVR_RTCINFO;
+
+/* RTC(temp) information */
+typedef struct
+{
+  int16_t RTCTempP0; //P0
+  int16_t RTCTempP1; //P1
+  int32_t RTCTempP2; //P2
+} NVR_TempParams;
+
+/* ADC Voltage Parameters */
+typedef struct
+{
+  float aParameter;
+  float bParameter;
+  float OffsetParameter;
+} NVR_ADCVOLPARA;
+//Mode
+#define NVR_3V_EXTERNAL_NODIV    (0x000UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: None
+#define NVR_3V_EXTERNAL_RESDIV   (0x001UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: Resistive
+#define NVR_3V_BAT1_RESDIV       (0x002UL)    // Power supply: 3.3V;    Channel: VDD;         Divider modeL: Resistive
+#define NVR_3V_BATRTC_RESDIV     (0x003UL)    // Power supply: 3.3V;    Channel: BATRTC;      Divider modeL: Resistive
+#define NVR_5V_EXTERNAL_NODIV    (0x100UL)    // Power supply: 5V;      Channel: External;    Divider modeL: None
+#define NVR_5V_EXTERNAL_RESDIV   (0x101UL)    // Power supply: 5V;      Channel: External;    Divider modeL: Resistive
+#define NVR_5V_BAT1_RESDIV       (0x102UL)    // Power supply: 5V;      Channel: VDD;         Divider modeL: Resistive
+#define NVR_5V_BATRTC_RESDIV     (0x103UL)    // Power supply: 5V;      Channel: BATRTC;      Divider modeL: Resistive
+#define IS_NVR_ADCVOL_MODE(__MODE__)  (((__MODE__) == NVR_3V_EXTERNAL_NODIV)   ||\
+                                       ((__MODE__) == NVR_3V_EXTERNAL_RESDIV)  ||\
+                                       ((__MODE__) == NVR_3V_BAT1_RESDIV)       ||\
+                                       ((__MODE__) == NVR_3V_BATRTC_RESDIV)    ||\
+                                       ((__MODE__) == NVR_5V_EXTERNAL_NODIV)   ||\
+                                       ((__MODE__) == NVR_5V_EXTERNAL_RESDIV)  ||\
+                                       ((__MODE__) == NVR_5V_BAT1_RESDIV)       ||\
+                                       ((__MODE__) == NVR_5V_BATRTC_RESDIV))
+
+//VOLMode
+#define NVR_MEARES_3V      0
+#define NVR_MEARES_5V      1
+#define IS_MEARES(__VOLMODE__)     (((__VOLMODE__) == NVR_MEARES_3V)   ||\
+                                    ((__VOLMODE__) == NVR_MEARES_5V))
+/********** NVR Address **********/
+//ADC Voltage Parameters
+#define NVR_3VPARA_BASEADDR1          (__IO uint32_t *)(0x80C48)
+#define NVR_3VPARA_BASEADDR2          (__IO uint32_t *)(0x80C6C)
+#define NVR_5VPARA_BASEADDR1          (__IO uint32_t *)(0x80C00)
+#define NVR_5VPARA_BASEADDR2          (__IO uint32_t *)(0x80C24)
+//RTC DATA
+//P4
+#define NVR_RTC1_P4                   (__IO uint32_t *)(0x80800)
+#define NVR_RTC1_P4_CHKSUM            (__IO uint32_t *)(0x80804)
+#define NVR_RTC2_P4                   (__IO uint32_t *)(0x80808)
+#define NVR_RTC2_P4_CHKSUM            (__IO uint32_t *)(0x8080C)
+//ACK1~ACK5
+#define NVR_RTC1_ACK0                 (__IO uint32_t *)(0x80810)
+#define NVR_RTC1_ACK1                 (__IO uint32_t *)(0x80814)
+#define NVR_RTC1_ACK2                 (__IO uint32_t *)(0x80818)
+#define NVR_RTC1_ACK3                 (__IO uint32_t *)(0x8081C)
+#define NVR_RTC1_ACK4                 (__IO uint32_t *)(0x80820)
+#define NVR_RTC1_ACK_CHKSUM           (__IO uint32_t *)(0x80824)
+#define NVR_RTC2_ACK0                 (__IO uint32_t *)(0x80828)
+#define NVR_RTC2_ACK1                 (__IO uint32_t *)(0x8082C)
+#define NVR_RTC2_ACK2                 (__IO uint32_t *)(0x80830)
+#define NVR_RTC2_ACK3                 (__IO uint32_t *)(0x80834)
+#define NVR_RTC2_ACK4                 (__IO uint32_t *)(0x80838)
+#define NVR_RTC2_ACK_CHKSUM           (__IO uint32_t *)(0x8083C)
+//ACTI
+#define NVR_RTC1_ACTI                 (__IO uint32_t *)(0x80840)
+#define NVR_RTC1_ACTI_CHKSUM          (__IO uint32_t *)(0x80844)
+#define NVR_RTC2_ACTI                 (__IO uint32_t *)(0x80848)
+#define NVR_RTC2_ACTI_CHKSUM          (__IO uint32_t *)(0x8084C)
+//ACKTEMP
+#define NVR_RTC1_ACKTEMP              (__IO uint32_t *)(0x80850)
+#define NVR_RTC1_ACKTEMP_CHKSUM       (__IO uint32_t *)(0x80854)
+#define NVR_RTC2_ACKTEMP              (__IO uint32_t *)(0x80858)
+#define NVR_RTC2_ACKTEMP_CHKSUM       (__IO uint32_t *)(0x8085C)
+//Analog trim data
+#define NVR_ANA_TRIMDATA1             (__IO uint32_t *)(0x80DC0)
+#define NVR_ANA_OPREG1                (__IO uint32_t *)(0x80DC4)
+#define NVR_ANA_KEYREG1               (__IO uint32_t *)(0x80DC8)
+#define NVR_ANA_CHECKSUM1             (__IO uint32_t *)(0x80DCC)
+#define NVR_ANA_TRIMDATA2             (__IO uint32_t *)(0x80DD0)
+#define NVR_ANA_OPREG2                (__IO uint32_t *)(0x80DD4)
+#define NVR_ANA_KEYREG2               (__IO uint32_t *)(0x80DD8)
+#define NVR_ANA_CHECKSUM2             (__IO uint32_t *)(0x80DDC)
+#define NVR_ANA1_REG10                (__IO uint32_t *)(0x80DE0)
+#define NVR_ANA1_REG10_CHKSUM         (__IO uint32_t *)(0x80DE4)
+#define NVR_ANA2_REG10                (__IO uint32_t *)(0x80DE8)
+#define NVR_ANA2_REG10_CHKSUM         (__IO uint32_t *)(0x80DEC)
+//ADC_CHx
+#define NVR_5VADCCHx_NODIV1           (__IO uint32_t *)(0x80C90)
+#define NVR_5VADCCHx_RESDIV1          (__IO uint32_t *)(0x80C94)
+#define NVR_5VADCCHx_NODIV2           (__IO uint32_t *)(0x80CA4)
+#define NVR_5VADCCHx_RESDIV2          (__IO uint32_t *)(0x80CA8)
+#define NVR_3VADCCHx_NODIV1           (__IO uint32_t *)(0x80CB8)
+#define NVR_3VADCCHx_RESDIV1          (__IO uint32_t *)(0x80CBC)
+#define NVR_3VADCCHx_NODIV2           (__IO uint32_t *)(0x80CCC)
+#define NVR_3VADCCHx_RESDIV2          (__IO uint32_t *)(0x80CD0)
+//BAT Measure Result 
+#define NVR_5VBAT1                    (__IO uint32_t *)(0x80C98)
+#define NVR_5VBATRTC1                 (__IO uint32_t *)(0x80C9C)
+#define NVR_5VBATCHKSUM1              (__IO uint32_t *)(0x80CA0)
+#define NVR_5VBAT2                    (__IO uint32_t *)(0x80CAC)
+#define NVR_5VBATRTC2                 (__IO uint32_t *)(0x80CB0)
+#define NVR_5VBATCHKSUM2              (__IO uint32_t *)(0x80CB4)
+#define NVR_3VBAT1                    (__IO uint32_t *)(0x80CC0)
+#define NVR_3VBATRTC1                 (__IO uint32_t *)(0x80CC4)
+#define NVR_3VBATCHKSUM1              (__IO uint32_t *)(0x80CC8)
+#define NVR_3VBAT2                    (__IO uint32_t *)(0x80CD4)
+#define NVR_3VBATRTC2                 (__IO uint32_t *)(0x80CD8)
+#define NVR_3VBATCHKSUM2              (__IO uint32_t *)(0x80CDC)
+//RTC AutoCal Px pramameters
+#define NVR_RTC1_P1_P0                (__IO uint32_t *)(0x80D10)
+#define NVR_RTC1_P2                   (__IO uint32_t *)(0x80D14)
+#define NVR_RTC1_P5_P4                (__IO uint32_t *)(0x80D18)
+#define NVR_RTC1_P7_P6                (__IO uint32_t *)(0x80D1C)
+#define NVR_RTC1_PCHECHSUM            (__IO uint32_t *)(0x80D20)
+#define NVR_RTC2_P1_P0                (__IO uint32_t *)(0x80D24)
+#define NVR_RTC2_P2                   (__IO uint32_t *)(0x80D28)
+#define NVR_RTC2_P5_P4                (__IO uint32_t *)(0x80D2C)
+#define NVR_RTC2_P7_P6                (__IO uint32_t *)(0x80D30)
+#define NVR_RTC2_PCHECHSUM            (__IO uint32_t *)(0x80D34)
+//Power Measure Result
+#define NVR_AVCC_MEA1                 (__IO uint32_t *)(0x80D38)
+#define NVR_DVCC_MEA1                 (__IO uint32_t *)(0x80D3C)
+#define NVR_BGP_MEA1                  (__IO uint32_t *)(0x80D40)
+#define NVR_RCL_MEA1                  (__IO uint32_t *)(0x80D44)
+#define NVR_RCH_MEA1                  (__IO uint32_t *)(0x80D48)
+#define NVR_PWR_CHECKSUM1             (__IO uint32_t *)(0x80D4C)
+#define NVR_AVCC_MEA2                 (__IO uint32_t *)(0x80D50)
+#define NVR_DVCC_MEA2                 (__IO uint32_t *)(0x80D54)
+#define NVR_BGP_MEA2                  (__IO uint32_t *)(0x80D58)
+#define NVR_RCL_MEA2                  (__IO uint32_t *)(0x80D5C)
+#define NVR_RCH_MEA2                  (__IO uint32_t *)(0x80D60)
+#define NVR_PWR_CHECKSUM2             (__IO uint32_t *)(0x80D64)
+//Chip ID
+#define NVR_CHIP1_ID0                 (__IO uint32_t *)(0x80D68)
+#define NVR_CHIP1_ID1                 (__IO uint32_t *)(0x80D6C)
+#define NVR_CHIP1_CHECKSUM            (__IO uint32_t *)(0x80D70)
+#define NVR_CHIP2_ID0                 (__IO uint32_t *)(0x80D74)
+#define NVR_CHIP2_ID1                 (__IO uint32_t *)(0x80D78)
+#define NVR_CHIP2_CHECKSUM            (__IO uint32_t *)(0x80D7C)
+//Temperature information
+#define NVR_REALTEMP1                 (__IO uint32_t *)(0x80D80)
+#define NVR_MEATEMP1                  (__IO uint32_t *)(0x80D84)
+#define NVR_TEMP_CHECKSUM1            (__IO uint32_t *)(0x80D88)
+#define NVR_REALTEMP2                 (__IO uint32_t *)(0x80D9C)
+#define NVR_MEATEMP2                  (__IO uint32_t *)(0x80D90)
+#define NVR_TEMP_CHECKSUM2            (__IO uint32_t *)(0x80D94)
+
+uint32_t NVR_LoadANADataManual(void);
+uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData, uint32_t DivCLKSource);
+uint32_t NVR_GetVoltageParameters(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
+uint32_t NVR_GetTempParameters(NVR_TempParams *TempParams);
+uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
+uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_LOADNVR_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_conf.h

+/**
+  ******************************************************************************
+  * @file    lib_conf.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Dirver configuration.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_CONF_H
+#define __LIB_CONF_H
+
+/* ########################## Assert Selection ############################## */
+
+//#define ASSERT_NDEBUG    1
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+#include "lib_ana.h"
+#include "lib_adc.h"
+#include "lib_adc_tiny.h"
+#include "lib_clk.h"
+#include "lib_cmp.h"
+#include "lib_crypt.h"
+#include "lib_dma.h"
+#include "lib_flash.h"
+#include "lib_gpio.h"
+#include "lib_i2c.h"
+#include "lib_iso7816.h"
+#include "lib_lcd.h"
+#include "lib_misc.h"
+#include "lib_pmu.h"
+#include "lib_pwm.h"
+#include "lib_rtc.h"
+#include "lib_spi.h"
+#include "lib_tmr.h"
+#include "lib_u32k.h"
+#include "lib_uart.h"
+#include "lib_version.h"
+#include "lib_wdt.h"
+#include "lib_LoadNVR.h"
+#include "lib_CodeRAM.h"
+#include "lib_cortex.h"
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef  ASSERT_NDEBUG
+  #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_errhandler(uint8_t* file, uint32_t line);
+#else
+  #define assert_parameters(expr) ((void)0U)
+#endif /* ASSERT_NDEBUG */ 
+
+#endif
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/lib_cortex.h

+/**
+  ******************************************************************************
+  * @file    lib_Cortex.h 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Cortex module driver.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_CORTEX_H
+#define __LIB_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"   
+
+
+#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
+   
+#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x4)
+   
+/* Exported Functions ------------------------------------------------------- */
+void     CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
+   
+void     CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
+void     CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
+void     CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
+void     CORTEX_NVIC_SystemReset(void);
+uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
+void     CORTEX_Delay_nSysClock(__IO uint32_t nClock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CORTEX_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/system_target.h

+/**
+  ******************************************************************************
+  * @file    system_target.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   system source file.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#ifndef __SYSTEM_TARGET_H
+#define __SYSTEM_TARGET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "type_def.h"
+
+
+
+extern void SystemInit(void);
+extern void SystemUpdate(void);
+
+
+#ifdef USE_TARGET_DRIVER
+    #include "lib_conf.h"
+#endif /* USE_TARGET_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_TARGET_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/type_def.h

+/**
+  ******************************************************************************
+  * @file    type_def.h 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2018-09-27
+  * @brief   Typedef file
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __TYPE_DEF_H
+#define __TYPE_DEF_H
+
+#define ENABLE  1
+#define DISABLE 0
+#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
+
+#define BIT_BAND(addr, bitnum)        *((volatile unsigned long *)((((uint32_t)addr) & 0xF0000000) + \
+                                        0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2)))
+
+#define BIT0      0x00000001
+#define BIT1      0x00000002
+#define BIT2      0x00000004
+#define BIT3      0x00000008
+#define BIT4      0x00000010
+#define BIT5      0x00000020
+#define BIT6      0x00000040
+#define BIT7      0x00000080
+#define BIT8      0x00000100
+#define BIT9      0x00000200
+#define BIT10     0x00000400
+#define BIT11     0x00000800
+#define BIT12     0x00001000
+#define BIT13     0x00002000
+#define BIT14     0x00004000
+#define BIT15     0x00008000
+#define BIT16     0x00010000
+#define BIT17     0x00020000
+#define BIT18     0x00040000
+#define BIT19     0x00080000
+#define BIT20     0x00100000
+#define BIT21     0x00200000
+#define BIT22     0x00400000
+#define BIT23     0x00800000
+#define BIT24     0x01000000
+#define BIT25     0x02000000
+#define BIT26     0x04000000
+#define BIT27     0x08000000
+#define BIT28     0x10000000
+#define BIT29     0x20000000
+#define BIT30     0x40000000
+#define BIT31     0x80000000
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
+/* ARM & GNUCompiler
+   ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#endif /* __TYPE_DEF_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S

+;/**
+;* @file    startup_target.s
+;* @author  Application Team
+;* @version V1.1.0
+;* @date    2019-10-28
+;* @brief   Target Devices vector table.
+;******************************************************************************/
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.equ __CHIPINITIAL, 1
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/*************************************************************************
+* Chip init.
+*      1. Load flash configuration
+*      2. Load ANA_REG(B/C/D/E) information
+*      3. Load ANA_REG10 information
+
+**************************************************************************/
+.if (__CHIPINITIAL != 0)
+  .section .chipinit_section.__CHIP_INIT
+__CHIP_INIT:
+CONFIG1_START:
+        /*-------------------------------*/
+        /* 1. Load flash configuration */
+        /* Unlock flash */
+        LDR     R0, =0x000FFFE0
+        LDR     R1, =0x55AAAA55
+        STR     R1, [R0]
+        /* Load configure word 0 to 7
+           Compare bit[7:0] */
+        LDR     R0, =0x00080E00
+        LDR     R1, =0x20
+        LDR     R2, =0x000FFFE8
+        LDR     R3, =0x000FFFF0
+        LDR     R4, =0x0
+        LDR     R7, =0x0FF
+FLASH_CONF_START_1:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+        BNE     FLASH_CONF_AGAIN_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_1
+        B       FLASH_CONF_START_1
+FLASH_CONF_AGAIN_1:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+FLASH_CONF_WHILELOOP_1:
+        BNE     FLASH_CONF_WHILELOOP_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_1
+        B       FLASH_CONF_START_1
+FLASH_CONF_END_1:
+        /* Load configure word 8 to 11
+           Compare bit 31,24,23:16,8,7:0 */
+        LDR     R1, =0x30
+        LDR     R7, =0x81FF81FF
+FLASH_CONF_START_2:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+        BNE     FLASH_CONF_AGAIN_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_2
+        B       FLASH_CONF_START_2
+FLASH_CONF_AGAIN_2:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+FLASH_CONF_WHILELOOP_2:
+        BNE     FLASH_CONF_WHILELOOP_2
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_2
+        B       FLASH_CONF_START_2
+FLASH_CONF_END_2:
+        /* Lock flash */
+        LDR     R0, =0x000FFFE0
+        LDR     R1, =0x0
+        STR     R1, [R0]
+        /*-------------------------------*/
+        /* 2. Load ANA_REG(B/C/D/E) information */
+CONFIG2_START:
+        LDR     R4, =0x4001422C
+        LDR     R5, =0x40014230
+        LDR     R6, =0x40014234
+        LDR     R7, =0x40014238
+        LDR     R0, =0x80DC0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DC4
+        LDR     R1, [R1]
+        ADDS    R2, R0, R1
+        ADDS    R2, #0x0FFFFFFFF
+        MVNS    R2, R2
+        LDR     R3, =0x80DCC
+        LDR     R3, [R3]
+        CMP     R3, R2
+        BEQ     ANADAT_CHECKSUM1_OK
+        B       ANADAT_CHECKSUM1_ERR
+ANADAT_CHECKSUM1_OK:
+        /* ANA_REGB */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R4]
+        /* ANA_REGC */
+        LDR     R1, =0x0FF00
+        ANDS    R1, R0
+        LSRS    R1, R1, #8
+        STR     R1, [R5]
+        /* ANA_REGD */
+        LDR     R1, =0x0FF0000
+        ANDS    R1, R0
+        LSRS    R1, R1, #16
+        STR     R1, [R6]
+        /* ANA_REGE */
+        LDR     R1, =0x0FF000000
+        ANDS    R1, R0
+        LSRS    R1, R1, #24
+        STR     R1, [R7]
+        B       CONFIG3_START
+ANADAT_CHECKSUM1_ERR:
+        LDR     R0, =0x80DD0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DD4
+        LDR     R1, [R1]
+        ADDS    R2, R0, R1
+        ADDS    R2, #0x0FFFFFFFF
+        MVNS    R2, R2
+        LDR     R3, =0x80DDC
+        LDR     R3, [R3]
+        CMP     R3, R2
+        BEQ     ANADAT_CHECKSUM2_OK
+        B       ANADAT_CHECKSUM2_ERR
+ANADAT_CHECKSUM2_OK:
+        /* ANA_REGB */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R4]
+        /* ANA_REGC */
+        LDR     R1, =0x0FF00
+        ANDS    R1, R0
+        LSRS    R1, R1, #8
+        STR     R1, [R5]
+        /* ANA_REGD */
+        LDR     R1, =0x0FF0000
+        ANDS    R1, R0
+        LSRS    R1, R1, #16
+        STR     R1, [R6]
+        /* ANA_REGE */
+        LDR     R1, =0x0FF000000
+        ANDS    R1, R0
+        LSRS    R1, R1, #24
+        STR     R1, [R7]
+        B       CONFIG3_START
+ANADAT_CHECKSUM2_ERR:
+        B       ANADAT_CHECKSUM2_ERR
+        /*-------------------------------*/
+        /* 3. Load ANA_REG10 information */
+CONFIG3_START:
+        LDR     R7, =0x40014240
+        LDR     R0, =0x80DE0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DE4
+        LDR     R1, [R1]
+        MVNS    R1, R1
+        CMP     R1, R0
+        BEQ     ANADAT10_CHECKSUM1_OK
+        B       ANADAT10_CHECKSUM1_ERR
+ANADAT10_CHECKSUM1_OK:
+        /* ANA_REG10 */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R7]
+        BX      LR
+ANADAT10_CHECKSUM1_ERR:
+        LDR     R0, =0x80DE8
+        LDR     R0, [R0]
+        LDR     R1, =0x80DEC
+        LDR     R1, [R1]
+        MVNS    R1, R1
+        CMP     R1, R0
+        BEQ     ANADAT10_CHECKSUM2_OK
+        B       ANADAT10_CHECKSUM2_ERR
+ANADAT10_CHECKSUM2_OK:
+        /* ANA_REG10 */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R7]
+        BX      LR
+ANADAT10_CHECKSUM2_ERR:
+        B       ANADAT10_CHECKSUM2_ERR
+.size __CHIP_INIT, .-__CHIP_INIT
+.endif
+
+
+.if (__CHIPINITIAL != 0)
+  .global __CHIP_INIT
+  .section .chipinit_section.Reset_Handler
+.else
+  .section .text.Reset_Handler
+.endif
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+.if (__CHIPINITIAL != 0)
+/* Chip Initiliazation */  
+  bl    __CHIP_INIT
+/* System Initiliazation */
+  bl SystemInit
+.endif
+
+/* set stack pointer */
+  ldr   r0, =_estack
+  mov   sp, r0
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word  PMU_IRQHandler                    /*  0: PMU       */
+  .word  RTC_IRQHandler                    /*  1: RTC       */
+  .word  U32K0_IRQHandler                  /*  2: U32K0     */
+  .word  U32K1_IRQHandler                  /*  3: U32K1     */
+  .word  I2C_IRQHandler                    /*  4: I2C       */
+  .word  SPI1_IRQHandler                   /*  5: SPI1      */
+  .word  UART0_IRQHandler                  /*  6: UART0     */
+  .word  UART1_IRQHandler                  /*  7: UART1     */
+  .word  UART2_IRQHandler                  /*  8: UART2     */
+  .word  UART3_IRQHandler                  /*  9: UART3     */
+  .word  UART4_IRQHandler                  /* 10: UART4     */
+  .word  UART5_IRQHandler                  /* 11: UART5     */
+  .word  ISO78160_IRQHandler               /* 12: ISO78160  */
+  .word  ISO78161_IRQHandler               /* 13: ISO78161  */
+  .word  TMR0_IRQHandler                   /* 14: TMR0      */
+  .word  TMR1_IRQHandler                   /* 15: TMR1      */
+  .word  TMR2_IRQHandler                   /* 16: TMR2      */
+  .word  TMR3_IRQHandler                   /* 17: TMR3      */
+  .word  PWM0_IRQHandler                   /* 18: PWM0      */
+  .word  PWM1_IRQHandler                   /* 19: PWM1      */
+  .word  PWM2_IRQHandler                   /* 20: PWM2      */
+  .word  PWM3_IRQHandler                   /* 21: PWM3      */
+  .word  DMA_IRQHandler                    /* 22: DMA       */
+  .word  FLASH_IRQHandler                  /* 23: FLASH     */
+  .word  ANA_IRQHandler                    /* 24: ANA       */
+  .word  0                                 /* 25: Reserved  */
+  .word  0                                 /* 26: Reserved  */
+  .word  SPI2_IRQHandler                   /* 27: SPI2      */
+  .word  SPI3_IRQHandler                   /* 28: SPI3      */
+  .word  0                                 /* 29: Reserved  */
+  .word  0                                 /* 30: Reserved  */
+  .word  0                                 /* 31: Reserved  */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      PMU_IRQHandler
+  .thumb_set PMU_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      U32K0_IRQHandler
+  .thumb_set U32K0_IRQHandler,Default_Handler
+
+  .weak      U32K1_IRQHandler
+  .thumb_set U32K1_IRQHandler,Default_Handler
+
+  .weak      I2C_IRQHandler
+  .thumb_set I2C_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      UART0_IRQHandler
+  .thumb_set UART0_IRQHandler,Default_Handler
+
+  .weak      UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Default_Handler
+
+  .weak      UART2_IRQHandler
+  .thumb_set UART2_IRQHandler,Default_Handler
+
+  .weak      UART3_IRQHandler
+  .thumb_set UART3_IRQHandler,Default_Handler
+
+  .weak      UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak      UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak      ISO78160_IRQHandler
+  .thumb_set ISO78160_IRQHandler,Default_Handler
+
+  .weak      ISO78161_IRQHandler
+  .thumb_set ISO78161_IRQHandler,Default_Handler
+
+  .weak      TMR0_IRQHandler
+  .thumb_set TMR0_IRQHandler,Default_Handler
+
+  .weak      TMR1_IRQHandler
+  .thumb_set TMR1_IRQHandler,Default_Handler
+
+  .weak      TMR2_IRQHandler
+  .thumb_set TMR2_IRQHandler,Default_Handler
+
+  .weak      TMR3_IRQHandler
+  .thumb_set TMR3_IRQHandler,Default_Handler
+
+  .weak      PWM0_IRQHandler
+  .thumb_set PWM0_IRQHandler,Default_Handler
+
+  .weak      PWM1_IRQHandler
+  .thumb_set PWM1_IRQHandler,Default_Handler
+
+  .weak      PWM2_IRQHandler
+  .thumb_set PWM2_IRQHandler,Default_Handler
+
+  .weak      PWM3_IRQHandler
+  .thumb_set PWM3_IRQHandler,Default_Handler
+
+  .weak      DMA_IRQHandler
+  .thumb_set DMA_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      ANA_IRQHandler
+  .thumb_set ANA_IRQHandler,Default_Handler
+
+  .weak      SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak      SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S

+;/**
+;* @file    startup_target.s
+;* @author  Application Team
+;* @version V1.1.0
+;* @date    2019-10-28
+;* @brief   Target Devices vector table.
+;******************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+__CHIPINITIAL   EQU     1
+
+Stack_Size      EQU     0x000001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     PMU_IRQHandler            ;  0:  PMU
+                DCD     RTC_IRQHandler            ;  1:  RTC
+                DCD     U32K0_IRQHandler          ;  2:  U32K0
+                DCD     U32K1_IRQHandler          ;  3:  U32K1
+                DCD     I2C_IRQHandler            ;  4:  I2C
+                DCD     SPI1_IRQHandler           ;  5:  SPI1
+                DCD     UART0_IRQHandler          ;  6:  UART0
+                DCD     UART1_IRQHandler          ;  7:  UART1
+                DCD     UART2_IRQHandler          ;  8:  UART2
+                DCD     UART3_IRQHandler          ;  9:  UART3
+                DCD     UART4_IRQHandler          ; 10:  UART4
+                DCD     UART5_IRQHandler          ; 11:  UART5
+                DCD     ISO78160_IRQHandler       ; 12:  ISO78160
+                DCD     ISO78161_IRQHandler       ; 13:  ISO78161
+                DCD     TMR0_IRQHandler           ; 14:  TMR0
+                DCD     TMR1_IRQHandler           ; 15:  TMR1
+                DCD     TMR2_IRQHandler           ; 16:  TMR2
+                DCD     TMR3_IRQHandler           ; 17:  TMR3
+                DCD     PWM0_IRQHandler           ; 18:  PWM0
+                DCD     PWM1_IRQHandler           ; 19:  PWM1
+                DCD     PWM2_IRQHandler           ; 20:  PWM2
+                DCD     PWM3_IRQHandler           ; 21:  PWM3
+                DCD     DMA_IRQHandler            ; 22:  DMA
+                DCD     FLASH_IRQHandler          ; 23:  FLASH
+                DCD     ANA_IRQHandler            ; 24:  ANA
+                DCD     0                         ; 25:  Reserved
+                DCD     0                         ; 26:  Reserved
+                DCD     SPI2_IRQHandler           ; 27:  SPI2
+                DCD     SPI3_IRQHandler           ; 28:  SPI3
+                DCD     0                         ; 29:  Reserved
+                DCD     0                         ; 30:  Reserved
+                DCD     0                         ; 31:  Reserved
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+  IF (__CHIPINITIAL != 0)
+                AREA    |.ARM.__AT_0xC0|, CODE, READONLY
+  ELSE
+                AREA    |.text|, CODE, READONLY
+  ENDIF
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+  IF (__CHIPINITIAL != 0)
+                LDR     R0, =__CHIP_INIT
+                BLX     R0
+  ENDIF
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+                AREA    |.text|, CODE, READONLY
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  PMU_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  U32K0_IRQHandler          [WEAK]
+                EXPORT  U32K1_IRQHandler          [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  SPI1_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  UART5_IRQHandler          [WEAK]
+                EXPORT  ISO78160_IRQHandler       [WEAK]
+                EXPORT  ISO78161_IRQHandler       [WEAK]
+                EXPORT  TMR0_IRQHandler           [WEAK]
+                EXPORT  TMR1_IRQHandler           [WEAK]
+                EXPORT  TMR2_IRQHandler           [WEAK]
+                EXPORT  TMR3_IRQHandler           [WEAK]
+                EXPORT  PWM0_IRQHandler           [WEAK]
+                EXPORT  PWM1_IRQHandler           [WEAK]
+                EXPORT  PWM2_IRQHandler           [WEAK]
+                EXPORT  PWM3_IRQHandler           [WEAK]
+                EXPORT  DMA_IRQHandler            [WEAK]
+                EXPORT  FLASH_IRQHandler      	  [WEAK]
+                EXPORT  ANA_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler           [WEAK]
+                EXPORT  SPI3_IRQHandler           [WEAK]
+
+PMU_IRQHandler
+RTC_IRQHandler
+U32K0_IRQHandler
+U32K1_IRQHandler
+I2C_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+ISO78160_IRQHandler
+ISO78161_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+PWM0_IRQHandler
+PWM1_IRQHandler
+PWM2_IRQHandler
+PWM3_IRQHandler
+DMA_IRQHandler
+FLASH_IRQHandler
+ANA_IRQHandler
+SPI2_IRQHandler
+SPI3_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Chip init.
+;;      1. Load flash configuration
+;;      2. Load ANA_REG(B/C/D/E) information
+;;      3. Load ANA_REG10 information
+  IF (__CHIPINITIAL != 0)
+        AREA    |.ARM.__AT_0xC0|, CODE, READONLY
+
+__CHIP_INIT PROC
+CONFIG1_START
+        ;-------------------------------;
+        ;; 1. Load flash configuration
+        ; Unlock flash
+        LDR     R0, =0x000FFFE0
+        LDR     R1, =0x55AAAA55
+        STR     R1, [R0]
+        ; Load configure word 0 to 7
+        ; Compare bit[7:0]
+        LDR     R0, =0x00080E00
+        LDR     R1, =0x20
+        LDR     R2, =0x000FFFE8
+        LDR     R3, =0x000FFFF0
+        LDR     R4, =0x0
+        LDR     R7, =0x0FF
+FLASH_CONF_START_1
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+        BNE     FLASH_CONF_AGAIN_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_1
+        B       FLASH_CONF_START_1
+FLASH_CONF_AGAIN_1
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+FLASH_CONF_WHILELOOP_1
+        BNE     FLASH_CONF_WHILELOOP_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_1
+        B       FLASH_CONF_START_1
+FLASH_CONF_END_1
+        ; Load configure word 8 to 11
+        ; Compare bit 31,24,23:16,8,7:0
+        LDR     R1, =0x30
+        LDR     R7, =0x81FF81FF
+FLASH_CONF_START_2
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+        BNE     FLASH_CONF_AGAIN_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_2
+        B       FLASH_CONF_START_2
+FLASH_CONF_AGAIN_2
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+FLASH_CONF_WHILELOOP_2
+        BNE     FLASH_CONF_WHILELOOP_2
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_2
+        B       FLASH_CONF_START_2
+FLASH_CONF_END_2  
+        ; Lock flash
+        LDR     R0, =0x000FFFE0
+        LDR     R1, =0x0
+        STR     R1, [R0]
+        ;-------------------------------;
+        ;; 2. Load ANA_REG(B/C/D/E) information
+CONFIG2_START
+        LDR     R4, =0x4001422C
+        LDR     R5, =0x40014230
+        LDR     R6, =0x40014234
+        LDR     R7, =0x40014238
+        LDR     R0, =0x80DC0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DC4
+        LDR     R1, [R1]
+        ADDS    R2, R0, R1
+        ADDS    R2, #0x0FFFFFFFF
+        MVNS    R2, R2
+        LDR     R3, =0x80DCC
+        LDR     R3, [R3]
+        CMP     R3, R2
+        BEQ     ANADAT_CHECKSUM1_OK
+        B       ANADAT_CHECKSUM1_ERR
+ANADAT_CHECKSUM1_OK  
+        ; ANA_REGB
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R4]
+        ; ANA_REGC
+        LDR     R1, =0x0FF00
+        ANDS    R1, R0
+        LSRS    R1, R1, #8
+        STR     R1, [R5]
+        ; ANA_REGD
+        LDR     R1, =0x0FF0000
+        ANDS    R1, R0
+        LSRS    R1, R1, #16
+        STR     R1, [R6]
+        ; ANA_REGE
+        LDR     R1, =0x0FF000000
+        ANDS    R1, R0
+        LSRS    R1, R1, #24
+        STR     R1, [R7]
+        B       CONFIG3_START
+ANADAT_CHECKSUM1_ERR
+        LDR     R0, =0x80DD0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DD4
+        LDR     R1, [R1]
+        ADDS    R2, R0, R1
+        ADDS    R2, #0x0FFFFFFFF
+        MVNS    R2, R2
+        LDR     R3, =0x80DDC
+        LDR     R3, [R3]
+        CMP     R3, R2
+        BEQ     ANADAT_CHECKSUM2_OK
+        B       ANADAT_CHECKSUM2_ERR
+ANADAT_CHECKSUM2_OK  
+        ; ANA_REGB
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R4]
+        ; ANA_REGC
+        LDR     R1, =0x0FF00
+        ANDS    R1, R0
+        LSRS    R1, R1, #8
+        STR     R1, [R5]
+        ; ANA_REGD
+        LDR     R1, =0x0FF0000
+        ANDS    R1, R0
+        LSRS    R1, R1, #16
+        STR     R1, [R6]
+        ; ANA_REGE
+        LDR     R1, =0x0FF000000
+        ANDS    R1, R0
+        LSRS    R1, R1, #24
+        STR     R1, [R7]
+        B       CONFIG3_START 
+ANADAT_CHECKSUM2_ERR
+        B       ANADAT_CHECKSUM2_ERR
+        ;-------------------------------;
+        ;; 2. Load ANA_REG10 information
+CONFIG3_START
+        LDR     R7, =0x40014240
+        LDR     R0, =0x80DE0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DE4
+        LDR     R1, [R1]
+        MVNS    R1, R1
+        CMP     R1, R0
+        BEQ     ANADAT10_CHECKSUM1_OK
+        B       ANADAT10_CHECKSUM1_ERR
+ANADAT10_CHECKSUM1_OK  
+        ; ANA_REG10
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R7]
+        BX      LR
+ANADAT10_CHECKSUM1_ERR
+        LDR     R0, =0x80DE8
+        LDR     R0, [R0]
+        LDR     R1, =0x80DEC
+        LDR     R1, [R1]
+        MVNS    R1, R1
+        CMP     R1, R0
+        BEQ     ANADAT10_CHECKSUM2_OK
+        B       ANADAT10_CHECKSUM2_ERR
+ANADAT10_CHECKSUM2_OK
+        ; ANA_REG10
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R7]
+        BX      LR             
+ANADAT10_CHECKSUM2_ERR
+        B       ANADAT10_CHECKSUM2_ERR
+         
+        NOP
+        ENDP
+  ENDIF
+
+                END
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c

+/**
+  ******************************************************************************
+  * @file    lib_CodeRAM.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Codes executed in SRAM.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lib_CodeRAM.h"
+
+#ifndef __GNUC__
+/**
+  * @brief  Enter idle mode with flash deep standby.
+  * @note   This function is executed in RAM.
+  * @param  None
+  * @retval None
+  */
+__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void)
+{
+  /* Flash deep standby */
+  FLASH->PASS = 0x55AAAA55;
+  FLASH->DSTB = 0xAA5555AA;
+  /* Enter Idle mode */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  __WFI();
+}
+#endif
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/lib_cortex.c

+/**
+  ******************************************************************************
+  * @file    lib_cortex.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Cortex module driver.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lib_cortex.h"
+#include "core_cm0.h"
+
+/**
+  * @brief  1. Clears Pending of a device specific External Interrupt.
+  *         2. Sets Priority of a device specific External Interrupt.
+  *         3. Enables a device specific External Interrupt. 
+  * @param  IRQn: External interrupt number .
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to target.h file)
+  * @param  Priority: The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 3.
+  *         A lower priority value indicates a higher priority
+  * @retval None
+  */
+void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+  assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
+
+  /* Clear Pending Interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+  /* Set Interrupt Priority */
+  NVIC_SetPriority(IRQn, Priority);
+  /* Enable Interrupt in NVIC */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly before calling it.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+  * @retval None
+  */
+void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+  /* Enable interrupt in NVIC */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+  * @retval None
+  */
+void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+  /* Disable interrupt in NVIC */
+  NVIC_DisableIRQ(IRQn); 
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void CORTEX_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();  
+}
+
+/**
+  * @brief  Gets the Pending bit of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+  * @retval 0  Interrupt status is not pending.
+            1  Interrupt status is pending.
+  */
+uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+  /* Get priority for Cortex-M0 system or device specific interrupts */
+  return NVIC_GetPendingIRQ(IRQn);  
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+  * @retval None
+  */
+void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+  * @retval None
+  */
+void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
+  /* Clear interrupt pending */
+  NVIC_ClearPendingIRQ(IRQn);  
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
+  * @retval Interrupt Priority. Value is aligned automatically to the implemented
+  *         priority bits of the microcontroller.
+  */
+uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
+{
+  /* Get priority for Cortex-M0 system or device specific interrupts */
+  return NVIC_GetPriority(IRQn);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn: External interrupt number .
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete target Devices IRQ Channels list, please refer to target.h file)
+  * @param  Priority: The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 3.
+  *         A lower priority value indicates a higher priority  
+  * @retval None
+  */
+void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
+{
+  /* Check parameters */
+  assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
+  /* Get priority for Cortex-M0 system or device specific interrupts */
+  NVIC_SetPriority(IRQn, Priority);
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
+{
+  return SysTick_Config(TicksNum);
+}
+
+/**
+  * @brief  Delay N system-clock cycle.
+  * @param  nClock < 0x1000000
+  * @retval None
+  */
+void CORTEX_Delay_nSysClock(__IO uint32_t nClock)
+{
+  uint32_t tmp;
+  
+  SysTick->LOAD = nClock - 1;
+  SysTick->VAL  = 0; 
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \
+                 |SysTick_CTRL_ENABLE_Msk;
+  
+  do
+  {
+    tmp = SysTick->CTRL;
+  }
+  while (!(tmp & SysTick_CTRL_COUNTFLAG_Msk));
+  
+  SysTick->CTRL = 0;
+}
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/Vango/V85xxP/Source/system_target.c

+/**
+  ******************************************************************************
+  * @file    system_target.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   system source file.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#include "target.h"
+
+
+
+/**
+  * @brief  Setup the microcontroller system
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  volatile uint32_t i;
+  uint32_t tmp[3];
+
+  ANA->REG0 = 0x30;
+  ANA->REG4 = 0x04;
+  ANA->REG7 = 0x84;
+  ANA->REGA = 0x02;
+  while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
+  ANA->ADCCTRL0 = 0x300000;
+  ANA->ADCCTRL1 = 0xC2;
+  ANA->ADCCTRL2 = 0x8014;
+  LCD->CTRL = 0x84;
+
+  tmp[0] = 0x599A599A;
+  tmp[1] = 0x78000000;
+  tmp[2] = 0x80000000;
+  RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
+}
+
+/**
+  * @brief  Initializes registers.
+  * @param  None
+  * @retval None
+  */
+void SystemUpdate(void)
+{
+  uint32_t tmp[3];
+  
+  ANA->REG0 &= ~0xCE;
+  ANA->REG0 |= 0x30;
+  ANA->REG1 &= ~0x7F;
+  ANA->REG2 &= ~0xC0;
+  ANA->REG3 &= ~0x01;
+  ANA->REG4 |= 0x04;
+  ANA->REG4 &= ~0xFB;
+  ANA->REG5 &= ~0xB0;
+  ANA->REG6 &= ~0x3E;
+  ANA->REG7 |= 0x84;
+  ANA->REG7 &= ~0x7B;
+  ANA->REG8 &= ~0x0C;
+  ANA->REGA |= 0x02;
+  ANA->REGA &= ~0x7D;
+  
+  tmp[0] = 0x599A599A;
+  tmp[1] = RTC->ADCMACTL;
+  tmp[1] &= ~0XFF080000;
+  tmp[1] |= 0x78000000;
+  tmp[2] = 0x80000000;
+  RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
+}
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/CMSIS/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/v85xxp/Libraries/CMSIS/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/v85xxp/Libraries/SConscript

+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('VangoV85xxP_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/system_target.c']
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_CodeRAM.c']
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_cortex.c']
+src += [cwd + '/CMSIS/Vango/V85xxP/Source/lib_LoadNVR.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/CMSIS/Vango/V85xxP/Source/GCC/startup_target.S']
+if rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/CMSIS/Vango/V85xxP/Source/Keil5/startup_target.S']
+
+path = [
+    cwd + '/CMSIS/Vango/V85xxP/Include',
+    cwd + '/CMSIS',
+    cwd + '/VangoV85xxP_standard_peripheral/Include',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85XXP','USE_TARGET_DRIVER']
+
+group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_adc_tiny.h

+/**
+  ******************************************************************************
+  * @file    lib_adc_tiny.h 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   ADC_TINY library.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#ifndef __LIB_ADC_TINY_H
+#define __LIB_ADC_TINY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+  uint32_t SignalSel; 
+  uint32_t ADTREF1;
+  uint32_t ADTREF2;  
+  uint32_t ADTREF3;
+} TADCInitType;
+
+//SelADT
+#define ADCTINY_SIGNALSEL_IOE6   0
+#define ADCTINY_SIGNALSEL_IOE7   ANA_REGF_ADTSEL
+#define IS_ADCTINY_SELADT(__SELADT__)  (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\
+                                        ((__SELADT__) == ADCTINY_SIGNALSEL_IOE7))
+
+//ADTREF1
+#define ADCTINY_REF1_0_9   0
+#define ADCTINY_REF1_0_7   ANA_REGF_ADTREF1SEL
+#define IS_ADCTINY_ADTREF1(__ADTREF1__)  (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\
+                                          ((__ADTREF1__) == ADCTINY_REF1_0_7))
+
+//ADTREF2
+#define ADCTINY_REF2_1_8   0
+#define ADCTINY_REF2_1_6   ANA_REGF_ADTREF2SEL
+#define IS_ADCTINY_ADTREF2(__ADTREF2__)  (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\
+                                          ((__ADTREF2__) == ADCTINY_REF2_1_6))
+
+//ADTREF3
+#define ADCTINY_REF3_2_7   0
+#define ADCTINY_REF3_2_5   ANA_REGF_ADTREF3SEL
+#define IS_ADCTINY_ADTREF3(__ADTREF3__)  (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\
+                                          ((__ADTREF3__) == ADCTINY_REF3_2_5))
+
+//THSel
+#define ADCTINY_THSEL_0  (0x00UL << ANA_MISC_TADCTH_Pos)
+#define ADCTINY_THSEL_1  (0x01UL << ANA_MISC_TADCTH_Pos)
+#define ADCTINY_THSEL_2  (0x02UL << ANA_MISC_TADCTH_Pos)
+#define ADCTINY_THSEL_3  (0x03UL << ANA_MISC_TADCTH_Pos)
+#define IS_ADCTINY_THSEL(__THSEL__)  (((__THSEL__) == ADCTINY_THSEL_0) ||\
+                                      ((__THSEL__) == ADCTINY_THSEL_1) ||\
+                                      ((__THSEL__) == ADCTINY_THSEL_2) ||\
+                                      ((__THSEL__) == ADCTINY_THSEL_3))
+
+/* Exported Functions ------------------------------------------------------- */
+void TADC_DeInit(void);
+void TADC_StructInit(TADCInitType* TADC_InitStruct);
+void TADC_Init(TADCInitType* TADC_InitStruct);
+void TADC_Cmd(uint32_t NewState);
+uint8_t TADC_GetOutput(void);
+void TADC_IntTHConfig(uint32_t THSel);
+void TADC_INTConfig(uint32_t NewState);
+uint8_t TADC_GetINTStatus(void);
+void TADC_ClearINTStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+     
+#endif  /* __LIB_ADC_TINY_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_ana.h

+/**
+  ******************************************************************************
+  * @file    lib_ana.h 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   Analog library.
+  ******************************************************************************
+  * @attention
+  *
+  *
+  ******************************************************************************
+  */
+#ifndef __LIB_ANA_H
+#define __LIB_ANA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+/***** StatusMask (ANA_GetStatus) *****/
+#define ANA_STATUS_AVCCLV       ANA_CMPOUT_AVCCLV
+#define ANA_STATUS_VDCINDROP    ANA_CMPOUT_VDCINDROP
+#define ANA_STATUS_VDDALARM     ANA_CMPOUT_VDDALARM
+#define ANA_STATUS_COMP2        ANA_CMPOUT_CMP2
+#define ANA_STATUS_COMP1        ANA_CMPOUT_CMP1
+#define ANA_STATUS_LOCKL        ANA_CMPOUT_LOCKL
+#define ANA_STATUS_LOCKH        ANA_CMPOUT_LOCKH
+
+/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/
+#define ANA_INT_UPPER_TH3       ANA_INTEN_INTEN21
+#define ANA_INT_LOWER_TH3       ANA_INTEN_INTEN20
+#define ANA_INT_UPPER_TH2       ANA_INTEN_INTEN19
+#define ANA_INT_LOWER_TH2       ANA_INTEN_INTEN18
+#define ANA_INT_UPPER_TH1       ANA_INTEN_INTEN17
+#define ANA_INT_LOWER_TH1       ANA_INTEN_INTEN16
+#define ANA_INT_UPPER_TH0       ANA_INTEN_INTEN15
+#define ANA_INT_LOWER_TH0       ANA_INTEN_INTEN14
+#define ANA_INT_TADC_OVER       ANA_INTEN_INTEN13
+#define ANA_INT_REGERR          ANA_INTEN_INTEN12
+#define ANA_INT_SLPFAIL_VDCIN   ANA_INTEN_INTEN11
+#define ANA_INT_AVCCLV          ANA_INTEN_INTEN10
+#define ANA_INT_VDCINDROP       ANA_INTEN_INTEN8
+#define ANA_INT_VDDALARM        ANA_INTEN_INTEN7
+#define ANA_INT_COMP2           ANA_INTEN_INTEN3
+#define ANA_INT_COMP1           ANA_INTEN_INTEN2
+#define ANA_INT_ADCA            ANA_INTEN_INTEN1
+#define ANA_INT_ADCM            ANA_INTEN_INTEN0
+#define ANA_INT_Msk             (ANA_INTSTS_INTSTS21     \
+                                |ANA_INTSTS_INTSTS20    \
+                                |ANA_INTSTS_INTSTS19    \
+                                |ANA_INTSTS_INTSTS18    \
+                                |ANA_INTSTS_INTSTS17    \
+                                |ANA_INTSTS_INTSTS16    \
+                                |ANA_INTSTS_INTSTS15    \
+                                |ANA_INTSTS_INTSTS14    \
+                                |ANA_INTSTS_INTSTS13    \
+                                |ANA_INTSTS_INTSTS12   \
+                                |ANA_INTSTS_INTSTS11   \
+                                |ANA_INTSTS_INTSTS10   \
+                                |ANA_INTSTS_INTSTS8    \
+                                |ANA_INTSTS_INTSTS7    \
+                                |ANA_INTSTS_INTSTS3    \
+                                |ANA_INTSTS_INTSTS2    \
+                                |ANA_INTSTS_INTSTS1    \
+                                |ANA_INTSTS_INTSTS0)
+
+/****************************** ANA Instances *********************************/
+#define IS_ANA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ANA)
+
+/* Private macros ------------------------------------------------------------*/
+#define IS_ANA_STATUS(__STATUS__)  (((__STATUS__) == ANA_STATUS_AVCCLV)    ||\
+                                    ((__STATUS__) == ANA_STATUS_VDCINDROP) ||\
+                                    ((__STATUS__) == ANA_STATUS_VDDALARM)  ||\
+                                    ((__STATUS__) == ANA_STATUS_COMP2)     ||\
+                                    ((__STATUS__) == ANA_STATUS_COMP1)     ||\
+                                    ((__STATUS__) == ANA_STATUS_LOCKL)     ||\
+                                    ((__STATUS__) == ANA_STATUS_LOCKH))
+
+#define IS_ANA_INTSTSR(__INTSTSR__)  (((__INTSTSR__) == ANA_INT_UPPER_TH3)     ||\
+                                      ((__INTSTSR__) == ANA_INT_LOWER_TH3)     ||\
+                                      ((__INTSTSR__) == ANA_INT_UPPER_TH2)     ||\
+                                      ((__INTSTSR__) == ANA_INT_LOWER_TH2)     ||\
+                                      ((__INTSTSR__) == ANA_INT_UPPER_TH1)     ||\
+                                      ((__INTSTSR__) == ANA_INT_LOWER_TH1)     ||\
+                                      ((__INTSTSR__) == ANA_INT_UPPER_TH0)     ||\
+                                      ((__INTSTSR__) == ANA_INT_LOWER_TH0)     ||\
+                                      ((__INTSTSR__) == ANA_INT_TADC_OVER)     ||\
+                                      ((__INTSTSR__) == ANA_INT_REGERR)        ||\
+                                      ((__INTSTSR__) == ANA_INT_SLPFAIL_VDCIN) ||\
+                                      ((__INTSTSR__) == ANA_INT_AVCCLV)        ||\
+                                      ((__INTSTSR__) == ANA_INT_VDCINDROP)     ||\
+                                      ((__INTSTSR__) == ANA_INT_VDDALARM)      ||\
+                                      ((__INTSTSR__) == ANA_INT_COMP2)         ||\
+                                      ((__INTSTSR__) == ANA_INT_COMP1)         ||\
+                                      ((__INTSTSR__) == ANA_INT_ADCA)          ||\
+                                      ((__INTSTSR__) == ANA_INT_ADCM))
+
+#define IS_ANA_INTSTSC(__INTSTSC__)  ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\
+                                      (((__INTSTSC__) & ~ANA_INT_Msk) == 0U))
+
+#define IS_ANA_INT(__INT__)  IS_ANA_INTSTSC(__INT__)
+
+/* Exported Functions ------------------------------------------------------- */
+uint8_t ANA_GetStatus(uint32_t StatusMask);
+uint8_t ANA_GetINTStatus(uint32_t IntMask);
+void ANA_ClearINTStatus(uint32_t IntMask);
+void ANA_INTConfig(uint32_t IntMask, uint32_t NewState);
+
+#ifdef __cplusplus
+}
+#endif
+     
+#endif  /* __LIB_ANA_H */
+
+/*********************************** END OF FILE ******************************/

bsp/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/lib_version.h

+/**
+*******************************************************************************
+	* @file    lib_version.h
+	* @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+	* @brief   Version library.
+*******************************************************************************/
+
+#ifndef __LIB_VERSION_H
+#define __LIB_VERSION_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+   
+#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor))
+
+/* Exported Functions ------------------------------------------------------- */
+   
+/**
+  * @brief  Read receive data register.
+  * @param  None
+  * @retval Version value
+  */
+uint16_t Target_GetDriveVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_VERSION_H */
+
+/*********************************** END OF FILE ******************************/