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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
35eff9a8
编写于
5月 20, 2019
作者:
armink_ztl
浏览文件
操作
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电子邮件补丁
差异文件
Fix the CI build error.
上级
9ac80745
变更
7
隐藏空白更改
内联
并排
Showing
7 changed file
with
89 addition
and
1 deletion
+89
-1
.travis.yml
.travis.yml
+0
-1
bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm0.a
...c54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm0.a
+0
-0
bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a
...ite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a
+0
-0
bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_softabi.a
...ite/Libraries/devices/LPC54114/gcc/libpower_cm4_softabi.a
+0
-0
bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a
...54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a
+0
-0
bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power_m0.a
...14-lite/Libraries/devices/LPC54114/iar/iar_lib_power_m0.a
+0
-0
libcpu/arm/cortex-m7/cpu_cache.c
libcpu/arm/cortex-m7/cpu_cache.c
+89
-0
未找到文件。
.travis.yml
浏览文件 @
35eff9a8
...
...
@@ -59,7 +59,6 @@ env:
# - RTT_BSP='microblaze' # no scons
-
RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='mini4020' # no scons
-
RTT_BSP='mm32l07x'
# - RTT_BSP='nios_ii' # no scons
-
RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
-
RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
...
...
bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm0.a
0 → 100644
浏览文件 @
35eff9a8
文件已添加
bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_hardabi.a
0 → 100644
浏览文件 @
35eff9a8
文件已添加
bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/libpower_cm4_softabi.a
0 → 100644
浏览文件 @
35eff9a8
文件已添加
bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power.a
0 → 100644
浏览文件 @
35eff9a8
文件已添加
bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/iar_lib_power_m0.a
0 → 100644
浏览文件 @
35eff9a8
文件已添加
libcpu/arm/cortex-m7/cpu_cache.c
0 → 100644
浏览文件 @
35eff9a8
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-04-02 tanek first implementation
* 2019-04-27 misonyo update to cortex-m7 series
*/
#include <rthw.h>
#include <rtdef.h>
#include <board.h>
/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
#define L1CACHE_LINESIZE_BYTE (32)
void
rt_hw_cpu_icache_enable
(
void
)
{
SCB_EnableICache
();
}
void
rt_hw_cpu_icache_disable
(
void
)
{
SCB_DisableICache
();
}
rt_base_t
rt_hw_cpu_icache_status
(
void
)
{
return
0
;
}
void
rt_hw_cpu_icache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
rt_uint32_t
address
=
(
rt_uint32_t
)
addr
&
(
rt_uint32_t
)
~
(
L1CACHE_LINESIZE_BYTE
-
1
);
rt_int32_t
size_byte
=
size
+
address
-
(
rt_uint32_t
)
addr
;
rt_uint32_t
linesize
=
32U
;
if
(
ops
&
RT_HW_CACHE_INVALIDATE
)
{
__DSB
();
while
(
size_byte
>
0
)
{
SCB
->
ICIMVAU
=
address
;
address
+=
linesize
;
size_byte
-=
linesize
;
}
__DSB
();
__ISB
();
}
}
void
rt_hw_cpu_dcache_enable
(
void
)
{
SCB_EnableDCache
();
}
void
rt_hw_cpu_dcache_disable
(
void
)
{
SCB_DisableDCache
();
}
rt_base_t
rt_hw_cpu_dcache_status
(
void
)
{
return
0
;
}
void
rt_hw_cpu_dcache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
rt_uint32_t
startAddr
=
(
rt_uint32_t
)
addr
&
(
rt_uint32_t
)
~
(
L1CACHE_LINESIZE_BYTE
-
1
);
rt_uint32_t
size_byte
=
size
+
(
rt_uint32_t
)
addr
-
startAddr
;
if
(
ops
&
(
RT_HW_CACHE_FLUSH
|
RT_HW_CACHE_INVALIDATE
))
{
SCB_CleanInvalidateDCache_by_Addr
((
rt_uint32_t
*
)
startAddr
,
size_byte
);
}
else
if
(
ops
&
RT_HW_CACHE_FLUSH
)
{
SCB_CleanDCache_by_Addr
((
rt_uint32_t
*
)
startAddr
,
size_byte
);
}
else
if
(
ops
&
RT_HW_CACHE_INVALIDATE
)
{
SCB_InvalidateDCache_by_Addr
((
rt_uint32_t
*
)
startAddr
,
size_byte
);
}
else
{
RT_ASSERT
(
0
);
}
}
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