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提交 0c2aef2c 编写于 作者: W whsj2
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完善SWM320 BSP

上级 6420c277
展开全部 隐藏空白更改
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Showing with 47792 addition and 51 deletion
.github/workflows/action.yml
浏览文件 @ 0c2aef2c
......@@ -32,14 +32,14 @@ jobs:
- {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
......@@ -55,7 +55,7 @@ jobs:
- {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
- {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
- {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
......@@ -63,10 +63,10 @@ jobs:
- {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
......@@ -81,7 +81,7 @@ jobs:
- {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
......@@ -91,45 +91,46 @@ jobs:
- {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
steps:
- uses: actions/checkout@v2
- name: Set up Python
......@@ -144,13 +145,13 @@ jobs:
sudo apt-get -qq install gcc-multilib libsdl-dev scons
echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV
echo "RTT_CC=gcc" >> $GITHUB_ENV
- name: Install Arm ToolChains
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
shell: bash
run: |
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
/opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV
......@@ -158,8 +159,8 @@ jobs:
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
shell: bash
run: |
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2
sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2
sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt
/opt/mips-2016.05/bin/mips-sde-elf-gcc --version
echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV
......
bsp/swm320/.config 0 → 100644
浏览文件 @ 0c2aef2c
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_SWM320=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_CRC is not set
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_EXT_SRAM is not set
# CONFIG_BSP_USING_NOR_FLASH is not set
#
# Offboard Peripheral Drivers
#
bsp/swm320/Kconfig 0 → 100644
浏览文件 @ 0c2aef2c
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "drivers/Kconfig"
config SOC_SWM320
bool
select ARCH_ARM_CORTEX_M4
default y
bsp/swm320/README.md 0 → 100644
浏览文件 @ 0c2aef2c
# SWM320 BSP 说明
标签： SYNWIT、Cortex-M4、SWM320、国产MCU
---
## 简介
本文档为SWM320开发板提供的 BSP (板级支持包) 说明。
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
## 芯片介绍
- 内核
- 32位ARM® Cortex™-M4 内核
- 24位系统定时器
- 工作频率最高120MHz
- 硬件单周期乘法
- 集成嵌套向量中断控制器（NVIC），提供最多240个、8级可配置优先级的中断
- 通过SWD接口烧录
- 内置LDO
- 供电电压范围为2.0V至3.6V
- 片上SRAM存储器
- 128KB
- 片上FLASH存储器
- 128KB/256KB/512KB
- 支持用户定制ISP（在系统编程）更新用户程序
- 串行接口
- UART模块，具有独立8字节FIFO，最高支持主时钟16分频
- SPI模块，具有8字节独立FIFO，支持SPI、SSI协议，支持Master/slave模式
- I2C模块，支持7位、10位地址方式，支持Master/slave模式
- CAN模块，支持协议2.0A(11Bit标识符)和2.0B（29Bit标识符）
- PWM控制模块
- 12通道16位PWM产生器
- 可设置高电平结束或周期开始两种条件触发中断
- 具有普通、互补、中心对称等多种输出模式
- 支持死区控制
- ADC采样触发
- 定时器模块
- 6路32位通用定时器
- 具备独立中断
- 可做计数器使用
- 支持输入单脉冲捕获功能
- 32位看门狗定时器，溢出后可配置触发中断或复位芯片
- RTC模块
- 可自由设置日期（年、月、周、日）和时间（时、分、秒）
- 可自由设置闹钟（周、时、分、秒）
- 自动识别当前设置年份是否为闰年
- 支持RTC中断从Sleep模式下唤醒芯片
- DMA模块
- 支持存储器到存储器之间的数据搬运
- SRAMC模块
- 支持8位数据位宽和16位数据位宽的外部SRAM存储器
- 最大支持24位地址线
- SDRAMC模块
- 支持16Bit位宽的SDRAM
- 支持兼容PC133标准的SDRAM颗粒
- 支持2MB到32MB的外部SDRAM颗粒
- NORFLC模块
- 支持并行NOR FLASH接口
- 支持8位数据位宽和16位数据位宽的外部NOR FLASH存储器
- 最大支持24位地址线
- SDIO接口模块
- 支持标准SDIO接口协议
- TFT-LCD驱动模块
- 支持SYNC接口的外部LCD扩展
- 支持最高分辨率1024*768，实际分辨率可以配置
- 输出数据宽度16Bit
- 支持横屏和竖屏模式
- GPIO
- 最多可达100个GPIO
- 可配置2种IO模式
- 上拉输入
- 下拉输入
- 灵活的中断配置
- 触发类型设置（边沿检测、电平检测）
- 触发电平设置（高电平、低电平）
- 触发边沿设置（上升沿、下降沿、双边沿）
- 模拟外设
- 最多2个12位8通道高精度SAR ADC
- 采样率高达1M SPS
- 内建参考电压
- 支持single、scan两种模式
- 独立的结果寄存器
- 提供独立FIFO
- 可由软件、PWM触发
- 欠压检测（BOD）
- 支持欠压检测
- 支持欠压中断和复位选择
- 时钟源
- 20MHz/40MHz精度可达1%的片内时钟源
- 32K片内时钟源
- 2～32MHz片外晶振
芯片更多详细信息请参考[华芯微特技术支持][http://www.synwit.cn/support-1/3.html]。
## 编译说明
本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板
推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/swm320` 目录中，运行以下命令：
`scons`
来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。
## 烧写及执行
### 硬件连接
- 使用 USB B-Type 数据线连接开发板到 PC（注意：需要下载安装串口驱动支持 CH340 芯片，使用 MDK5 需要安装 SWM320 相关的 pack）。
> USB B-Type 数据线用于串口通讯，同时供电
- 使用 Jlink 连接开发板到 PC （需要 Jlink 驱动）
将串口 0 引脚为：`[PA2/PA3]`和 USB 转串口模块 P2 相连，串口配置方式为115200-N-8-1。
当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后，可以使用 ISP 的方式来烧写到设备中。
**建议使用 keil 软件直接下载**。ISP 下载较复杂。
### 运行结果
如果编译 & 烧写无误，当复位设备后，会在串口上看到板子上的蓝色LED闪烁。串口打印RT-Thread的启动logo信息：
```
\ | /
- RT - Thread Operating System
/ | \ 4.0.0 build Dec 11 2018
2006 - 2018 Copyright by rt-thread team
msh />
```
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :----------------------------------- |
| GPIO | 支持 | PA0, PA1... PP23 ---> PIN: 0, 1...100 |
| UART | 支持 | UART0/1/2/3 |
| ADC | 支持 | ADC0/1 |
| TIM | 支持 | TIM0/1/2/3/4/5 |
| I2C | 支持 | 软件 I2C0/1 |
| PWM | 支持 | PWM0/1/2/3/4/5 |
| RTC | 支持 | RTC |
| SPI | 支持 | SPI0/1 |
| WDT | 支持 | WDT |
| CRC | 支持 | CRC |
| SDIO | 支持 | SDIO |
| SRAM | 支持 | SRAM |
| NOR FLASH | 支持 | NOR FLASH |
| CAN | 暂不支持 | |
## 维护人信息
- [yanmowudi](https://github.com/yanmowudi)
- [邮箱](lik@synwit.cn)
## 参考资料
* [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
* [SWM320数据手册](http://www.synwit.cn/support-1/3.html)
bsp/swm320/SConscript 0 → 100644
浏览文件 @ 0c2aef2c
# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/swm320/SConstruct 0 → 100644
浏览文件 @ 0c2aef2c
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)
bsp/swm320/applications/SConscript 0 → 100644
浏览文件 @ 0c2aef2c
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Glob('*.c') + Glob('*.cpp')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/swm320/applications/main.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN 21
int main(void)
{
int count = 1;
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(1000);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(1000);
}
return RT_EOK;
}
// #ifdef RT_USING_PIN
// #define KEY1_PIN 25
// void key1_cb(void *args)
// {
// rt_kprintf("key1 irq!\n");
// }
// static int pin_sample(int argc, char *argv[])
// {
// rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING);
// rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL);
// rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE);
// return RT_EOK;
// }
// MSH_CMD_EXPORT(pin_sample, pin sample);
// #endif
#ifdef RT_USING_ADC
#define ADC_DEV_NAME "adc0"
#define ADC_DEV_CHANNEL 0
#define REFER_VOLTAGE 330
#define CONVERT_BITS (1 << 12)
static int adc_vol_sample(int argc, char *argv[])
{
rt_adc_device_t adc_dev;
rt_uint32_t value, vol;
rt_err_t ret = RT_EOK;
adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
if (adc_dev == RT_NULL)
{
rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
return RT_ERROR;
}
while (1)
{
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d,", value);
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
rt_thread_mdelay(500);
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
}
return ret;
}
MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);
#endif
#ifdef RT_USING_HWTIMER
#define HWTIMER_DEV_NAME "timer0"
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
rt_kprintf("this is hwtimer timeout callback fucntion!\n");
rt_kprintf("tick is :%d !\n", rt_tick_get());
return 0;
}
static int hwtimer_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_hwtimerval_t timeout_s;
rt_device_t hw_dev = RT_NULL;
rt_hwtimer_mode_t mode;
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
rt_device_set_rx_indicate(hw_dev, timeout_cb);
mode = HWTIMER_MODE_PERIOD;
//mode = HWTIMER_MODE_ONESHOT;
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
if (ret != RT_EOK)
{
rt_kprintf("set mode failed! ret is :%d\n", ret);
return ret;
}
timeout_s.sec = 2;
timeout_s.usec = 0;
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
{
rt_kprintf("set timeout value failed\n");
return RT_ERROR;
}
rt_thread_mdelay(3500);
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
#endif
#ifdef RT_USING_PWM
#define PWM_DEV_NAME "pwm0" /* PWM???? */
#define PWM_DEV_CHANNEL 0 /* PWM?? */
struct rt_device_pwm *pwm_dev; /* PWM???? */
static int pwm_sample(int argc, char *argv[])
{
rt_uint32_t period, pulse;
period = 500000; /* ???0.5ms,?????ns */
pulse = 250000; /* PWM?????,?????ns */
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
{
rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
return RT_ERROR;
}
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
return RT_EOK;
}
MSH_CMD_EXPORT(pwm_sample, pwm sample);
#endif
#ifdef RT_USING_RTC
static int rtc_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
time_t now;
ret = set_date(2020, 6, 15);
if (ret != RT_EOK)
{
rt_kprintf("set RTC date failed\n");
return ret;
}
ret = set_time(11, 15, 50);
if (ret != RT_EOK)
{
rt_kprintf("set RTC time failed\n");
return ret;
}
rt_thread_mdelay(3000);
now = time(RT_NULL);
rt_kprintf("%s\n", ctime(&now));
return ret;
}
MSH_CMD_EXPORT(rtc_sample, rtc sample);
#endif
#ifdef RT_USING_WDT
#define WDT_DEVICE_NAME "wdt"
static rt_device_t wdg_dev;
static void idle_hook(void)
{
rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL);
rt_kprintf("feed the dog!\n ");
}
static int wdt_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_uint32_t timeout = 1;
char device_name[RT_NAME_MAX];
if (argc == 2)
{
rt_strncpy(device_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX);
}
wdg_dev = rt_device_find(device_name);
if (!wdg_dev)
{
rt_kprintf("find %s failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_init(wdg_dev);
if (ret != RT_EOK)
{
rt_kprintf("initialize %s failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout);
if (ret != RT_EOK)
{
rt_kprintf("set %s timeout failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
if (ret != RT_EOK)
{
rt_kprintf("start %s failed!\n", device_name);
return -RT_ERROR;
}
// rt_thread_idle_sethook(idle_hook);
return ret;
}
MSH_CMD_EXPORT(wdt_sample, wdt sample);
#endif
#ifdef RT_USING_SPI
#define W25Q_SPI_DEVICE_NAME "spi00"
#define W25Q_FLASH_NAME "norflash0"
#include "drv_spi.h"
#include "spi_flash_sfud.h"
#include "dfs_posix.h"
static int rt_hw_spi_flash_init(void)
{
rt_hw_spi_device_attach("spi0", "spi00", GPIOA, PIN12);
if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME))
{
return -RT_ERROR;
};
return RT_EOK;
}
/* ???????? */
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
static void spi_w25q_sample(int argc, char *argv[])
{
struct rt_spi_device *spi_dev_w25q;
char name[RT_NAME_MAX];
rt_uint8_t w25x_read_id = 0x90;
rt_uint8_t id[5] = {0};
if (argc == 2)
{
rt_strncpy(name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX);
}
/* ?? spi ???????? */
spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name);
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB;
cfg.max_hz = 20 * 1000 * 1000; /* 20M */
rt_spi_configure(spi_dev_w25q, &cfg);
if (!spi_dev_w25q)
{
rt_kprintf("spi sample run failed! can't find %s device!\n", name);
}
else
{
/* ??1:?? rt_spi_send_then_recv()??????ID */
rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5);
rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]);
/* ??2:?? rt_spi_transfer_message()??????ID */
struct rt_spi_message msg1, msg2;
msg1.send_buf = &w25x_read_id;
msg1.recv_buf = RT_NULL;
msg1.length = 1;
msg1.cs_take = 1;
msg1.cs_release = 0;
msg1.next = &msg2;
msg2.send_buf = RT_NULL;
msg2.recv_buf = id;
msg2.length = 5;
msg2.cs_take = 0;
msg2.cs_release = 1;
msg2.next = RT_NULL;
rt_spi_transfer_message(spi_dev_w25q, &msg1);
rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
}
}
static void spi_flash_elmfat_sample(void)
{
int fd, size;
struct statfs elm_stat;
char str[] = "elmfat mount to W25Q flash.\r\n", buf[80];
if (dfs_mkfs("elm", W25Q_FLASH_NAME) == 0)
rt_kprintf("make elmfat filesystem success.\n");
if (dfs_mount(W25Q_FLASH_NAME, "/", "elm", 0, 0) == 0)
rt_kprintf("elmfat filesystem mount success.\n");
if (statfs("/", &elm_stat) == 0)
rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
if (mkdir("/user", 0x777) == 0)
rt_kprintf("make a directory: '/user'.\n");
rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
/* ????????????,??????????????*/
fd = open("/user/test.txt", O_WRONLY | O_CREAT);
if (fd >= 0)
{
if (write(fd, str, sizeof(str)) == sizeof(str))
rt_kprintf("Write data done.\n");
close(fd);
}
/* ????????? */
fd = open("/user/test.txt", O_RDONLY);
if (fd >= 0)
{
size = read(fd, buf, sizeof(buf));
close(fd);
if (size == sizeof(str))
rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
}
}
MSH_CMD_EXPORT(spi_flash_elmfat_sample, spi flash elmfat sample);
MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
#endif
//#ifdef RT_USING_SPI
//#define SD_SPI_DEVICE_NAME "spi10"
//#define SDCARD_NAME "sd0"
//#include "drv_spi.h"
//#include "dfs_posix.h"
//#include "spi_msd.h"
//static int rt_hw_spi1_tfcard(void)
//{
// rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6);
// return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME);
//}
//INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard);
//static void elmfat_sample(void)
//{
// int fd, size;
// struct statfs elm_stat;
// char str[] = "elmfat mount to sdcard.\r\n", buf[80];
// if (dfs_mkfs("elm", SDCARD_NAME) == 0)
// rt_kprintf("make elmfat filesystem success.\n");
// if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0)
// rt_kprintf("elmfat filesystem mount success.\n");
// if (statfs("/", &elm_stat) == 0)
// rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
// elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
// if (mkdir("/user", 0x777) == 0)
// rt_kprintf("make a directory: '/user'.\n");
// rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
// fd = open("/user/test.txt", O_WRONLY | O_CREAT);
// if (fd >= 0)
// {
// if (write(fd, str, sizeof(str)) == sizeof(str))
// rt_kprintf("Write data done.\n");
// close(fd);
// }
// fd = open("/user/test.txt", O_RDONLY);
// if (fd >= 0)
// {
// size = read(fd, buf, sizeof(buf));
// close(fd);
// if (size == sizeof(str))
// rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
// }
//}
//MSH_CMD_EXPORT(elmfat_sample, elmfat sample);
//#endif
#ifdef RT_USING_SDIO
#define SDCARD_NAME "sd0"
#include "dfs_posix.h"
static void sdio_elmfat_sample(void)
{
int fd, size;
struct statfs elm_stat;
char str[] = "elmfat mount to sdcard.\n", buf[80];
if (dfs_mkfs("elm", SDCARD_NAME) == 0)
rt_kprintf("make elmfat filesystem success.\n");
if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0)
rt_kprintf("elmfat filesystem mount success.\n");
if (statfs("/", &elm_stat) == 0)
rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
if (mkdir("/user", 0x777) == 0)
rt_kprintf("make a directory: '/user'.\n");
rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
fd = open("/user/test.txt", O_WRONLY | O_CREAT);
if (fd >= 0)
{
if (write(fd, str, sizeof(str)) == sizeof(str))
rt_kprintf("Write data done.\n");
close(fd);
}
fd = open("/user/test.txt", O_RDONLY);
if (fd >= 0)
{
size = read(fd, buf, sizeof(buf));
close(fd);
if (size == sizeof(str))
rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
}
}
MSH_CMD_EXPORT(sdio_elmfat_sample, sdio elmfat sample);
#endif
#ifdef RT_USING_HWCRYPTO
static void crypto_sample(void)
{
rt_uint8_t temp[] = {0, 1, 2, 3, 4, 5, 6, 7};
struct rt_hwcrypto_ctx *ctx;
rt_uint32_t result = 0;
struct hwcrypto_crc_cfg cfg =
{
.last_val = 0x0,
.poly = 0x04C11DB7,
.width = 8,
.xorout = 0x00000000,
.flags = 0,
};
ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32);
rt_hwcrypto_crc_cfg(ctx, &cfg);
result = rt_hwcrypto_crc_update(ctx, temp, sizeof(temp));
rt_kprintf("result: 0x%08x \n", result);
rt_hwcrypto_crc_destroy(ctx);
}
MSH_CMD_EXPORT(crypto_sample, crypto sample);
#endif
#ifdef BSP_USING_NOR_FLASH
#define NORFLASH_DEV_NAME "nor"
static int norflash_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_device_t hw_dev = RT_NULL;
hw_dev = rt_device_find(NORFLASH_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("norflash sample run failed! can't find %s device!\n", NORFLASH_DEV_NAME);
return RT_ERROR;
}
else
{
rt_kprintf("norflash sample run success! find %s device!\n", NORFLASH_DEV_NAME);
}
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", NORFLASH_DEV_NAME);
return ret;
}
else
{
rt_kprintf("open %s device success!\n", NORFLASH_DEV_NAME);
}
struct rt_mtd_nor_device *hw_nor;
hw_nor = RT_MTD_NOR_DEVICE(hw_dev);
long id = hw_nor->ops->read_id(hw_nor);
rt_kprintf("id = %08x!\n", id);
// rt_device_set_rx_indicate(hw_dev, timeout_cb);
// mode = HWTIMER_MODE_PERIOD;
// //mode = HWTIMER_MODE_ONESHOT;
// ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
// if (ret != RT_EOK)
// {
// rt_kprintf("set mode failed! ret is :%d\n", ret);
// return ret;
// }
// timeout_s.sec = 2;
// timeout_s.usec = 0;
// if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
// {
// rt_kprintf("set timeout value failed\n");
// return RT_ERROR;
// }
// rt_thread_mdelay(3500);
// rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
// rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
MSH_CMD_EXPORT(norflash_sample, norflash sample);
#endif
bsp/swm320/drivers/Kconfig 0 → 100644
浏览文件 @ 0c2aef2c
menu "Hardware Drivers Config"
config SOC_SWM320
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0 (A2/RX,A3/TX)"
default y
config BSP_USING_UART1
bool "Enable UART1 (C2/RX,C3/TX)"
default n
config BSP_USING_UART2
bool "Enable UART2 (C4/RX,C5/TX)"
default n
config BSP_USING_UART3
bool "Enable UART3 (C6/RX,C7/TX)"
default n
endif
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
if BSP_USING_ADC0
config BSP_USING_ADC0_CHN0
bool "Enable ADC0_CHN0"
default n
config BSP_USING_ADC0_CHN1
bool "Enable ADC0_CHN1"
default n
config BSP_USING_ADC0_CHN2
bool "Enable ADC0_CHN2"
default n
config BSP_USING_ADC0_CHN3
bool "Enable ADC0_CHN3"
default n
config BSP_USING_ADC0_CHN4
bool "Enable ADC0_CHN4(A12)"
default n
config BSP_USING_ADC0_CHN5
bool "Enable ADC0_CHN5(A11)"
default n
config BSP_USING_ADC0_CHN6
bool "Enable ADC0_CHN6(A10)"
default n
config BSP_USING_ADC0_CHN7
bool "Enable ADC0_CHN7(A9)"
default n
endif
config BSP_USING_ADC1
bool "Enable ADC1"
default n
if BSP_USING_ADC1
config BSP_USING_ADC1_CHN0
bool "Enable ADC1_CHN0(C7)"
default n
config BSP_USING_ADC1_CHN1
bool "Enable ADC1_CHN1(C6)"
default n
config BSP_USING_ADC1_CHN2
bool "Enable ADC1_CHN2(C5)"
default n
config BSP_USING_ADC1_CHN3
bool "Enable ADC1_CHN3(C4)"
default n
config BSP_USING_ADC1_CHN4
bool "Enable ADC1_CHN4(N0)"
default n
config BSP_USING_ADC1_CHN5
bool "Enable ADC1_CHN5(N1)"
default n
config BSP_USING_ADC1_CHN6
bool "Enable ADC1_CHN6(N2)"
default n
config BSP_USING_ADC1_CHN7
bool "Enable ADC1_CHN7"
default n
endif
endif
menuconfig BSP_USING_TIM
bool "Enable HWTIMER"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM0
bool "Enable TIM0"
default n
config BSP_USING_TIM1
bool "Enable TIM1"
default n
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
config BSP_USING_TIM4
bool "Enable TIM4"
default n
config BSP_USING_TIM5
bool "Enable TIM5"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default n
if BSP_USING_I2C0
comment "Notice: PC2 --> 28; PC3 --> 29"
config BSP_I2C0_SCL_PIN
int "I2C0 scl pin number"
range 0 99
default 28
config BSP_I2C0_SDA_PIN
int "I2C0 sda pin number"
range 0 99
default 29
endif
config BSP_USING_I2C1
bool "Enable I2C1"
default n
if BSP_USING_I2C1
comment "Notice: PC6 --> 32; PC7 --> 33"
config BSP_I2C1_SCL_PIN
int "I2C1 scl pin number"
range 0 99
default 32
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 99
default 33
endif
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config BSP_USING_PWM0
bool "Enable PWM0"
default n
if BSP_USING_PWM0
config BSP_USING_PWM0A
bool "Enable PWM0A (C2)"
default n
config BSP_USING_PWM0B
bool "Enable PWM0B (C4)"
default n
endif
config BSP_USING_PWM1
bool "Enable PWM1"
default n
if BSP_USING_PWM1
config BSP_USING_PWM1A
bool "Enable PWM1A (C3)"
default n
config BSP_USING_PWM1B
bool "Enable PWM1B (C5)"
default n
endif
config BSP_USING_PWM2
bool "Enable PWM2"
default n
if BSP_USING_PWM2
config BSP_USING_PWM2A
bool "Enable PWM2A (N4)"
default n
config BSP_USING_PWM2B
bool "Enable PWM2B (N6)"
default n
endif
config BSP_USING_PWM3
bool "Enable PWM3"
default n
if BSP_USING_PWM3
config BSP_USING_PWM3A
bool "Enable PWM3A (N3)"
default n
config BSP_USING_PWM3B
bool "Enable PWM3B (N5)"
default n
endif
config BSP_USING_PWM4
bool "Enable PWM4"
default n
if BSP_USING_PWM4
config BSP_USING_PWM4A
bool "Enable PWM4A (N8)"
default n
config BSP_USING_PWM4B
bool "Enable PWM4B (N10)"
default n
endif
config BSP_USING_PWM5
bool "Enable PWM5"
default n
if BSP_USING_PWM5
config BSP_USING_PWM5A
bool "Enable PWM5A (N7)"
default n
config BSP_USING_PWM5B
bool "Enable PWM5B (N9)"
default n
endif
endif
config BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS(CS/A12,MISO/A11,MOSI/A10,CLK/A9)"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS(CS/C4,MISO/C5,MOSI/C6,CLK/C7)"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_CRC
bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_CRC
default n
endmenu
menu "Onboard Peripheral Drivers"
config BSP_USING_SDIO
bool "Enable SDCARD (sdio)"
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
menuconfig BSP_USING_EXT_SRAM
bool "Enable external sram"
select RT_USING_MEMHEAP
select RT_USING_MEMHEAP_AS_HEAP
default n
if BSP_USING_EXT_SRAM
config BSP_EXT_SRAM_SIZE
hex "external sram size"
default 0x100000
endif
menuconfig BSP_USING_NOR_FLASH
bool "Enable mtd nor flash"
select RT_USING_MTD_NOR
select PKG_USING_FTL_SRC
default n
if BSP_USING_NOR_FLASH
config BSP_NOR_FLASH_SIZE
hex "mtd nor flash size"
default 0x1000000
config BSP_NOR_FLASH_SECTOR_SIZE
hex "mtd nor flsah sector"
default 0x10000
endif
endmenu
menu "Offboard Peripheral Drivers"
endmenu
endmenu
bsp/swm320/drivers/SConscript 0 → 100644
浏览文件 @ 0c2aef2c
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Split('''
board.c
''')
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['drv_hwtimer.c']
if GetDepend(['RT_USING_I2C']):
src += ['drv_soft_i2c.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['RT_USING_RTC']):
src += ['drv_rtc.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['RT_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['RT_USING_HWCRYPTO']):
src += ['drv_crypto.c']
if GetDepend(['BSP_USING_EXT_SRAM']):
src += ['drv_sram.c']
if GetDepend(['BSP_USING_NOR_FLASH']):
src += ['drv_nor_flash.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/swm320/drivers/board.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee format file
*/
#include "board.h"
static void bsp_clock_config(void)
{
SystemInit();
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
SysTick->CTRL |= 0x00000004UL;
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
void rt_hw_board_init()
{
bsp_clock_config();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
bsp/swm320/drivers/board.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee format file
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <string.h>
#include <SWM320.h>
#ifdef __cplusplus
extern "C"
{
#endif
#define SRAM_BASE 0x20000000
#define SRAM_SIZE 0x20000
#define SRAM_END (SRAM_BASE + SRAM_SIZE)
#ifdef BSP_USING_EXT_SRAM
#define EXT_SRAM_BASE SRAMM_BASE
#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE
#define EXT_SRAM_BEGIN EXT_SRAM_BASE
#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE)
#endif
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END SRAM_END
#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
void rt_hw_board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */
bsp/swm320/drivers/drv_adc.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-5-26 lik first version
*/
#include "drv_adc.h"
#ifdef RT_USING_ADC
#ifdef BSP_USING_ADC
//#define DRV_DEBUG
#define LOG_TAG "drv.adc"
#include <drv_log.h>
static struct swm_adc_cfg adc_cfg[] =
{
#ifdef BSP_USING_ADC0
ADC0_CFG,
#endif
#ifdef BSP_USING_ADC1
ADC1_CFG,
#endif
};
static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])];
static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
{
struct swm_adc_cfg *cfg = RT_NULL;
RT_ASSERT(adc_device != RT_NULL);
cfg = adc_device->parent.user_data;
if (enabled)
{
ADC_Open(cfg->ADCx);
}
else
{
ADC_Close(cfg->ADCx);
}
return RT_EOK;
}
static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
{
rt_uint32_t swm_channel = 0;
switch (channel)
{
case 0:
swm_channel = ADC_CH0;
break;
case 1:
swm_channel = ADC_CH1;
break;
case 2:
swm_channel = ADC_CH2;
break;
case 3:
swm_channel = ADC_CH3;
break;
case 4:
swm_channel = ADC_CH4;
break;
case 5:
swm_channel = ADC_CH5;
break;
case 6:
swm_channel = ADC_CH6;
break;
case 7:
swm_channel = ADC_CH7;
break;
}
return swm_channel;
}
static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
{
uint32_t adc_chn;
struct swm_adc_cfg *cfg = RT_NULL;
RT_ASSERT(adc_device != RT_NULL);
RT_ASSERT(value != RT_NULL);
cfg = adc_device->parent.user_data;
if (channel < 8)
{
/* set stm32 ADC channel */
adc_chn = swm_adc_get_channel(channel);
}
else
{
LOG_E("ADC channel must be between 0 and 7.");
return -RT_ERROR;
}
/* start ADC */
ADC_Start(cfg->ADCx);
/* Wait for the ADC to convert */
while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0)
;
/* get ADC value */
*value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn);
return RT_EOK;
}
static const struct rt_adc_ops swm_adc_ops =
{
.enabled = swm_adc_enabled,
.convert = swm_get_adc_value,
};
static int rt_hw_adc_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++)
{
/* ADC init */
adc_drv[i].cfg = &adc_cfg[i];
if (adc_drv[i].cfg->ADCx == ADC0)
{
#ifdef BSP_USING_ADC0_CHN0
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
#endif
#ifdef BSP_USING_ADC0_CHN1
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
#endif
#ifdef BSP_USING_ADC0_CHN2
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
#endif
#ifdef BSP_USING_ADC0_CHN3
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
#endif
#ifdef BSP_USING_ADC0_CHN4
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4
#endif
#ifdef BSP_USING_ADC0_CHN5
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5
#endif
#ifdef BSP_USING_ADC0_CHN6
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6
#endif
#ifdef BSP_USING_ADC0_CHN7
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9 => ADC0.CH7
#endif
}
else if (adc_drv[i].cfg->ADCx == ADC1)
{
#ifdef BSP_USING_ADC1_CHN0
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0
#endif
#ifdef BSP_USING_ADC1_CHN1
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1
#endif
#ifdef BSP_USING_ADC1_CHN2
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2
#endif
#ifdef BSP_USING_ADC1_CHN3
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3
#endif
#ifdef BSP_USING_ADC1_CHN4
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4
#endif
#ifdef BSP_USING_ADC1_CHN5
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5
#endif
#ifdef BSP_USING_ADC1_CHN6
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6
#endif
#ifdef BSP_USING_ADC1_CHN7
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
#endif
}
ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct));
ADC_Open(adc_drv[i].cfg->ADCx);
/* register ADC device */
if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK)
{
LOG_D("%s init success", adc_drv[i].cfg->name);
}
else
{
LOG_E("%s register failed", adc_drv[i].cfg->name);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(rt_hw_adc_init);
#endif /* BSP_USING_ADC */
#endif /* RT_USING_ADC */
bsp/swm320/drivers/drv_adc.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-5-26 lik first version
*/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
#include "board.h"
struct swm_adc_cfg
{
const char *name;
ADC_TypeDef *ADCx;
ADC_InitStructure adc_initstruct;
};
struct swm_adc
{
struct swm_adc_cfg *cfg;
struct rt_adc_device adc_device;
};
#ifdef BSP_USING_ADC0
#ifndef ADC0_CFG
#define ADC0_CFG \
{ \
.name = "adc0", \
.ADCx = ADC0, \
.adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
.adc_initstruct.clk_div = 25, \
.adc_initstruct.pga_ref = PGA_REF_INTERNAL, \
.adc_initstruct.channels = 0, \
.adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
.adc_initstruct.trig_src = ADC_TRIGSRC_SW, \
.adc_initstruct.Continue = 0, \
.adc_initstruct.EOC_IEn = 0, \
.adc_initstruct.OVF_IEn = 0, \
.adc_initstruct.HFULL_IEn = 0, \
.adc_initstruct.FULL_IEn = 0, \
}
#endif /* ADC0_CFG */
#endif /* BSP_USING_ADC0 */
#ifdef BSP_USING_ADC1
#ifndef ADC1_CFG
#define ADC1_CFG \
{ \
.name = "adc1", \
.ADCx = ADC1, \
.adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
.adc_initstruct.clk_div = 25, \
.adc_initstruct.pga_ref = PGA_REF_INTERNAL, \
.adc_initstruct.channels = 0, \
.adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
.adc_initstruct.trig_src = ADC_TRIGSRC_SW, \
.adc_initstruct.Continue = 0, \
.adc_initstruct.EOC_IEn = 0, \
.adc_initstruct.OVF_IEn = 0, \
.adc_initstruct.HFULL_IEn = 0, \
.adc_initstruct.FULL_IEn = 0, \
}
#endif /* ADC1_CFG */
#endif /* BSP_USING_ADC1 */
#endif /* __DRV_ADC_H__ */
bsp/swm320/drivers/drv_crypto.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-10 lik first version
*/
#include "drv_crypto.h"
#include <string.h>
#ifdef RT_USING_HWCRYPTO
struct swm_hwcrypto_device
{
struct rt_hwcrypto_device dev;
struct rt_mutex mutex;
};
#ifdef BSP_USING_CRC
struct hash_ctx_des
{
struct swm_crc_cfg contex;
};
static struct hwcrypto_crc_cfg crc_backup_cfg;
static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
{
rt_uint32_t result = 0;
struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data;
struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex);
rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER);
if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
{
hw_crc_cfg->CRCx = CRC;
hw_crc_cfg->inival = ctx->crc_cfg.last_val;
switch (ctx->crc_cfg.width)
{
case 8:
hw_crc_cfg->crc_inbits = 2;
break;
case 16:
hw_crc_cfg->crc_inbits = 1;
break;
case 32:
hw_crc_cfg->crc_inbits = 0;
break;
default:
goto _exit;
}
switch (ctx->crc_cfg.poly)
{
case 0x1021:
hw_crc_cfg->crc_1632 = 1;
break;
case 0x04C11DB7:
hw_crc_cfg->crc_1632 = 0;
break;
default:
goto _exit;
}
hw_crc_cfg->crc_out_not = 0;
switch (ctx->crc_cfg.flags)
{
case 0:
case CRC_FLAG_REFIN:
hw_crc_cfg->crc_out_rev = 0;
break;
case CRC_FLAG_REFOUT:
case CRC_FLAG_REFIN | CRC_FLAG_REFOUT:
hw_crc_cfg->crc_out_rev = 1;
break;
default:
goto _exit;
}
CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival);
memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg));
}
for (uint32_t i = 0; i < length; i++)
CRC_Write((uint32_t)in[i]);
result = CRC_Result();
ctx->crc_cfg.last_val = result;
crc_backup_cfg.last_val = ctx->crc_cfg.last_val;
result = (result ? result ^ (ctx->crc_cfg.xorout) : result);
_exit:
rt_mutex_release(&swm_hw_dev->mutex);
return result;
}
static const struct hwcrypto_crc_ops crc_ops =
{
.update = _crc_update,
};
static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
{
rt_err_t res = RT_EOK;
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
{
struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg));
if (RT_NULL == contex)
{
res = -RT_ERROR;
break;
}
contex->CRCx = DEFAULT_CRC;
contex->inival = DEFAULT_INIVAL;
contex->crc_inbits = DEFAULT_INBITS;
contex->crc_1632 = DEFAULT_CRC1632;
contex->crc_out_not = DEFAULT_OUT_NOT;
contex->crc_out_rev = DEFAULT_OUT_REV;
ctx->contex = contex;
((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
break;
}
#endif /* BSP_USING_CRC */
default:
res = -RT_ERROR;
break;
}
return res;
}
static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
{
struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
break;
#endif /* BSP_USING_CRC */
default:
break;
}
rt_free(ctx->contex);
}
static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
rt_err_t res = RT_EOK;
switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
}
break;
#endif /* BSP_USING_CRC */
default:
res = -RT_ERROR;
break;
}
return res;
}
static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
{
struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
break;
#endif /* BSP_USING_CRC */
default:
break;
}
}
static const struct rt_hwcrypto_ops _ops =
{
.create = _crypto_create,
.destroy = _crypto_destroy,
.copy = _crypto_clone,
.reset = _crypto_reset,
};
int rt_hw_crypto_init(void)
{
static struct swm_hwcrypto_device _crypto_dev;
rt_uint32_t cpuid[2] = {0};
_crypto_dev.dev.ops = &_ops;
cpuid[0] = SCB->CPUID;
_crypto_dev.dev.id = 0;
rt_memcpy(&_crypto_dev.dev.id, cpuid, 8);
_crypto_dev.dev.user_data = &_crypto_dev;
if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
{
return -1;
}
rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO);
return 0;
}
INIT_BOARD_EXPORT(rt_hw_crypto_init);
#endif /* BSP_USING_WDT */
#endif /* RT_USING_WDT */
bsp/swm320/drivers/drv_crypto.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-10 lik first version
*/
#ifndef __DRV_CRYPTO_H__
#define __DRV_CRYPTO_H__
#include "board.h"
/* swm config class */
struct swm_crc_cfg
{
CRC_TypeDef *CRCx;
uint32_t inival;
uint8_t crc_inbits;
uint8_t crc_1632;
uint8_t crc_out_not;
uint8_t crc_out_rev;
};
#ifdef BSP_USING_CRC
#define DEFAULT_CRC (CRC)
#define DEFAULT_INIVAL (0x00000000)
#define DEFAULT_INBITS (2)
#define DEFAULT_CRC1632 (0)
#define DEFAULT_OUT_NOT (0)
#define DEFAULT_OUT_REV (0)
#endif /* BSP_USING_CRC */
int rt_hw_crypto_init(void);
#endif /* __DRV_CRYPTO_H__ */
bsp/swm320/drivers/drv_gpio.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee fix bug
* 2020-07-10 lik rewrite
*/
#include "drv_gpio.h"
#ifdef RT_USING_PIN
#ifdef BSP_USING_GPIO
static const struct swm_pin_index pins[] =
{
__SWM_PIN(0, A, 0),
__SWM_PIN(1, A, 1),
__SWM_PIN(2, A, 2),
__SWM_PIN(3, A, 3),
__SWM_PIN(4, A, 4),
__SWM_PIN(5, A, 5),
__SWM_PIN(6, A, 6),
__SWM_PIN(7, A, 7),
__SWM_PIN(8, A, 8),
__SWM_PIN(9, A, 9),
__SWM_PIN(10, A, 10),
__SWM_PIN(11, A, 11),
__SWM_PIN(12, A, 12),
__SWM_PIN(13, B, 0),
__SWM_PIN(14, B, 1),
__SWM_PIN(15, B, 2),
__SWM_PIN(16, B, 3),
__SWM_PIN(17, B, 4),
__SWM_PIN(18, B, 5),
__SWM_PIN(19, B, 6),
__SWM_PIN(20, B, 7),
__SWM_PIN(21, B, 8),
__SWM_PIN(22, B, 9),
__SWM_PIN(23, B, 10),
__SWM_PIN(24, B, 11),
__SWM_PIN(25, B, 12),
__SWM_PIN(26, C, 0),
__SWM_PIN(27, C, 1),
__SWM_PIN(28, C, 2),
__SWM_PIN(29, C, 3),
__SWM_PIN(30, C, 4),
__SWM_PIN(31, C, 5),
__SWM_PIN(32, C, 6),
__SWM_PIN(33, C, 7),
__SWM_PIN(34, M, 0),
__SWM_PIN(35, M, 1),
__SWM_PIN(36, M, 2),
__SWM_PIN(37, M, 3),
__SWM_PIN(38, M, 4),
__SWM_PIN(39, M, 5),
__SWM_PIN(40, M, 6),
__SWM_PIN(41, M, 7),
__SWM_PIN(42, M, 8),
__SWM_PIN(43, M, 9),
__SWM_PIN(44, M, 10),
__SWM_PIN(45, M, 11),
__SWM_PIN(46, M, 12),
__SWM_PIN(47, M, 13),
__SWM_PIN(48, M, 14),
__SWM_PIN(49, M, 15),
__SWM_PIN(50, M, 16),
__SWM_PIN(51, M, 17),
__SWM_PIN(52, M, 18),
__SWM_PIN(53, M, 19),
__SWM_PIN(54, M, 20),
__SWM_PIN(55, M, 21),
__SWM_PIN(56, N, 0),
__SWM_PIN(57, N, 1),
__SWM_PIN(58, N, 2),
__SWM_PIN(59, N, 3),
__SWM_PIN(60, N, 4),
__SWM_PIN(61, N, 5),
__SWM_PIN(62, N, 6),
__SWM_PIN(63, N, 7),
__SWM_PIN(64, N, 8),
__SWM_PIN(65, N, 9),
__SWM_PIN(66, N, 10),
__SWM_PIN(67, N, 11),
__SWM_PIN(68, N, 12),
__SWM_PIN(69, N, 13),
__SWM_PIN(70, N, 14),
__SWM_PIN(71, N, 15),
__SWM_PIN(72, N, 16),
__SWM_PIN(73, N, 17),
__SWM_PIN(74, N, 18),
__SWM_PIN(75, N, 19),
__SWM_PIN(76, P, 0),
__SWM_PIN(77, P, 1),
__SWM_PIN(78, P, 2),
__SWM_PIN(79, P, 3),
__SWM_PIN(80, P, 4),
__SWM_PIN(81, P, 5),
__SWM_PIN(82, P, 6),
__SWM_PIN(83, P, 7),
__SWM_PIN(84, P, 8),
__SWM_PIN(85, P, 9),
__SWM_PIN(86, P, 10),
__SWM_PIN(87, P, 11),
__SWM_PIN(88, P, 12),
__SWM_PIN(89, P, 13),
__SWM_PIN(90, P, 14),
__SWM_PIN(91, P, 15),
__SWM_PIN(92, P, 16),
__SWM_PIN(93, P, 17),
__SWM_PIN(94, P, 18),
__SWM_PIN(95, P, 19),
__SWM_PIN(96, P, 20),
__SWM_PIN(97, P, 21),
__SWM_PIN(98, P, 22),
__SWM_PIN(99, P, 23)};
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{0, 0, RT_NULL, RT_NULL},
{1, 0, RT_NULL, RT_NULL},
{2, 0, RT_NULL, RT_NULL},
{3, 0, RT_NULL, RT_NULL},
{4, 0, RT_NULL, RT_NULL},
{5, 0, RT_NULL, RT_NULL},
{6, 0, RT_NULL, RT_NULL},
{7, 0, RT_NULL, RT_NULL},
{8, 0, RT_NULL, RT_NULL},
{9, 0, RT_NULL, RT_NULL},
{10, 0, RT_NULL, RT_NULL},
{11, 0, RT_NULL, RT_NULL},
{12, 0, RT_NULL, RT_NULL},
{13, 0, RT_NULL, RT_NULL},
{14, 0, RT_NULL, RT_NULL},
{15, 0, RT_NULL, RT_NULL},
{16, 0, RT_NULL, RT_NULL},
{17, 0, RT_NULL, RT_NULL},
{18, 0, RT_NULL, RT_NULL},
{19, 0, RT_NULL, RT_NULL},
{20, 0, RT_NULL, RT_NULL},
{21, 0, RT_NULL, RT_NULL},
{22, 0, RT_NULL, RT_NULL},
{23, 0, RT_NULL, RT_NULL},
{24, 0, RT_NULL, RT_NULL},
{25, 0, RT_NULL, RT_NULL},
{26, 0, RT_NULL, RT_NULL},
{27, 0, RT_NULL, RT_NULL},
{28, 0, RT_NULL, RT_NULL},
{29, 0, RT_NULL, RT_NULL},
{30, 0, RT_NULL, RT_NULL},
{31, 0, RT_NULL, RT_NULL},
{32, 0, RT_NULL, RT_NULL},
{33, 0, RT_NULL, RT_NULL},
{34, 0, RT_NULL, RT_NULL},
{35, 0, RT_NULL, RT_NULL},
{36, 0, RT_NULL, RT_NULL},
{37, 0, RT_NULL, RT_NULL},
{38, 0, RT_NULL, RT_NULL},
{39, 0, RT_NULL, RT_NULL},
{40, 0, RT_NULL, RT_NULL},
{41, 0, RT_NULL, RT_NULL},
{42, 0, RT_NULL, RT_NULL},
{43, 0, RT_NULL, RT_NULL},
{44, 0, RT_NULL, RT_NULL},
{45, 0, RT_NULL, RT_NULL},
{46, 0, RT_NULL, RT_NULL},
{47, 0, RT_NULL, RT_NULL},
{48, 0, RT_NULL, RT_NULL},
{49, 0, RT_NULL, RT_NULL},
{50, 0, RT_NULL, RT_NULL},
{51, 0, RT_NULL, RT_NULL},
{52, 0, RT_NULL, RT_NULL},
{53, 0, RT_NULL, RT_NULL},
{54, 0, RT_NULL, RT_NULL},
{55, 0, RT_NULL, RT_NULL},
{56, 0, RT_NULL, RT_NULL},
{57, 0, RT_NULL, RT_NULL},
{58, 0, RT_NULL, RT_NULL},
{59, 0, RT_NULL, RT_NULL},
{60, 0, RT_NULL, RT_NULL},
{61, 0, RT_NULL, RT_NULL},
{62, 0, RT_NULL, RT_NULL},
{63, 0, RT_NULL, RT_NULL},
{64, 0, RT_NULL, RT_NULL},
{65, 0, RT_NULL, RT_NULL},
{66, 0, RT_NULL, RT_NULL},
{67, 0, RT_NULL, RT_NULL},
{68, 0, RT_NULL, RT_NULL},
{69, 0, RT_NULL, RT_NULL},
{70, 0, RT_NULL, RT_NULL},
{71, 0, RT_NULL, RT_NULL},
{72, 0, RT_NULL, RT_NULL},
{73, 0, RT_NULL, RT_NULL},
{74, 0, RT_NULL, RT_NULL},
{75, 0, RT_NULL, RT_NULL},
{76, 0, RT_NULL, RT_NULL},
{77, 0, RT_NULL, RT_NULL},
{78, 0, RT_NULL, RT_NULL},
{79, 0, RT_NULL, RT_NULL},
{80, 0, RT_NULL, RT_NULL},
{81, 0, RT_NULL, RT_NULL},
{82, 0, RT_NULL, RT_NULL},
{83, 0, RT_NULL, RT_NULL},
{84, 0, RT_NULL, RT_NULL},
{85, 0, RT_NULL, RT_NULL},
{86, 0, RT_NULL, RT_NULL},
{87, 0, RT_NULL, RT_NULL},
{88, 0, RT_NULL, RT_NULL},
{89, 0, RT_NULL, RT_NULL},
{90, 0, RT_NULL, RT_NULL},
{91, 0, RT_NULL, RT_NULL},
{92, 0, RT_NULL, RT_NULL},
{93, 0, RT_NULL, RT_NULL},
{94, 0, RT_NULL, RT_NULL},
{95, 0, RT_NULL, RT_NULL},
{96, 0, RT_NULL, RT_NULL},
{97, 0, RT_NULL, RT_NULL},
{98, 0, RT_NULL, RT_NULL},
{99, 0, RT_NULL, RT_NULL}};
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct swm_pin_index *get_pin(uint8_t pin)
{
const struct swm_pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->gpio == GPIO0)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
}
static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct swm_pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
if (value)
{
GPIO_SetBit(index->gpio, index->pin);
}
else
{
GPIO_ClrBit(index->gpio, index->pin);
}
}
static int swm_pin_read(rt_device_t dev, rt_base_t pin)
{
const struct swm_pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return PIN_LOW;
}
return (int)GPIO_GetBit(index->gpio, index->pin);
}
static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct swm_pin_index *index;
int dir = 0;
int pull_up = 0;
int pull_down = 0;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
/* Configure GPIO_InitStructure */
switch (mode)
{
case PIN_MODE_OUTPUT:
/* output setting */
dir = 1;
break;
case PIN_MODE_INPUT:
/* input setting: not pull. */
dir = 0;
break;
case PIN_MODE_INPUT_PULLUP:
/* input setting: pull up. */
dir = 0;
pull_up = 1;
break;
case PIN_MODE_INPUT_PULLDOWN:
/* input setting: pull down. */
dir = 0;
pull_down = 1;
break;
case PIN_MODE_OUTPUT_OD:
/* output setting: od. */
dir = 1;
pull_up = 1;
break;
}
GPIO_Init(index->gpio, index->pin, dir, pull_up, pull_down);
}
static rt_err_t swm_pin_attach_irq(struct rt_device *device,
rt_int32_t pin,
rt_uint32_t mode,
void (*hdr)(void *args),
void *args)
{
const struct swm_pin_index *index;
rt_base_t level;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[pin].pin == pin &&
pin_irq_hdr_tab[pin].mode == mode &&
pin_irq_hdr_tab[pin].hdr == hdr &&
pin_irq_hdr_tab[pin].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[pin].pin = pin;
pin_irq_hdr_tab[pin].mode = mode;
pin_irq_hdr_tab[pin].hdr = hdr;
pin_irq_hdr_tab[pin].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct swm_pin_index *index;
rt_base_t level;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
pin_irq_hdr_tab[pin].mode = 0;
pin_irq_hdr_tab[pin].hdr = RT_NULL;
pin_irq_hdr_tab[pin].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t swm_pin_irq_enable(struct rt_device *device,
rt_base_t pin,
rt_uint32_t enabled)
{
const struct swm_pin_index *index;
rt_base_t level = 0;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
switch (pin_irq_hdr_tab[pin].mode)
{
case PIN_IRQ_MODE_RISING:
GPIO_Init(index->gpio, index->pin, 0, 0, 1);
EXTI_Init(index->gpio, index->pin, EXTI_RISE_EDGE);
break;
case PIN_IRQ_MODE_FALLING:
GPIO_Init(index->gpio, index->pin, 0, 1, 0);
EXTI_Init(index->gpio, index->pin, EXTI_FALL_EDGE);
break;
case PIN_IRQ_MODE_RISING_FALLING:
GPIO_Init(index->gpio, index->pin, 0, 1, 1);
EXTI_Init(index->gpio, index->pin, EXTI_BOTH_EDGE);
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
GPIO_Init(index->gpio, index->pin, 0, 0, 1);
EXTI_Init(index->gpio, index->pin, EXTI_HIGH_LEVEL);
break;
case PIN_IRQ_MODE_LOW_LEVEL:
GPIO_Init(index->gpio, index->pin, 0, 1, 0);
EXTI_Init(index->gpio, index->pin, EXTI_LOW_LEVEL);
break;
default:
return RT_EINVAL;
}
level = rt_hw_interrupt_disable();
NVIC_EnableIRQ(index->irq);
EXTI_Open(index->gpio, index->pin);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
level = rt_hw_interrupt_disable();
NVIC_DisableIRQ(index->irq);
EXTI_Close(index->gpio, index->pin);
rt_hw_interrupt_enable(level);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops swm_pin_ops =
{
.pin_mode = swm_pin_mode,
.pin_write = swm_pin_write,
.pin_read = swm_pin_read,
.pin_attach_irq = swm_pin_attach_irq,
.pin_detach_irq = swm_pin_detach_irq,
.pin_irq_enable = swm_pin_irq_enable};
static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
{
static int gpio[24];
int index = 0;
static int init = 0;
const struct swm_pin_index *pin;
if (init == 0)
{
init = 1;
for (pin = &pins[0];
pin->index < ITEM_NUM(pins);
pin++)
{
if (pin->gpio == GPIOx)
{
gpio[index] = pin->index;
index++;
RT_ASSERT(index <= 24)
}
}
}
for (index = 0; index < 24; index++)
{
pin = get_pin(gpio[index]);
if (EXTI_State(pin->gpio, pin->pin))
{
EXTI_Clear(pin->gpio, pin->pin);
if (pin_irq_hdr_tab[pin->index].hdr)
{
pin_irq_hdr_tab[pin->index].hdr(pin_irq_hdr_tab[pin->index].args);
}
}
}
}
void GPIOA_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOA);
rt_interrupt_leave();
}
void GPIOB_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOB);
rt_interrupt_leave();
}
void GPIOC_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOC);
rt_interrupt_leave();
}
void GPIOM_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOM);
rt_interrupt_leave();
}
void GPION_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPION);
rt_interrupt_leave();
}
void GPIOP_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOP);
rt_interrupt_leave();
}
int rt_hw_pin_init(void)
{
return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /* BSP_USING_GPIO */
#endif /* RT_USING_PIN */
bsp/swm320/drivers/drv_gpio.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include "board.h"
#define __SWM_PIN(index, gpio, pin_index) \
{ \
index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
}
#define GPIO0 ((GPIO_TypeDef *)(0))
#define GPIO0_IRQn (GPIOA0_IRQn)
struct swm_pin_index
{
uint32_t index;
GPIO_TypeDef *gpio;
uint32_t pin;
IRQn_Type irq;
};
typedef struct swm_pin_index pin_t;
int rt_hw_pin_init(void);
#endif /* __DRV_GPIO_H__ */
bsp/swm320/drivers/drv_hwtimer.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik format file
*/
#include "drv_hwtimer.h"
#ifdef RT_USING_HWTIMER
#ifdef BSP_USING_TIM
enum
{
#ifdef BSP_USING_TIM0
TIM0_INDEX,
#endif
#ifdef BSP_USING_TIM1
TIM1_INDEX,
#endif
#ifdef BSP_USING_TIM2
TIM2_INDEX,
#endif
#ifdef BSP_USING_TIM3
TIM3_INDEX,
#endif
#ifdef BSP_USING_TIM4
TIM4_INDEX,
#endif
#ifdef BSP_USING_TIM5
TIM5_INDEX,
#endif
};
static struct swm_hwtimer_cfg hwtimer_cfg[] =
{
#ifdef BSP_USING_TIM0
TIM0_CFG,
#endif
#ifdef BSP_USING_TIM1
TIM1_CFG,
#endif
#ifdef BSP_USING_TIM2
TIM2_CFG,
#endif
#ifdef BSP_USING_TIM3
TIM3_CFG,
#endif
#ifdef BSP_USING_TIM4
TIM4_CFG,
#endif
#ifdef BSP_USING_TIM5
TIM5_CFG,
#endif
};
static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0};
static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
if (state)
{
cfg = timer_device->parent.user_data;
TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1);
timer_device->freq = SystemCoreClock;
}
}
static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode)
{
rt_err_t result = RT_EOK;
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
if (opmode == HWTIMER_MODE_ONESHOT)
{
/* set timer to single mode */
timer_device->mode = HWTIMER_MODE_ONESHOT;
}
else
{
timer_device->mode = HWTIMER_MODE_PERIOD;
}
TIMR_SetPeriod(cfg->TIMRx, cnt);
TIMR_Stop(cfg->TIMRx);
TIMR_Start(cfg->TIMRx);
return result;
}
static void swm_timer_stop(rt_hwtimer_t *timer_device)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
/* stop timer */
TIMR_Stop(cfg->TIMRx);
}
static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
return TIMR_GetCurValue(cfg->TIMRx);
}
static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
rt_err_t result = RT_EOK;
RT_ASSERT(timer_device != RT_NULL);
RT_ASSERT(args != RT_NULL);
cfg = timer_device->parent.user_data;
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
freq = *(rt_uint32_t *)args;
TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1);
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
static struct rt_hwtimer_ops swm_hwtimer_ops =
{
.init = swm_timer_init,
.start = swm_timer_start,
.stop = swm_timer_stop,
.count_get = swm_timer_count_get,
.control = swm_timer_ctrl};
void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
TIMR_INTClr(cfg->TIMRx);
rt_device_hwtimer_isr(timer_device);
}
#ifdef BSP_USING_TIM0
void TIMR0_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM0
#ifdef BSP_USING_TIM1
void TIMR1_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM1
#ifdef BSP_USING_TIM2
void TIMR2_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM2
#ifdef BSP_USING_TIM3
void TIMR3_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM3
#ifdef BSP_USING_TIM4
void TIMR4_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM4
#ifdef BSP_USING_TIM5
void TIMR5_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM5
static int rt_hw_hwtimer_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++)
{
hwtimer_drv[i].cfg = &hwtimer_cfg[i];
hwtimer_drv[i].time_device.info = &_info;
hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops;
if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK)
{
;
}
else
{
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
#endif /* BSP_USING_TIM */
#endif /* RT_USING_HWTIMER */
bsp/swm320/drivers/drv_hwtimer.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_HWTIMER_H__
#define __DRV_HWTIMER_H__
#include "board.h"
struct swm_hwtimer_cfg
{
char *name;
TIMR_TypeDef *TIMRx;
};
struct swm_hwtimer
{
struct swm_hwtimer_cfg *cfg;
rt_hwtimer_t time_device;
};
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 120000000, \
.minfreq = 120000000, \
.maxcnt = 0xFFFFFFFF, \
.cntmode = HWTIMER_CNTMODE_DW, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM0
#ifndef TIM0_CFG
#define TIM0_CFG \
{ \
.name = "timer0", \
.TIMRx = TIMR0, \
}
#endif /* TIM0_CFG */
#endif /* BSP_USING_TIM0 */
#ifdef BSP_USING_TIM1
#ifndef TIM1_CFG
#define TIM1_CFG \
{ \
.name = "timer1", \
.TIMRx = TIMR1, \
}
#endif /* TIM1_CFG */
#endif /* BSP_USING_TIM1 */
#ifdef BSP_USING_TIM2
#ifndef TIM2_CFG
#define TIM2_CFG \
{ \
.name = "timer2", \
.TIMRx = TIMR2, \
}
#endif /* TIM2_CFG */
#endif /* BSP_USING_TIM2 */
#ifdef BSP_USING_TIM3
#ifndef TIM3_CFG
#define TIM3_CFG \
{ \
.name = "timer3", \
.TIMRx = TIMR3, \
}
#endif /* TIM3_CFG */
#endif /* BSP_USING_TIM3 */
#ifdef BSP_USING_TIM4
#ifndef TIM4_CFG
#define TIM4_CFG \
{ \
.name = "timer4", \
.TIMRx = TIMR4, \
}
#endif /* TIM4_CFG */
#endif /* BSP_USING_TIM4 */
#ifdef BSP_USING_TIM5
#ifndef TIM5_CFG
#define TIM5_CFG \
{ \
.name = "timer5", \
.TIMRx = TIMR5, \
}
#endif /* TIM5_CFG */
#endif /* BSP_USING_TIM5 */
int rt_hw_hwtimer_init(void);
#endif /* __DRV_HWTIMER_H__ */
bsp/swm320/drivers/drv_log.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
bsp/swm320/drivers/drv_nor_flash.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee format file
* 2020-07-10 lik rewrite
*/
#include "drv_nor_flash.h"
#ifdef BSP_USING_NOR_FLASH
#define DRV_DEBUG
#define LOG_TAG "drv.norflash"
#include <drv_log.h>
static struct rt_mutex flash_lock;
/* RT-Thread MTD device interface */
static long swm_norflash_read_id(struct rt_mtd_nor_device *device)
{
return 0xdeadbeef;
}
static rt_size_t swm_norflash_read(struct rt_mtd_nor_device *device,
rt_off_t position,
rt_uint8_t *data,
rt_uint32_t size)
{
rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
memcpy(data, ((const void *)(NORFLM_BASE + position)), size);
rt_mutex_release(&flash_lock);
return size;
}
static rt_size_t swm_norflash_write(struct rt_mtd_nor_device *device,
rt_off_t position,
const rt_uint8_t *data,
rt_uint32_t size)
{
rt_size_t i;
const rt_uint16_t *hwdata = (const rt_uint16_t *)data;
rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
for (i = 0; i < size / 2; i++)
{
NORFL_Write(position, hwdata[i]);
position += 2;
}
rt_mutex_release(&flash_lock);
return size;
}
static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device,
rt_off_t offset,
rt_uint32_t length)
{
rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
NORFL_SectorErase(offset);
rt_mutex_release(&flash_lock);
return RT_EOK;
}
const static struct rt_mtd_nor_driver_ops mtd_ops =
{
swm_norflash_read_id,
swm_norflash_read,
swm_norflash_write,
swm_norflash_erase_block};
static struct rt_mtd_nor_device mtd;
int rt_hw_norflash_init(void)
{
NORFL_InitStructure NORFL_InitStruct;
PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23
PORT->PORTP_SEL1 = 0xAAAA;
PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0
PORT->PORTM_INEN = 0xFFFF;
PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE
NORFL_InitStruct.DataWidth = 16;
NORFL_InitStruct.WELowPulseTime = 5;
NORFL_InitStruct.OEPreValidTime = 12;
NORFL_InitStruct.OperFinishIEn = 0;
NORFL_InitStruct.OperTimeoutIEn = 0;
NORFL_Init(&NORFL_InitStruct);
/* set page size and block size */
mtd.block_size = BLOCK_SIZE; /* 64kByte */
mtd.ops = &mtd_ops;
/* initialize mutex */
if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_FIFO) != RT_EOK)
{
rt_kprintf("init sd lock mutex failed\n");
return -RT_ERROR;
}
mtd.block_start = 0;
mtd.block_end = BLOCK_COUNTER;
/* register MTD device */
rt_mtd_nor_register_device("nor", &mtd);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_norflash_init);
#endif /* BSP_USING_NOR_FLASH */
bsp/swm320/drivers/drv_nor_flash.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef DRV_NOR_FLASH_H__
#define DRV_NOR_FLASH_H__
#include "board.h"
#define BLOCK_SIZE (64 * 1024)
#define FLASH_SIZE (BSP_NOR_FLASH_SIZE)
#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE)
int rt_hw_norflash_init(void);
#endif
bsp/swm320/drivers/drv_pwm.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik format file
*/
#include "drv_pwm.h"
#ifdef RT_USING_PWM
#ifdef BSP_USING_PWM
//#define DRV_DEBUG
#define LOG_TAG "drv.pwm"
#include <drv_log.h>
#define MIN_PERIOD 2
#define MIN_PULSE 1
static struct swm_pwm_cfg pwm_cfg[] =
{
#ifdef BSP_USING_PWM0
PWM0_CFG,
#endif
#ifdef BSP_USING_PWM1
PWM1_CFG,
#endif
#ifdef BSP_USING_PWM2
PWM2_CFG,
#endif
#ifdef BSP_USING_PWM3
PWM3_CFG,
#endif
#ifdef BSP_USING_PWM4
PWM4_CFG,
#endif
#ifdef BSP_USING_PWM5
PWM5_CFG,
#endif
};
static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0};
static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg);
static struct rt_pwm_ops pwm_ops =
{
swm_pwm_control};
static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
struct swm_pwm_cfg *cfg = RT_NULL;
RT_ASSERT(pwm_device != RT_NULL);
cfg = pwm_device->parent.user_data;
if (!enable)
{
if (PWM_CH_A == configuration->channel)
{
PWM_Stop(cfg->PWMx, 1, 0);
}
if (PWM_CH_B == configuration->channel)
{
PWM_Stop(cfg->PWMx, 0, 1);
}
}
else
{
if (PWM_CH_A == configuration->channel)
{
PWM_Start(cfg->PWMx, 1, 0);
}
if (PWM_CH_B == configuration->channel)
{
PWM_Start(cfg->PWMx, 0, 1);
}
}
return RT_EOK;
}
static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
{
rt_uint64_t tim_clock;
tim_clock = SystemCoreClock / 8;
struct swm_pwm_cfg *cfg = RT_NULL;
RT_ASSERT(pwm_device != RT_NULL);
cfg = pwm_device->parent.user_data;
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
tim_clock /= 1000000UL;
configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
return RT_EOK;
}
static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period, pulse;
rt_uint64_t tim_clock;
tim_clock = SystemCoreClock / 8;
struct swm_pwm_cfg *cfg = RT_NULL;
RT_ASSERT(pwm_device != RT_NULL);
cfg = pwm_device->parent.user_data;
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
/* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */
/* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */
tim_clock /= 1000000UL;
period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL;
if (period < MIN_PERIOD)
{
period = MIN_PERIOD;
}
if (pulse < MIN_PULSE)
{
pulse = MIN_PULSE;
}
PWM_SetCycle(cfg->PWMx, configuration->channel, period);
PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse);
return RT_EOK;
}
static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg)
{
RT_ASSERT(pwm_device != RT_NULL);
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
switch (cmd)
{
case PWM_CMD_ENABLE:
return swm_pwm_enable(pwm_device, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return swm_pwm_enable(pwm_device, configuration, RT_FALSE);
case PWM_CMD_SET:
return swm_pwm_set(pwm_device, configuration);
case PWM_CMD_GET:
return swm_pwm_get(pwm_device, configuration);
default:
return RT_EINVAL;
}
}
int rt_hw_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++)
{
pwm_drv[i].cfg = &pwm_cfg[i];
if (pwm_drv[i].cfg->PWMx == PWM0)
{
#ifdef BSP_USING_PWM0A
PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0);
#endif
#ifdef BSP_USING_PWM0B
PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM1)
{
#ifdef BSP_USING_PWM1A
PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0);
#endif
#ifdef BSP_USING_PWM1B
PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM2)
{
#ifdef BSP_USING_PWM2A
PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0);
#endif
#ifdef BSP_USING_PWM2B
PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM3)
{
#ifdef BSP_USING_PWM3A
PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0);
#endif
#ifdef BSP_USING_PWM3B
PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM4)
{
#ifdef BSP_USING_PWM4A
PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0);
#endif
#ifdef BSP_USING_PWM4B
PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM5)
{
#ifdef BSP_USING_PWM5A
PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0);
#endif
#ifdef BSP_USING_PWM5B
PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0);
#endif
}
PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct));
if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK)
{
LOG_D("%s register success", pwm_drv[i].cfg->name);
}
else
{
LOG_E("%s register failed", pwm_drv[i].cfg->name);
result = -RT_ERROR;
}
}
return result;
}
INIT_DEVICE_EXPORT(rt_hw_pwm_init);
#endif /* BSP_USING_PWM */
#endif /* RT_USING_PWM */
bsp/swm320/drivers/drv_pwm.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include "board.h"
struct swm_pwm_cfg
{
const char *name;
PWM_TypeDef *PWMx;
PWM_InitStructure pwm_initstruct;
};
struct swm_pwm
{
struct swm_pwm_cfg *cfg;
struct rt_device_pwm pwm_device;
};
#ifdef BSP_USING_PWM0
#ifndef PWM0_CFG
#define PWM0_CFG \
{ \
.name = "pwm0", \
.PWMx = PWM0, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM0_CFG */
#endif /* BSP_USING_PWM0 */
#ifdef BSP_USING_PWM1
#ifndef PWM1_CFG
#define PWM1_CFG \
{ \
.name = "pwm1", \
.PWMx = PWM1, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM1_CFG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CFG
#define PWM2_CFG \
{ \
.name = "pwm2", \
.PWMx = PWM2, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM2_CFG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CFG
#define PWM3_CFG \
{ \
.name = "pwm3", \
.PWMx = PWM3, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM3_CFG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CFG
#define PWM4_CFG \
{ \
.name = "pwm4", \
.PWMx = PWM4, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM4_CFG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CFG
#define PWM5_CFG \
{ \
.name = "pwm5", \
.PWMx = PWM5, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM5_CFG */
#endif /* BSP_USING_PWM5 */
int rt_hw_pwm_init(void);
#endif /* __DRV_PWM_H__ */
bsp/swm320/drivers/drv_rtc.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik format file
*/
#include "drv_rtc.h"
#ifdef RT_USING_RTC
#ifdef BSP_USING_RTC
//#define DRV_DEBUG
#define LOG_TAG "drv.rtc"
#include <drv_log.h>
static struct rt_device rtc_device;
static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date)
{
uint32_t i, cnt = 0;
const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
for (i = 1; i < month; i++)
cnt += daysOfMonth[i];
cnt += date;
if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3))
cnt += 1;
cnt += (year - 1901) * 365;
for (i = 1901; i < year; i++)
{
if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0)))
cnt += 1;
}
return (cnt + 1) % 7;
}
static time_t swm_get_rtc_time_stamp(void)
{
RTC_DateTime get_datetime = {0};
struct tm tm_new;
RTC_GetDateTime(RTC, &get_datetime);
tm_new.tm_sec = get_datetime.Second;
tm_new.tm_min = get_datetime.Minute;
tm_new.tm_hour = get_datetime.Hour;
tm_new.tm_mday = get_datetime.Date;
tm_new.tm_mon = get_datetime.Month - 1;
tm_new.tm_year = get_datetime.Year - 1900;
LOG_D("get rtc time.");
return mktime(&tm_new);
}
static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
{
RTC_DateTime set_datetime = {0};
struct tm *p_tm;
p_tm = gmtime(&time_stamp);
set_datetime.Second = p_tm->tm_sec;
set_datetime.Minute = p_tm->tm_min;
set_datetime.Hour = p_tm->tm_hour;
set_datetime.Date = p_tm->tm_mday;
set_datetime.Month = p_tm->tm_mon + 1;
set_datetime.Year = p_tm->tm_year + 1900;
// datetime.Day = p_tm->tm_wday;
RTC_Stop(RTC);
while (RTC->CFGABLE == 0)
;
RTC->MINSEC = (set_datetime.Second << RTC_MINSEC_SEC_Pos) |
(set_datetime.Minute << RTC_MINSEC_MIN_Pos);
RTC->DATHUR = (set_datetime.Hour << RTC_DATHUR_HOUR_Pos) |
((set_datetime.Date) << RTC_DATHUR_DATE_Pos);
RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date)
<< RTC_MONDAY_DAY_Pos) |
((set_datetime.Month) << RTC_MONDAY_MON_Pos);
RTC->YEAR = set_datetime.Year - 1901;
RTC->LOAD = 1 << RTC_LOAD_TIME_Pos;
RTC_Start(RTC);
LOG_D("set rtc time.");
return RT_EOK;
}
static rt_err_t swm_rtc_control(rt_device_t rtc_device, int cmd, void *args)
{
rt_err_t result = RT_EOK;
RT_ASSERT(rtc_device != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = swm_get_rtc_time_stamp();
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
break;
default:
break;
}
return result;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops swm_rtc_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
swm_rtc_control};
#endif
static void swm_rtc_init(void)
{
RTC_InitStructure rtc_initstruct;
rtc_initstruct.Year = 2020;
rtc_initstruct.Month = 6;
rtc_initstruct.Date = 8;
rtc_initstruct.Hour = 12;
rtc_initstruct.Minute = 0;
rtc_initstruct.Second = 0;
rtc_initstruct.SecondIEn = 0;
rtc_initstruct.MinuteIEn = 0;
RTC_Init(RTC, &rtc_initstruct);
RTC_Start(RTC);
}
static rt_err_t rt_hw_rtc_register(rt_device_t rtc_device, const char *name, rt_uint32_t flag)
{
RT_ASSERT(rtc_device != RT_NULL);
swm_rtc_init();
#ifdef RT_USING_DEVICE_OPS
rtc_device->ops = &swm_rtc_ops;
#else
rtc_device->init = RT_NULL;
rtc_device->open = RT_NULL;
rtc_device->close = RT_NULL;
rtc_device->read = RT_NULL;
rtc_device->write = RT_NULL;
rtc_device->control = swm_rtc_control;
#endif
rtc_device->type = RT_Device_Class_RTC;
rtc_device->rx_indicate = RT_NULL;
rtc_device->tx_complete = RT_NULL;
rtc_device->user_data = RT_NULL;
/* register a character device */
return rt_device_register(rtc_device, name, flag);
}
int rt_hw_rtc_init(void)
{
rt_err_t result;
result = rt_hw_rtc_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
if (result != RT_EOK)
{
LOG_E("rtc register err code: %d", result);
return result;
}
LOG_D("rtc init success");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif /* BSP_USING_RTC */
#endif /* RT_USING_RTC */
bsp/swm320/drivers/drv_rtc.h 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_RTC_H__
#define __DRV_RTC_H__
#include "board.h"
int rt_hw_rtc_init(void);
#endif /* __DRV_RTC_H__ */
bsp/swm320/drivers/drv_sdio.c 0 → 100644
浏览文件 @ 0c2aef2c
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-10 lik first version
*/
#include "drv_sdio.h"
#ifdef RT_USING_SDIO
#ifdef BSP_USING_SDIO
//#define DRV_DEBUG
#define LOG_TAG "drv.sdio"
#include <drv_log.h>
static struct rt_mmcsd_host *host;
#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
struct rthw_sdio
{
struct rt_mmcsd_host *host;
struct swm_sdio_des sdio_des;
struct rt_event event;
struct rt_mutex mutex;
struct sdio_pkg *pkg;
};
ALIGN(SDIO_ALIGN_LEN)
static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
/**
* @brief This function wait sdio completed.
* @param sdio rthw_sdio
* @retval None
*/
static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
{
rt_uint32_t status;
struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
{
LOG_E("wait completed timeout");
cmd->err = -RT_ETIMEOUT;
return;
}
if (sdio->pkg == RT_NULL)
{
return;
}
if (resp_type(cmd) == RESP_NONE)
{
;
}
else if (resp_type(cmd) == RESP_R2)
{
cmd->resp[0] = (hw_sdio->RESP[3] << 8) + ((hw_sdio->RESP[2] >> 24) & 0xFF);
cmd->resp[1] = (hw_sdio->RESP[2] << 8) + ((hw_sdio->RESP[1] >> 24) & 0xFF);
cmd->resp[2] = (hw_sdio->RESP[1] << 8) + ((hw_sdio->RESP[0] >> 24) & 0xFF);
cmd->resp[3] = (hw_sdio->RESP[0] << 8) + 0x00;
}
else
{
cmd->resp[0] = hw_sdio->RESP[0];
}
if (status & SDIO_IF_ERROR_Msk)
{
if ((status & SDIO_IF_CMDCRCERR_Msk) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
{
cmd->err = RT_EOK;
}
else
{
cmd->err = -RT_ERROR;
}
if (status & SDIO_IF_CMDTIMEOUT_Msk)
{
cmd->err = -RT_ETIMEOUT;
}
if (status & SDIO_IF_DATCRCERR_Msk)
{
data->err = -RT_ERROR;
}
if (status & SDIO_IF_DATTIMEOUT_Msk)
{
data->err = -RT_ETIMEOUT;
}
if (cmd->err == RT_EOK)
{
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
else
{
LOG_D("err:0x%08x, %s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
status,
status == 0 ? "NULL" : "",
cmd->cmd_code,
cmd->arg,
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0);
}
}
else
{
cmd->err = RT_EOK;
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
}
/**
* @brief This function transfer data by dma.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_data *data;
int size;
void *buff;
if ((RT_NULL == pkg) || (RT_NULL == sdio))
{
LOG_E("rthw_sdio_transfer invalid args");
return;
}
data = pkg->cmd->data;
if (RT_NULL == data)
{
LOG_E("rthw_sdio_transfer invalid args");
return;
}
buff = pkg->buff;
if (RT_NULL == buff)
{
LOG_E("rthw_sdio_transfer invalid args");
return;
}
size = data->blks * data->blksize;
if (data->flags & DATA_DIR_WRITE)
{
sdio->sdio_des.txconfig(pkg, (rt_uint32_t *)buff, size);
}
else if (data->flags & DATA_DIR_READ)
{
sdio->sdio_des.rxconfig(pkg, (rt_uint32_t *)buff, size);
}
}
/**
* @brief This function send command.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t reg_cmd;
/* save pkg */
sdio->pkg = pkg;
LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
cmd->cmd_code,
cmd->arg,
resp_type(cmd) == RESP_NONE ? "NONE" : "",
resp_type(cmd) == RESP_R1 ? "R1" : "",
resp_type(cmd) == RESP_R1B ? "R1B" : "",
resp_type(cmd) == RESP_R2 ? "R2" : "",
resp_type(cmd) == RESP_R3 ? "R3" : "",
resp_type(cmd) == RESP_R4 ? "R4" : "",
resp_type(cmd) == RESP_R5 ? "R5" : "",
resp_type(cmd) == RESP_R6 ? "R6" : "",
resp_type(cmd) == RESP_R7 ? "R7" : "",
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0);
/* config cmd reg */
reg_cmd = (cmd->cmd_code << SDIO_CMD_CMDINDX_Pos) |
(0 << SDIO_CMD_CMDTYPE_Pos) |
(0 << SDIO_CMD_IDXCHECK_Pos) |
(0 << SDIO_CMD_CRCCHECK_Pos) |
(0 << SDIO_CMD_DMAEN_Pos);
if (resp_type(cmd) == RESP_NONE)
reg_cmd |= SD_RESP_NO << SDIO_CMD_RESPTYPE_Pos;
else if (resp_type(cmd) == RESP_R2)
reg_cmd |= SD_RESP_128b << SDIO_CMD_RESPTYPE_Pos;
else
reg_cmd |= SD_RESP_32b << SDIO_CMD_RESPTYPE_Pos;
/* config data reg */
if (data != RT_NULL)
{
rt_uint32_t dir = 0;
dir = (data->flags & DATA_DIR_READ) ? 1 : 0;
hw_sdio->BLK = (data->blks << SDIO_BLK_COUNT_Pos) | (data->blksize << SDIO_BLK_SIZE_Pos);
reg_cmd |= (1 << SDIO_CMD_HAVEDATA_Pos) |
(dir << SDIO_CMD_DIRREAD_Pos) |
((data->blks > 1) << SDIO_CMD_MULTBLK_Pos) |
((data->blks > 1) << SDIO_CMD_BLKCNTEN_Pos) |
(0 << SDIO_CMD_AUTOCMD12_Pos);
}
else
{
reg_cmd |= (0 << SDIO_CMD_HAVEDATA_Pos);
}
if (cmd->cmd_code != SD_IO_SEND_OP_COND)
{
/* send cmd */
hw_sdio->ARG = cmd->arg;
hw_sdio->CMD = reg_cmd;
}
/* transfer config */
if (data != RT_NULL)
{
rthw_sdio_transfer(sdio, pkg);
}
/* wait completed */
rthw_sdio_wait_completed(sdio);
/* clear pkg */
sdio->pkg = RT_NULL;
}
/**
* @brief This function send sdio request.
* @param sdio rthw_sdio
* @param req request
* @retval None
*/
static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
struct sdio_pkg pkg;
struct rthw_sdio *sdio = host->private_data;
struct rt_mmcsd_data *data;
RTHW_SDIO_LOCK(sdio);
if (req->cmd != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
data = req->cmd->data;
pkg.cmd = req->cmd;
if (data != RT_NULL)
{
rt_uint32_t size = data->blks * data->blksize;
RT_ASSERT(size <= SDIO_BUFF_SIZE);
pkg.buff = data->buf;
if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
{
pkg.buff = cache_buf;
if (data->flags & DATA_DIR_WRITE)
{
rt_memcpy(cache_buf, data->buf, size);
}
}
}
rthw_sdio_send_command(sdio, &pkg);
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
{
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
}
}
if (req->stop != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
pkg.cmd = req->stop;
rthw_sdio_send_command(sdio, &pkg);
}
RTHW_SDIO_UNLOCK(sdio);
mmcsd_req_complete(sdio->host);
}
/**
* @brief This function config sdio.
* @param host rt_mmcsd_host
* @param io_cfg rt_mmcsd_io_cfg
* @retval None
*/
static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
rt_uint32_t clkcr, div, clk_src;
rt_uint32_t clk = io_cfg->clock;
struct rthw_sdio *sdio = host->private_data;
SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
if (clk_src < 400 * 1000)
{
LOG_E("The clock rate is too low! rata:%d", clk_src);
return;
}
if (clk > host->freq_max)
clk = host->freq_max;
if (clk > clk_src)
{
LOG_W("Setting rate is greater than clock source rate.");
clk = clk_src;
}
LOG_D("clk:%d width:%s%s%s power:%s%s%s",
clk,
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "");
RTHW_SDIO_LOCK(sdio);
hw_sdio->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | (7 << SDIO_CR1_VOLT_Pos);
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
{
hw_sdio->CR1 |= (1 << SDIO_CR1_8BIT_Pos);
}
else
{
hw_sdio->CR1 &= ~SDIO_CR1_8BIT_Msk;
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
{
hw_sdio->CR1 |= (1 << SDIO_CR1_4BIT_Pos);
}
else
{
hw_sdio->CR1 &= ~SDIO_CR1_4BIT_Msk;
}
}
switch (io_cfg->power_mode)
{
case MMCSD_POWER_OFF:
hw_sdio->CR1 &= ~SDIO_CR1_PWRON_Msk;
break;
case MMCSD_POWER_UP:
case MMCSD_POWER_ON:
hw_sdio->CR1 |= (1 << SDIO_CR1_PWRON_Pos);
break;
default:
LOG_W("unknown power_mode %d", io_cfg->power_mode);
break;
}
div = clk_src / clk;
if ((clk == 0) || (div == 0))
{
clkcr = 0;
}
else
{
if (div > 128)
clkcr = 0x80;
else if (div > 64)
clkcr = 0x40;
else if (div > 32)
clkcr = 0x20;
else if (div > 16)
clkcr = 0x10;
else if (div > 8)
clkcr = 0x08;
else if (div > 4)
clkcr = 0x04;
else if (div > 2)
clkcr = 0x02;
else if (div > 1)
clkcr = 0x01;
else
clkcr = 0x00;
}
SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) |
(1 << SDIO_CR2_SDCLKEN_Pos) |
(clkcr << SDIO_CR2_SDCLKDIV_Pos) |
(0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK
while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0)
;
RTHW_SDIO_UNLOCK(sdio);
}
/**
* @brief This function delect sdcard.
* @param host rt_mmcsd_host
* @retval 0x01
*/
static rt_int32_t rthw_sdio_delect(struct rt_mmcsd_host *host)
{
LOG_D("try to detect device");
return 0x01;
}
/**
* @brief This function update sdio interrupt.
* @param host rt_mmcsd_host
* @param enable
* @retval None
*/
void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
{
struct rthw_sdio *sdio = host->private_data;
SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
if (enable)
{
LOG_D("enable sdio irq");
hw_sdio->IFE = 0xFFFFFFFF;
hw_sdio->IE = 0xFFFF000F;
}
else
{
LOG_D("disable sdio irq");
hw_sdio->IFE &= ~0xFFFFFFFF;
hw_sdio->IE &= ~0xFFFFFFFF;
}
}
static const struct rt_mmcsd_host_ops swm_sdio_ops =
{
rthw_sdio_request,
rthw_sdio_iocfg,
rthw_sdio_delect,
rthw_sdio_irq_update,
};
struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des)
{
struct rt_mmcsd_host *host;
struct rthw_sdio *sdio = RT_NULL;
if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
{
LOG_E("L:%d F:%s %s %s %s",
(sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
(sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
(sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : ""));
return RT_NULL;
}
sdio = rt_malloc(sizeof(struct rthw_sdio));
if (sdio == RT_NULL)
{
LOG_E("L:%d F:%s malloc rthw_sdio fail");
return RT_NULL;
}
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
host = mmcsd_alloc_host();
if (host == RT_NULL)
{
LOG_E("L:%d F:%s mmcsd alloc host fail");
rt_free(sdio);
return RT_NULL;
}
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct swm_sdio_des));
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
/* set host defautl attributes */
host->ops = &swm_sdio_ops;
host->freq_min = 400 * 1000;
host->freq_max = SDIO_MAX_FREQ;
host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */
#ifndef SDIO_USING_1_BIT
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#else
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#endif
host->max_seg_size = SDIO_BUFF_SIZE;
host->max_dma_segs = 1;
host->max_blk_size = 512;
host->max_blk_count = 512;
/* link up host and sdio */
sdio->host = host;
host->private_data = sdio;
rthw_sdio_irq_update(host, 1);
/* ready to change */
mmcsd_change(host);
return host;
}
static rt_uint32_t swm_sdio_clock_get(SDIO_TypeDef *hw_sdio)
{
uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos);
return (SystemCoreClock / (1 << prediv));
}
static rt_err_t swm_sdio_rxconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
for (uint32_t i = 0; i < data->blks; i++)
{
while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_BUFRDRDY_Msk;
for (uint32_t j = 0; j < data->blksize / 4; j++)
buff[j] = SDIO->DATA;
}
return RT_EOK;
}
static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
for (uint32_t i = 0; i < data->blks; i++)
{
while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_BUFWRRDY_Msk;
for (uint32_t j = 0; j < data->blksize / 4; j++)
SDIO->DATA = buff[j];
}
return RT_EOK;
}
/**
* @brief This function interrupt process function.
* @param host rt_mmcsd_host
* @retval None
*/
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
{
int complete = 0;
struct rthw_sdio *sdio = host->private_data;
SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t intstatus = hw_sdio->IF;
if (intstatus & SDIO_IF_ERROR_Msk)
{
hw_sdio->IF = 0xFFFFFFFF;
complete = 1;
}
else
{
if (intstatus & SDIO_IF_CMDDONE_Msk)
{
hw_sdio->IF = SDIO_IF_CMDDONE_Msk;
if (sdio->pkg != RT_NULL)
{
if (!sdio->pkg->cmd->data)
{
complete = 1;
}
}
}
if (intstatus & SDIO_IF_TRXDONE_Msk)
{
hw_sdio->IF = SDIO_IF_TRXDONE_Msk;
complete = 1;
}
}
if (complete)
{
rt_event_send(&sdio->event, intstatus);
}
}
void SDIO_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* Process All SDIO Interrupt Sources */
rthw_sdio_irq_process(host);
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_sdio_init(void)
{
struct swm_sdio_des sdio_des;
#if 1
PORT_Init(PORTB, PIN1, PORTB_PIN1_SD_CLK, 0);
PORT_Init(PORTB, PIN2, PORTB_PIN2_SD_CMD, 1);
PORT_Init(PORTB, PIN3, PORTB_PIN3_SD_D0, 1);
PORT_Init(PORTB, PIN4, PORTB_PIN4_SD_D1, 1);
PORT_Init(PORTB, PIN5, PORTB_PIN5_SD_D2, 1);
PORT_Init(PORTB, PIN6, PORTB_PIN6_SD_D3, 1);
#else
PORT_Init(PORTP, PIN11, PORTP_PIN11_SD_CLK, 0);
PORT_Init(PORTP, PIN10, PORTP_PIN10_SD_CMD, 1);
PORT_Init(PORTP, PIN9, PORTP_PIN9_SD_D0, 1);
PORT_Init(PORTP, PIN8, PORTP_PIN8_SD_D1, 1);
PORT_Init(PORTP, PIN7, PORTP_PIN7_SD_D2, 1);
PORT_Init(PORTP, PIN6, PORTP_PIN6_SD_D3, 1);
#endif
NVIC_EnableIRQ(SDIO_IRQn);
SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk;
if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz
SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4
else
SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2
SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos);
SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos);
NVIC_EnableIRQ(SDIO_IRQn);
sdio_des.clk_get = swm_sdio_clock_get;
sdio_des.hw_sdio = SDIO;
sdio_des.rxconfig = swm_sdio_rxconfig;
sdio_des.txconfig = swm_sdio_txconfig;
host = sdio_host_create(&sdio_des);
if (host == RT_NULL)
{
LOG_E("host create fail");
return -1;
}
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
#endif /* BSP_USING_SDIO */
#endif /* RT_USING_SDIO */
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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-10 lik first version
*/
#ifndef __DRV_SDIO_H__
#define __DRV_SDIO_H__
#include "board.h"
#define SDIO_BUFF_SIZE 4096
#define SDIO_ALIGN_LEN 4
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (30000000)
#endif
struct sdio_pkg
{
struct rt_mmcsd_cmd *cmd;
void *buff;
rt_uint32_t flag;
};
typedef rt_err_t (*sdio_txconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size);
typedef rt_err_t (*sdio_rxconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size);
typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *hw_sdio);
struct swm_sdio_des
{
SDIO_TypeDef *hw_sdio;
sdio_txconfig txconfig;
sdio_rxconfig rxconfig;
sdio_clk_get clk_get;
};
#endif /* __DRV_SDIO_H__ */
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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_SOFT_I2C_H__
#define __DRV_SOFT_I2C_H__
#include "board.h"
/* swm config class */
struct swm_soft_i2c_cfg
{
rt_uint8_t scl;
rt_uint8_t sda;
const char *name;
};
/* swm i2c dirver class */
struct swm_i2c
{
struct rt_i2c_bit_ops ops;
struct rt_i2c_bus_device i2c2_bus;
};
#ifdef BSP_USING_I2C0
#define I2C0_BUS_CFG \
{ \
.scl = BSP_I2C0_SCL_PIN, \
.sda = BSP_I2C0_SDA_PIN, \
.name = "i2c0", \
}
#endif
#ifdef BSP_USING_I2C1
#define I2C1_BUS_CFG \
{ \
.scl = BSP_I2C1_SCL_PIN, \
.sda = BSP_I2C1_SDA_PIN, \
.name = "i2c1", \
}
#endif
int rt_hw_i2c_init(void);
#endif /* __DRV_SOFT_I2C_H__ */
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00080000 { ; load region size_region
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}
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