Now construction of PA/VA only uses 56/39 bits.

os/src/config.rs

@@ -18,4 +18,4 @@ pub const TRAP_CONTEXT: usize = TRAMPOLINE - PAGE_SIZE;
 pub const CLOCK_FREQ: usize = 403000000 / 62;
 
 #[cfg(feature = "board_qemu")]
-pub const CLOCK_FREQ: usize = 12500000;
\ No newline at end of file
+pub const CLOCK_FREQ: usize = 12500000;

os/src/mm/address.rs

@@ -2,6 +2,11 @@ use crate::config::{PAGE_SIZE, PAGE_SIZE_BITS};
 use super::PageTableEntry;
 use core::fmt::{self, Debug, Formatter};
 
+const PA_WIDTH_SV39: usize = 56;
+const VA_WIDTH_SV39: usize = 39;
+const PPN_WIDTH_SV39: usize = PA_WIDTH_SV39 - PAGE_SIZE_BITS;
+const VPN_WIDTH_SV39: usize = VA_WIDTH_SV39 - PAGE_SIZE_BITS;
+
 /// Definitions
 #[derive(Copy, Clone, Ord, PartialOrd, Eq, PartialEq)]
 pub struct PhysAddr(pub usize);
@@ -43,16 +48,16 @@ impl Debug for PhysPageNum {
 /// usize -> T: usize.into()
 
 impl From<usize> for PhysAddr {
-    fn from(v: usize) -> Self { Self(v) }
+    fn from(v: usize) -> Self { Self(v & ( (1 << PA_WIDTH_SV39) - 1 )) }
 }
 impl From<usize> for PhysPageNum {
-    fn from(v: usize) -> Self { Self(v) }
+    fn from(v: usize) -> Self { Self(v & ( (1 << PPN_WIDTH_SV39) - 1 )) }
 }
 impl From<usize> for VirtAddr {
-    fn from(v: usize) -> Self { Self(v) }
+    fn from(v: usize) -> Self { Self(v & ( (1 << VA_WIDTH_SV39) - 1 )) }
 }
 impl From<usize> for VirtPageNum {
-    fn from(v: usize) -> Self { Self(v) }
+    fn from(v: usize) -> Self { Self(v & ( (1 << VPN_WIDTH_SV39) - 1 )) }
 }
 impl From<PhysAddr> for usize {
     fn from(v: PhysAddr) -> Self { v.0 }
@@ -192,4 +197,4 @@ impl<T> Iterator for SimpleRangeIterator<T> where
         }
     }
 }
-pub type VPNRange = SimpleRange<VirtPageNum>;
\ No newline at end of file
+pub type VPNRange = SimpleRange<VirtPageNum>;