* [fix] implementation fault on avl

* [fix] mm may free varea allocated statically

* [test] add test and benchmark for avl

整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时，除hpmicro的内核，rv32内核bsp已完成去除大部分的冗余，大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件，从而提供一份公用代码，新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件：interrupt_gcc.S
- 修改原有的文件，将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改，修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件：trap_common.c；提供统一中断入口函数，中断入口函数初始化，中断入口注册等函数，并完善异常时的信息输出

- 在common中提供一份公用文件：rt_hw_stack_frame.h；将栈帧结构体剥离，供用户使用

- 在上述工作完成后，在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名，完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

> 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试，测试过程系统运行正常。

* [libcpu.aarch64] add rt_backtrace function.

[rt-smart] handling kernel from accessing unmapped user stack

fix bugs on cache maintenance when starting user app

* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces

rt_ssize_t can give negative error code, which follows the unix style correctly

* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT

* [rt-smart] asid for c906

* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error

synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes

* add new bsp-bl808

* support ARCH_RISCV_FPU_S && update rtconfig.py

* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件

* 修正cpuport.h宏定义

* 规范宏定义格式

【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件

* 对接了rt_hw_context_switch_interruptC(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)接口

* Update libcpu/risc-v/ch32v1/cpuport.c
Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>

* [smart/aarch64] sync aarch64

* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.

* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support

* [risc-v/libcpu] porting Smart & RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef

* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>

* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64
Co-authored-by: NRbb666 <zhangbingru@rt-thread.com>
Co-authored-by: Nzhkag <zhkag@foxmail.com>

If the application defines dozens of global variables,
the speed of clearing the bss segment will be slower.

Because icache can be enabled before the mmu enabled.
Therefore, in order to speed up the process of clearing the BSS segment,
enable icache needs to be put ahead.

[bsp][c28x] add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts.