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体验新版 GitCode,发现更多精彩内容 >>
提交
da701d6b
编写于
7月 03, 2021
作者:
F
fenghuijie
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
添加dcache invalidate/dcache clean&invalidate接口
上级
c77ddf44
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
48 addition
and
0 deletion
+48
-0
libcpu/arm/cortex-a/cache.c
libcpu/arm/cortex-a/cache.c
+48
-0
未找到文件。
libcpu/arm/cortex-a/cache.c
浏览文件 @
da701d6b
...
@@ -58,6 +58,37 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
...
@@ -58,6 +58,37 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
asm
volatile
(
"dsb"
:::
"memory"
);
asm
volatile
(
"dsb"
:::
"memory"
);
}
}
void
rt_hw_cpu_dcache_inv_range
(
void
*
addr
,
int
size
)
{
rt_uint32_t
line_size
=
rt_cpu_dcache_line_size
();
rt_uint32_t
start_addr
=
(
rt_uint32_t
)
addr
;
rt_uint32_t
end_addr
=
(
rt_uint32_t
)
addr
+
size
;
asm
volatile
(
"dmb"
:::
"memory"
);
if
((
start_addr
&
(
line_size
-
1
))
!=
0
)
{
start_addr
&=
~
(
line_size
-
1
);
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 1"
::
"r"
(
start_addr
));
start_addr
+=
line_size
;
asm
volatile
(
"dsb"
:::
"memory"
);
}
if
((
end_addr
&
(
line_size
-
1
))
!=
0
)
{
end_addr
&=
~
(
line_size
-
1
);
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 1"
::
"r"
(
end_addr
));
asm
volatile
(
"dsb"
:::
"memory"
);
}
while
(
start_addr
<
end_addr
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
::
"r"
(
start_addr
));
/* dcimvac */
start_addr
+=
line_size
;
}
asm
volatile
(
"dsb"
:::
"memory"
);
}
void
rt_hw_cpu_dcache_clean
(
void
*
addr
,
int
size
)
void
rt_hw_cpu_dcache_clean
(
void
*
addr
,
int
size
)
{
{
rt_uint32_t
line_size
=
rt_cpu_dcache_line_size
();
rt_uint32_t
line_size
=
rt_cpu_dcache_line_size
();
...
@@ -75,6 +106,23 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
...
@@ -75,6 +106,23 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
asm
volatile
(
"dsb"
:::
"memory"
);
asm
volatile
(
"dsb"
:::
"memory"
);
}
}
void
rt_hw_cpu_dcache_clean_inv
(
void
*
addr
,
int
size
)
{
rt_uint32_t
line_size
=
rt_cpu_dcache_line_size
();
rt_uint32_t
start_addr
=
(
rt_uint32_t
)
addr
;
rt_uint32_t
end_addr
=
(
rt_uint32_t
)
addr
+
size
+
line_size
-
1
;
asm
volatile
(
"dmb"
:::
"memory"
);
start_addr
&=
~
(
line_size
-
1
);
end_addr
&=
~
(
line_size
-
1
);
while
(
start_addr
<
end_addr
)
{
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 1"
::
"r"
(
start_addr
));
start_addr
+=
line_size
;
}
asm
volatile
(
"dsb"
:::
"memory"
);
}
void
rt_hw_cpu_icache_ops
(
int
ops
,
void
*
addr
,
int
size
)
void
rt_hw_cpu_icache_ops
(
int
ops
,
void
*
addr
,
int
size
)
{
{
if
(
ops
==
RT_HW_CACHE_INVALIDATE
)
if
(
ops
==
RT_HW_CACHE_INVALIDATE
)
...
...
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