[bsp/nuvoton] Support NuMaker-M467HJ BSP and update drivers. (#6416)

* [bsp/nuvoton] Support NuMaker-M467HJ BSP and update drivers.

* Format files.
Co-authored-by: NWayne Lin <wclin@nuvoton.com>

bsp/nuvoton/README.md

@@ -10,3 +10,4 @@ Current supported BSP shown in below table:
 | [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
 | [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |
 | [numaker-m032ki](numaker-m032ki) | Nuvoton NuMaker-M032KI |
+| [numaker-m467hj](numaker-m467hj) | Nuvoton NuMaker-M467HJ |

bsp/nuvoton/docs/LVGL_Notes.md

@@ -10,6 +10,7 @@ Current supported LVGL running environment on Nuvoton's boards shown in below ta
 | numaker-m2354 | Music | Nu-TFT v1.3 | config_lvgl |
 | nk-n9h30 | Music | No | .config |
 | numaker-m032ki | Widgets | Nu-TFT v1.3 | config_lvgl |
+| numaker-m467hj | Widgets | NuMaker-TFT-LCD43 v1.0 | config_lvgl |
 
 ## Download related packages
 

bsp/nuvoton/libraries/m031/Device/Nuvoton/M031/Include/spi_reg.h

@@ -488,7 +488,11 @@ typedef struct
     __O  uint32_t TX;                    /*!< [0x0020] SPI Data Transmit Register                                       */
     __I  uint32_t RESERVE1[3];
     __I  uint32_t RX;                    /*!< [0x0030] SPI Data Receive Register                                        */
-    __I  uint32_t RESERVE2[11];
+    __I  uint32_t RESERVE2[5];           /*!< [0x0034] Reserved                                                         */
+    __IO uint32_t INTERNAL;              /*!< [0x0048] SPI Internal Control Register                                    */
+    __I  uint32_t RESERVE3;              /*!< [0x004C] Reserved                                                         */
+    __I  uint32_t VER_NUM;               /*!< [0x0050] SPI Version Number Register                                      */
+    __I  uint32_t RESERVE4[3];           /*!< [0x0054] Reserved                                                         */
     __IO uint32_t I2SCTL;                /*!< [0x0060] I2S Control Register                                             */
     __IO uint32_t I2SCLK;                /*!< [0x0064] I2S Clock Divider Control Register                               */
     __IO uint32_t I2SSTS;                /*!< [0x0068] I2S Status Register                                              */

bsp/nuvoton/libraries/m031/rtt_port/drv_crc.c

@@ -45,8 +45,10 @@ static rt_uint32_t nu_crc_run(
 {
     uint32_t u32CalChecksum = 0;
     uint32_t i = 0;
+    rt_err_t result;
 
-    rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
+    result = rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
+    RT_ASSERT(result == RT_EOK);
 
     /* Configure CRC controller  */
     CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_WDATA_8);
@@ -86,7 +88,9 @@ static rt_uint32_t nu_crc_run(
 
     /* Get checksum value */
     u32CalChecksum = CRC_GetChecksum();
-    rt_mutex_release(&s_CRC_mutex);
+
+    result = rt_mutex_release(&s_CRC_mutex);
+    RT_ASSERT(result == RT_EOK);
 
     return u32CalChecksum;
 }
@@ -94,9 +98,7 @@ static rt_uint32_t nu_crc_run(
 rt_err_t nu_crc_init(void)
 {
     SYS_ResetModule(CRC_RST);
-
-    rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
-    return RT_EOK;
+    return rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
 }
 
 rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)

bsp/nuvoton/libraries/m031/rtt_port/drv_pdma.c

@@ -201,10 +201,13 @@ static void nu_pdma_init(void)
     /* Assign first SG table address as PDMA SG table base address */
     PDMA->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0];
 
-    /* Initializa token pool. */
+    /* Initialize token pool. */
     rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
-    latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
-    nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
+    if (NU_PDMA_SGTBL_POOL_SIZE % 32)
+    {
+        latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32;
+        nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
+    }
 
     nu_pdma_inited = 1;
 }

bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c

@@ -288,7 +288,6 @@ static struct nu_uart nu_uart_arr [] =
 #endif
     },
 #endif
-    {0}
 }; /* uart nu_uart */
 
 /* Interrupt Handle Function  ----------------------------------------------------*/
@@ -378,7 +377,7 @@ void UART57_IRQHandler(void)
 static void nu_uart_isr(nu_uart_t serial)
 {
     /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    UART_T *uart_base = serial->uart_base;
 
     /* Get interrupt event */
     uint32_t u32IntSts = uart_base->INTSTS;
@@ -413,12 +412,15 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
     uint32_t uart_stop_bit = 0;
     uint32_t uart_parity = 0;
 
-    /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    RT_ASSERT(serial);
+    RT_ASSERT(cfg);
 
     /* Check baudrate */
     RT_ASSERT(cfg->baud_rate != 0);
 
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
     /* Check word len */
     switch (cfg->data_bits)
     {
@@ -439,7 +441,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
         break;
 
     default:
-        rt_kprintf("Unsupported data length");
+        rt_kprintf("Unsupported data length\n");
         ret = RT_EINVAL;
         goto exit_nu_uart_configure;
     }
@@ -456,7 +458,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
         break;
 
     default:
-        rt_kprintf("Unsupported stop bit");
+        rt_kprintf("Unsupported stop bit\n");
         ret = RT_EINVAL;
         goto exit_nu_uart_configure;
     }
@@ -477,7 +479,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
         break;
 
     default:
-        rt_kprintf("Unsupported parity");
+        rt_kprintf("Unsupported parity\n");
         ret = RT_EINVAL;
         goto exit_nu_uart_configure;
     }
@@ -545,13 +547,12 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
     rt_size_t transferred_rxbyte = 0;
     struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
     nu_uart_t puart = (nu_uart_t)serial;
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
     UART_T *uart_base = puart->uart_base;
 
     transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len);
-
     if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
     {
         if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
@@ -576,8 +577,10 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
 
         recv_len = transferred_rxbyte - puart->rx_write_offset;
 
-        puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
-
+        if (recv_len > 0)
+        {
+            puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
+        }
     }
 
     if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
@@ -585,7 +588,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
         recv_len = puart->rxdma_trigger_len;
     }
 
-    if (recv_len)
+    if (recv_len > 0)
     {
         rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
     }
@@ -594,7 +597,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
 static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial)
 {
     rt_err_t result = RT_EOK;
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx,
                                        nu_pdma_uart_tx_cb,
@@ -608,7 +611,7 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
 {
     nu_uart_t puart = (nu_uart_t)pvOwner;
 
-    RT_ASSERT(puart != RT_NULL);
+    RT_ASSERT(puart);
 
     UART_DISABLE_INT(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
 
@@ -624,15 +627,16 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
 static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
 {
     rt_err_t result = RT_EOK;
+    nu_uart_t psNuUart = (nu_uart_t)serial;
 
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(buf != RT_NULL);
+    RT_ASSERT(serial);
+    RT_ASSERT(buf);
 
     /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    UART_T *uart_base = psNuUart->uart_base;
     if (direction == RT_SERIAL_DMA_TX)
     {
-        result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
+        result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
                                   8,
                                   (uint32_t)buf,
                                   (uint32_t)uart_base,
@@ -645,8 +649,8 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
         UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
         UART_DISABLE_INT(uart_base, UART_INTEN_RXPDMAEN_Msk);
         // If config.bufsz = 0, serial will trigger once.
-        ((nu_uart_t)serial)->rxdma_trigger_len = size;
-        ((nu_uart_t)serial)->rx_write_offset = 0;
+        psNuUart->rxdma_trigger_len = size;
+        psNuUart->rx_write_offset = 0;
         result = nu_pdma_uart_rx_config(serial, buf, size);
     }
     else
@@ -659,7 +663,7 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
 
 static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
 {
-    RT_ASSERT(pusrt != RT_NULL);
+    RT_ASSERT(pusrt);
 
     /* Allocate UART_TX nu_dma channel */
     if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
@@ -690,30 +694,31 @@ static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
  */
 static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
+    nu_uart_t psNuUart = (nu_uart_t)serial;
     rt_err_t result = RT_EOK;
-    rt_uint32_t flag;
     rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
 
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    UART_T *uart_base = psNuUart->uart_base;
 
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
         if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
         {
-            flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
-            UART_DISABLE_INT(uart_base, flag);
+            UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
         }
         else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
         {
             /* Disable Receive Line interrupt & Stop DMA RX transfer. */
 #if defined(RT_SERIAL_USING_DMA)
-            nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
-            UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
-            UART_DISABLE_INT(uart_base, UART_INTEN_RXPDMAEN_Msk);
+            if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
+            {
+                nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
+            }
+            UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
 #endif
         }
         break;
@@ -721,8 +726,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
     case RT_DEVICE_CTRL_SET_INT:
         if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
         {
-            flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
-            UART_ENABLE_INT(uart_base, flag);
+            UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
         }
         break;
 
@@ -731,9 +735,10 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
         if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
         {
             struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
-            ((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
-            ((nu_uart_t)serial)->rx_write_offset = 0;
-            result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len);  // Config & trigger
+            psNuUart->rxdma_trigger_len = serial->config.bufsz;
+            psNuUart->rx_write_offset = 0;
+
+            result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len);  // Config & trigger
         }
         else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
         {
@@ -744,15 +749,18 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
 
     case RT_DEVICE_CTRL_CLOSE:
         /* Disable NVIC interrupt. */
-        NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
+        NVIC_DisableIRQ(psNuUart->uart_irq_n);
 
 #if defined(RT_SERIAL_USING_DMA)
-        nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
-        nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
-#endif
+        UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
+        UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
 
-        /* Reset this module */
-        SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
+        if (psNuUart->dma_flag != 0)
+        {
+            nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
+            nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
+        }
+#endif
 
         /* Close UART port */
         UART_Close(uart_base);
@@ -772,7 +780,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
  */
 static int nu_uart_send(struct rt_serial_device *serial, char c)
 {
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
     UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@@ -791,7 +799,7 @@ static int nu_uart_send(struct rt_serial_device *serial, char c)
  */
 static int nu_uart_receive(struct rt_serial_device *serial)
 {
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
     UART_T *uart_base = ((nu_uart_t)serial)->uart_base;

bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c

@@ -234,8 +234,11 @@ static void nu_pdma_init(void)
 
     /* Initialize token pool. */
     rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
-    latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
-    nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
+    if (NU_PDMA_SGTBL_POOL_SIZE % 32)
+    {
+        latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32;
+        nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
+    }
 
     nu_pdma_inited = 1;
 }

bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c

@@ -238,7 +238,6 @@ static struct nu_uart nu_uart_arr [] =
 #endif
     },
 #endif
-    {0}
 }; /* uart nu_uart */
 
 /* Interrupt Handle Function  ----------------------------------------------------*/
@@ -332,7 +331,7 @@ void UART5_IRQHandler(void)
 static void nu_uart_isr(nu_uart_t serial)
 {
     /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    UART_T *uart_base = serial->uart_base;
 
     /* Get interrupt event */
     uint32_t u32IntSts = uart_base->INTSTS;
@@ -367,12 +366,15 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
     uint32_t uart_stop_bit = 0;
     uint32_t uart_parity = 0;
 
-    /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    RT_ASSERT(serial);
+    RT_ASSERT(cfg);
 
     /* Check baudrate */
     RT_ASSERT(cfg->baud_rate != 0);
 
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
     /* Check word len */
     switch (cfg->data_bits)
     {
@@ -393,7 +395,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
         break;
 
     default:
-        rt_kprintf("Unsupported data length");
+        rt_kprintf("Unsupported data length\n");
         ret = RT_EINVAL;
         goto exit_nu_uart_configure;
     }
@@ -410,7 +412,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
         break;
 
     default:
-        rt_kprintf("Unsupported stop bit");
+        rt_kprintf("Unsupported stop bit\n");
         ret = RT_EINVAL;
         goto exit_nu_uart_configure;
     }
@@ -431,7 +433,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
         break;
 
     default:
-        rt_kprintf("Unsupported parity");
+        rt_kprintf("Unsupported parity\n");
         ret = RT_EINVAL;
         goto exit_nu_uart_configure;
     }
@@ -488,7 +490,6 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
     UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
     UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
 
-
 exit_nu_pdma_uart_rx_config:
 
     return result;
@@ -500,7 +501,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
     rt_size_t transferred_rxbyte = 0;
     struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
     nu_uart_t puart = (nu_uart_t)serial;
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
     UART_T *uart_base = puart->uart_base;
@@ -531,8 +532,10 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
 
         recv_len = transferred_rxbyte - puart->rx_write_offset;
 
-        puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
-
+        if (recv_len > 0)
+        {
+            puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
+        }
     }
 
     if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
@@ -540,7 +543,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
         recv_len = puart->rxdma_trigger_len;
     }
 
-    if (recv_len)
+    if (recv_len > 0)
     {
         rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
     }
@@ -563,7 +566,7 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
 {
     nu_uart_t puart = (nu_uart_t)pvOwner;
 
-    RT_ASSERT(puart != RT_NULL);
+    RT_ASSERT(puart);
 
     UART_PDMA_DISABLE(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
 
@@ -579,29 +582,31 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
 static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
 {
     rt_err_t result = RT_EOK;
+    nu_uart_t psNuUart = (nu_uart_t)serial;
 
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(buf != RT_NULL);
+    RT_ASSERT(serial);
+    RT_ASSERT(buf);
 
     /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    UART_T *uart_base = psNuUart->uart_base;
     if (direction == RT_SERIAL_DMA_TX)
     {
-        result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
+        result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
                                   8,
                                   (uint32_t)buf,
                                   (uint32_t)uart_base,
                                   size,
                                   0);  // wait-forever
-        UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk);  // Start DMA TX transfer
+        // Start DMA TX transfer
+        UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk);
     }
     else if (direction == RT_SERIAL_DMA_RX)
     {
         UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
         UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
         // If config.bufsz = 0, serial will trigger once.
-        ((nu_uart_t)serial)->rxdma_trigger_len = size;
-        ((nu_uart_t)serial)->rx_write_offset = 0;
+        psNuUart->rxdma_trigger_len = size;
+        psNuUart->rx_write_offset = 0;
         result = nu_pdma_uart_rx_config(serial, buf, size);
     }
     else
@@ -614,7 +619,7 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
 
 static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
 {
-    RT_ASSERT(pusrt != RT_NULL);
+    RT_ASSERT(pusrt);
 
     /* Allocate UART_TX nu_dma channel */
     if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
@@ -645,30 +650,31 @@ static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
  */
 static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
+    nu_uart_t psNuUart = (nu_uart_t)serial;
     rt_err_t result = RT_EOK;
-    rt_uint32_t flag;
     rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
 
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
-    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    UART_T *uart_base = psNuUart->uart_base;
 
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
         if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
         {
-            flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
-            UART_DISABLE_INT(uart_base, flag);
+            UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
         }
         else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
         {
             /* Disable Receive Line interrupt & Stop DMA RX transfer. */
 #if defined(RT_SERIAL_USING_DMA)
-            nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
-            UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
-            UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
+            if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
+            {
+                nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
+            }
+            UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
 #endif
         }
         break;
@@ -676,8 +682,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
     case RT_DEVICE_CTRL_SET_INT:
         if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
         {
-            flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
-            UART_ENABLE_INT(uart_base, flag);
+            UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
         }
         break;
 
@@ -686,9 +691,10 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
         if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
         {
             struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
-            ((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
-            ((nu_uart_t)serial)->rx_write_offset = 0;
-            result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len);  // Config & trigger
+            psNuUart->rxdma_trigger_len = serial->config.bufsz;
+            psNuUart->rx_write_offset = 0;
+
+            result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len);  // Config & trigger
         }
         else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
         {
@@ -699,15 +705,18 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
 
     case RT_DEVICE_CTRL_CLOSE:
         /* Disable NVIC interrupt. */
-        NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
+        NVIC_DisableIRQ(psNuUart->uart_irq_n);
 
 #if defined(RT_SERIAL_USING_DMA)
-        nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
-        nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
-#endif
+        UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
+        UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
 
-        /* Reset this module */
-        SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
+        if (psNuUart->dma_flag != 0)
+        {
+            nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
+            nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
+        }
+#endif
 
         /* Close UART port */
         UART_Close(uart_base);
@@ -727,7 +736,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
  */
 static int nu_uart_send(struct rt_serial_device *serial, char c)
 {
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
     UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@@ -746,7 +755,7 @@ static int nu_uart_send(struct rt_serial_device *serial, char c)
  */
 static int nu_uart_receive(struct rt_serial_device *serial)
 {
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial);
 
     /* Get base address of uart register */
     UART_T *uart_base = ((nu_uart_t)serial)->uart_base;

bsp/nuvoton/libraries/m460/CMSIS/Include/arm_common_tables.h

+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/nuvoton/libraries/m460/CMSIS/Include/arm_const_structs.h

+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/nuvoton/libraries/m460/CMSIS/Include/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+
+#ifndef   __ASM
+    #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+    #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+#endif
+
+#include <cmsis_iar.h>
+
+/* CMSIS compiler control architecture macros */
+#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+    #ifndef __ARM_ARCH_6M__
+        #define __ARM_ARCH_6M__                      1
+    #endif
+#elif (__CORE__ == __ARM7M__)
+    #ifndef __ARM_ARCH_7M__
+        #define __ARM_ARCH_7M__                      1
+    #endif
+#elif (__CORE__ == __ARM7EM__)
+    #ifndef __ARM_ARCH_7EM__
+        #define __ARM_ARCH_7EM__                     1
+    #endif
+#endif
+
+#ifndef   __NO_RETURN
+    #define __NO_RETURN                            __noreturn
+#endif
+#ifndef   __USED
+    #define __USED                                 __root
+#endif
+#ifndef   __WEAK
+    #define __WEAK                                 __weak
+#endif
+#ifndef   __PACKED
+    #define __PACKED                               __packed
+#endif
+#ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+__packed struct T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+    //#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+#endif
+#ifndef   __RESTRICT
+    //#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+#endif
+
+// Workaround for missing __CLZ intrinsic in
+// various versions of the IAR compilers.
+// __IAR_FEATURE_CLZ__ should be defined by
+// the compiler that supports __CLZ internally.
+#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+__STATIC_INLINE uint32_t __CLZ(uint32_t data)
+{
+    if (data == 0u)
+    {
+        return 32u;
+    }
+
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while ((data & mask) == 0)
+    {
+        count += 1u;
+        mask = mask >> 1u;
+    }
+
+    return (count);
+}
+#endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+#include <cmsis_ccs.h>
+
+#ifndef   __ASM
+    #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+    #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+    #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+#endif
+#ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+struct __attribute__((packed)) T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+#endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#ifndef   __ASM
+    #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+    #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+    #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+    #define __PACKED                               __packed__
+#endif
+#ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+#endif
+#ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+struct __packed__ T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+#endif
+#ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+#endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+#include <cmsis_csm.h>
+
+#ifndef   __ASM
+    #define __ASM                                  _asm
+#endif
+#ifndef   __INLINE
+    #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+#endif
+#ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+#endif
+#ifndef   __WEAK
+    #define __WEAK                                 __weak
+#endif
+#ifndef   __PACKED
+    #define __PACKED                               @packed
+#endif
+#ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+#endif
+#ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+@packed struct T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+#endif
+#ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+#endif
+
+
+#else
+#error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/nuvoton/libraries/m460/CMSIS/Include/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+    #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/nuvoton/libraries/m460/CMSIS/Include/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+    #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+    #define __CORE_CMFUNC_H
+
+
+    /* ###########################  Core Function Access  ########################### */
+    /** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+    @{
+    */
+
+    /*------------------ RealView Compiler -----------------*/
+    #if   defined ( __CC_ARM )
+        #include "cmsis_armcc.h"
+
+        /*------------------ ARM Compiler V6 -------------------*/
+    #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+        #include "cmsis_armcc_V6.h"
+
+        /*------------------ GNU Compiler ----------------------*/
+    #elif defined ( __GNUC__ )
+        #include "cmsis_gcc.h"
+
+        /*------------------ ICC Compiler ----------------------*/
+    #elif defined ( __ICCARM__ )
+        #include <cmsis_iar.h>
+
+        /*------------------ TI CCS Compiler -------------------*/
+    #elif defined ( __TMS470__ )
+        #include <cmsis_ccs.h>
+
+        /*------------------ TASKING Compiler ------------------*/
+    #elif defined ( __TASKING__ )
+        /*
+        * The CMSIS functions have been implemented as intrinsics in the compiler.
+        * Please use "carm -?i" to get an up to date list of all intrinsics,
+        * Including the CMSIS ones.
+        */
+
+        /*------------------ COSMIC Compiler -------------------*/
+    #elif defined ( __CSMC__ )
+        #include <cmsis_csm.h>
+
+    #endif
+
+    /*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/nuvoton/libraries/m460/CMSIS/Include/core_cmInstr.h

+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+    #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+    #define __CORE_CMINSTR_H
+
+
+    /* ##########################  Core Instruction Access  ######################### */
+    /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+    Access to dedicated instructions
+    @{
+    */
+
+    /*------------------ RealView Compiler -----------------*/
+    #if   defined ( __CC_ARM )
+        #include "cmsis_armcc.h"
+
+        /*------------------ ARM Compiler V6 -------------------*/
+    #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+        #include "cmsis_armcc_V6.h"
+
+        /*------------------ GNU Compiler ----------------------*/
+    #elif defined ( __GNUC__ )
+        #include "cmsis_gcc.h"
+
+        /*------------------ ICC Compiler ----------------------*/
+    #elif defined ( __ICCARM__ )
+        #include <cmsis_iar.h>
+
+        /*------------------ TI CCS Compiler -------------------*/
+    #elif defined ( __TMS470__ )
+        #include <cmsis_ccs.h>
+
+        /*------------------ TASKING Compiler ------------------*/
+    #elif defined ( __TASKING__ )
+        /*
+        * The CMSIS functions have been implemented as intrinsics in the compiler.
+        * Please use "carm -?i" to get an up to date list of all intrinsics,
+        * Including the CMSIS ones.
+        */
+
+        /*------------------ COSMIC Compiler -------------------*/
+    #elif defined ( __CSMC__ )
+        #include <cmsis_csm.h>
+
+    #endif
+
+    /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/nuvoton/libraries/m460/CMSIS/Include/core_cmSimd.h

+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+    #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+#include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+#include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/nuvoton/libraries/m460/CMSIS/SConscript

+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+""")
+
+path = [cwd + '/Include',]
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/nuvoton/libraries/m460/Device/Nuvoton/m460/Include/NuMicro.h

+/**************************************************************************//**
+ * @file     NuMicro.h
+ * @version  V1.00
+ * @brief    NuMicro peripheral access layer header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "m460.h"
+
+#endif  /* __NUMICRO_H__ */
+
+

bsp/nuvoton/libraries/m460/SConscript

+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')