添加龙芯1C片内网卡的驱动（原创作者是chinesebear，https://github.com/chinesebear/rtt-net）

bsp/ls1cdev/applications/application.c

@@ -16,11 +16,15 @@
 
 #include <rtthread.h>
 #include <components.h>
+#include "net/synopGMAC.h"
+#include <lwip/api.h>
 
 void rt_init_thread_entry(void *parameter)
 {
+	
 	/* initialization RT-Thread Components */
 	rt_components_init();
+	rt_hw_eth_init();
 }
 
 int rt_application_init(void)

bsp/ls1cdev/drivers/SConscript

@@ -7,4 +7,14 @@ CPPPATH = [cwd]
 
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+group = group + objs
+
 Return('group')

bsp/ls1cdev/drivers/net/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+
+Return('group')

bsp/ls1cdev/drivers/net/debug.h

+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//#define GMAC_DEBUG
+#include <rtthread.h>
+#ifdef GMAC_DEBUG	
+#define DEBUG_MES	rt_kprintf
+#else
+#define DEBUG_MES(...)
+#endif
+
+#endif /*__DEBUG_H__*/

bsp/ls1cdev/drivers/net/mii.c

+#include "mii.h"
+
+#if 1
+static inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+	unsigned int ret;
+
+	if (negotiated & LPA_100FULL)
+		ret = LPA_100FULL;
+	else if (negotiated & LPA_100BASE4)
+		ret = LPA_100BASE4;
+	else if (negotiated & LPA_100HALF)
+		ret = LPA_100HALF;
+	else if (negotiated & LPA_10FULL)
+		ret = LPA_10FULL;
+	else
+		ret = LPA_10HALF;
+
+	return ret;
+}
+
+static int mii_check_gmii_support(struct mii_if_info *mii)
+{
+	int reg;
+
+	reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
+	if (reg & BMSR_ESTATEN) {
+		reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS);
+		if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF))
+			return 1;
+	}
+
+	return 0;
+}
+
+static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
+{
+	struct synopGMACNetworkAdapter * dev = mii->dev;
+	u32 advert, bmcr, lpa, nego;
+	u32 advert2 = 0, bmcr2 = 0, lpa2 = 0;
+
+	ecmd->supported =
+	    (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
+	     SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
+	     SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
+	if (mii->supports_gmii)
+		ecmd->supported |= SUPPORTED_1000baseT_Half |
+			SUPPORTED_1000baseT_Full;
+
+	/* only supports twisted-pair */
+	ecmd->port = PORT_MII;
+
+	/* only supports internal transceiver */
+	ecmd->transceiver = XCVR_INTERNAL;
+
+	/* this isn't fully supported at higher layers */
+	ecmd->phy_address = mii->phy_id;
+
+	ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
+	advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
+	if (mii->supports_gmii)
+		advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
+
+	if (advert & ADVERTISE_10HALF)
+		ecmd->advertising |= ADVERTISED_10baseT_Half;
+	if (advert & ADVERTISE_10FULL)
+		ecmd->advertising |= ADVERTISED_10baseT_Full;
+	if (advert & ADVERTISE_100HALF)
+		ecmd->advertising |= ADVERTISED_100baseT_Half;
+	if (advert & ADVERTISE_100FULL)
+		ecmd->advertising |= ADVERTISED_100baseT_Full;
+	if (advert2 & ADVERTISE_1000HALF)
+		ecmd->advertising |= ADVERTISED_1000baseT_Half;
+	if (advert2 & ADVERTISE_1000FULL)
+		ecmd->advertising |= ADVERTISED_1000baseT_Full;
+
+	bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
+	lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
+	if (mii->supports_gmii) {
+		bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
+		lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
+	}
+	if (bmcr & BMCR_ANENABLE) {
+		ecmd->advertising |= ADVERTISED_Autoneg;
+		ecmd->autoneg = AUTONEG_ENABLE;
+		
+		nego = mii_nway_result(advert & lpa);
+		if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & 
+		    (lpa2 >> 2))
+			ecmd->speed = SPEED_1000;
+		else if (nego == LPA_100FULL || nego == LPA_100HALF)
+			ecmd->speed = SPEED_100;
+		else
+			ecmd->speed = SPEED_10;
+		if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
+		    nego == LPA_10FULL) {
+			ecmd->duplex = DUPLEX_FULL;
+			mii->full_duplex = 1;
+		} else {
+			ecmd->duplex = DUPLEX_HALF;
+			mii->full_duplex = 0;
+		}
+	} else {
+		ecmd->autoneg = AUTONEG_DISABLE;
+
+		ecmd->speed = ((bmcr & BMCR_SPEED1000 && 
+				(bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 :
+			       (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10);
+		ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+	}
+
+	/* ignore maxtxpkt, maxrxpkt for now */
+
+	return 0;
+}
+
+static int mii_link_ok (struct mii_if_info *mii)
+{
+	/* first, a dummy read, needed to latch some MII phys */
+	mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
+	if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)
+		return 1;
+	return 0;
+}
+#endif

bsp/ls1cdev/drivers/net/mii.h

+#ifndef __MII_H__
+#define __MII_H__
+/* Generic MII registers. */
+
+#include "types.h"
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_CTRL1000        0x09        /* 1000BASE-T control          */
+#define MII_STAT1000        0x0a        /* 1000BASE-T status           */
+#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x003f  /* Unused...                   */
+#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x00c0  /* Unused...                   */
+#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_100FULL2		0x0200	/* Can do 100BASE-T2 HDX */
+#define BMSR_100HALF2		0x0400	/* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
+#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
+#define ADVERTISE_RESV          0x1000  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Indicates what features are advertised by the interface. */
+#define ADVERTISED_10baseT_Half		(1 << 0)
+#define ADVERTISED_10baseT_Full		(1 << 1)
+#define ADVERTISED_100baseT_Half	(1 << 2)
+#define ADVERTISED_100baseT_Full	(1 << 3)
+#define ADVERTISED_1000baseT_Half	(1 << 4)
+#define ADVERTISED_1000baseT_Full	(1 << 5)
+#define ADVERTISED_Autoneg		(1 << 6)
+#define ADVERTISED_TP			(1 << 7)
+#define ADVERTISED_AUI			(1 << 8)
+#define ADVERTISED_MII			(1 << 9)
+#define ADVERTISED_FIBRE		(1 << 10)
+#define ADVERTISED_BNC			(1 << 11)
+#define ADVERTISED_10000baseT_Full	(1 << 12)
+#define ADVERTISED_Pause		(1 << 13)
+#define ADVERTISED_Asym_Pause		(1 << 14)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
+#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
+#define LPA_RESV                0x1000  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
+#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK       0x2000  /* Link partner local receiver status */
+#define LPA_1000REMRXOK         0x1000  /* Link partner remote receiver status */
+#define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex */
+
+#define SUPPORTED_10baseT_Half		(1 << 0)
+#define SUPPORTED_10baseT_Full		(1 << 1)
+#define SUPPORTED_100baseT_Half		(1 << 2)
+#define SUPPORTED_100baseT_Full		(1 << 3)
+#define SUPPORTED_1000baseT_Half	(1 << 4)
+#define SUPPORTED_1000baseT_Full	(1 << 5)
+#define SUPPORTED_Autoneg		(1 << 6)
+#define SUPPORTED_TP			(1 << 7)
+#define SUPPORTED_AUI			(1 << 8)
+#define SUPPORTED_MII			(1 << 9)
+#define SUPPORTED_FIBRE			(1 << 10)
+#define SUPPORTED_BNC			(1 << 11)
+#define SUPPORTED_10000baseT_Full	(1 << 12)
+#define SUPPORTED_Pause			(1 << 13)
+#define SUPPORTED_Asym_Pause		(1 << 14)
+
+
+/* Which connector port. */
+#define PORT_TP         0x00
+#define PORT_AUI        0x01
+#define PORT_MII        0x02 
+#define PORT_FIBRE      0x03
+#define PORT_BNC        0x04
+
+/* Which transceiver to use. */
+#define XCVR_INTERNAL       0x00
+#define XCVR_EXTERNAL       0x01
+#define XCVR_DUMMY1     0x02 
+#define XCVR_DUMMY2     0x03 
+#define XCVR_DUMMY3     0x04
+
+#define AUTONEG_DISABLE		0x00
+#define AUTONEG_ENABLE		0x01
+
+
+#define SPEED_10		10
+#define SPEED_100		100
+#define SPEED_1000		1000
+#define SPEED_2500		2500
+#define SPEED_10000		10000
+
+#define DUPLEX_HALF		0x00
+#define DUPLEX_FULL		0x01
+
+struct ethtool_cmd {
+	u32	cmd;
+	u32	supported;	/* Features this interface supports */
+	u32	advertising;	/* Features this interface advertises */
+	u16	speed;		/* The forced speed, 10Mb, 100Mb, gigabit */
+	u8	duplex;		/* Duplex, half or full */
+	u8	port;		/* Which connector port */
+	u8	phy_address;
+	u8	transceiver;	/* Which transceiver to use */
+	u8	autoneg;	/* Enable or disable autonegotiation */
+	u32	maxtxpkt;	/* Tx pkts before generating tx int */
+	u32	maxrxpkt;	/* Rx pkts before generating rx int */
+	u32	reserved[4];
+};
+
+struct mii_if_info {
+	int phy_id;
+	int advertising;
+	int phy_id_mask;
+	int reg_num_mask;
+
+	unsigned int full_duplex : 1;	/* is full duplex? */
+	unsigned int force_media : 1;	/* is autoneg. disabled? */
+	unsigned int supports_gmii : 1; /* are GMII registers supported? */
+
+	struct synopGMACNetworkAdapter  *dev;
+	int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location);
+	void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val);
+};
+
+#endif

bsp/ls1cdev/drivers/net/ping.c

+/*
+ * netutils: ping implementation
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/icmp.h"
+#include "lwip/netif.h"
+#include "lwip/sys.h"
+#include "lwip/sockets.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip.h"
+#include <rthw.h>
+#include <rtthread.h>
+
+/**
+ * PING_DEBUG: Enable debugging for PING.
+ */
+#ifndef PING_DEBUG
+#define PING_DEBUG     LWIP_DBG_ON
+#endif
+
+/** ping receive timeout - in milliseconds */
+#define PING_RCV_TIMEO 1000
+/** ping delay - in milliseconds */
+#define PING_DELAY     100
+
+/** ping identifier - must fit on a u16_t */
+#ifndef PING_ID
+#define PING_ID        0xAFAF
+#endif
+
+/** ping additional data size to include in the packet */
+#ifndef PING_DATA_SIZE
+#define PING_DATA_SIZE 32
+#endif
+
+/* ping variables */
+static u16_t ping_seq_num;
+struct _ip_addr
+{
+    rt_uint8_t addr0, addr1, addr2, addr3;
+};
+
+/** Prepare a echo ICMP request */
+static void ping_prepare_echo( struct icmp_echo_hdr *iecho, u16_t len)
+{
+    size_t i;
+    size_t data_len = len - sizeof(struct icmp_echo_hdr);
+
+    ICMPH_TYPE_SET(iecho, ICMP_ECHO);
+    ICMPH_CODE_SET(iecho, 0);
+    iecho->chksum = 0;
+    iecho->id     = PING_ID;
+    iecho->seqno  = htons(++ping_seq_num);
+
+    /* fill the additional data buffer with some data */
+    for(i = 0; i < data_len; i++)
+    {
+        ((char*)iecho)[sizeof(struct icmp_echo_hdr) + i] = (char)i;
+    }
+
+    iecho->chksum = inet_chksum(iecho, len);
+}
+
+/* Ping using the socket ip */
+static err_t ping_send(int s, struct ip_addr *addr, int size)
+{
+    int err;
+    struct icmp_echo_hdr *iecho;
+    struct sockaddr_in to;
+    size_t ping_size = sizeof(struct icmp_echo_hdr) + size;
+    LWIP_ASSERT("ping_size is too big", ping_size <= 0xffff);
+
+    iecho = rt_malloc(ping_size);
+    if (iecho == RT_NULL)
+    {
+        return ERR_MEM;
+    }
+
+    ping_prepare_echo(iecho, (u16_t)ping_size);
+
+    to.sin_len = sizeof(to);
+    to.sin_family = AF_INET;
+    to.sin_addr.s_addr = addr->addr;
+
+    err = lwip_sendto(s, iecho, ping_size, 0, (struct sockaddr*)&to, sizeof(to));
+    rt_free(iecho);
+
+    return (err ? ERR_OK : ERR_VAL);
+}
+
+static void ping_recv(int s)
+{
+    char buf[64];
+    int fromlen, len;
+    struct sockaddr_in from;
+    struct ip_hdr *iphdr;
+    struct icmp_echo_hdr *iecho;
+    struct _ip_addr *addr;
+
+    while((len = lwip_recvfrom(s, buf, sizeof(buf), 0, (struct sockaddr*)&from, (socklen_t*)&fromlen)) > 0)
+    {
+        if (len >= (sizeof(struct ip_hdr)+sizeof(struct icmp_echo_hdr)))
+        {
+            addr = (struct _ip_addr *)&(from.sin_addr);
+            rt_kprintf("ping: recv %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+
+            iphdr = (struct ip_hdr *)buf;
+            iecho = (struct icmp_echo_hdr *)(buf+(IPH_HL(iphdr) * 4));
+            if ((iecho->id == PING_ID) && (iecho->seqno == htons(ping_seq_num)))
+            {
+                return;
+            }
+            else
+            {
+                rt_kprintf("ping: drop\n");
+            }
+        }
+    }
+
+    if (len <= 0)
+    {
+        rt_kprintf("ping: timeout\n");
+    }
+}
+
+rt_err_t ping(char* target, rt_uint32_t time, rt_size_t size)
+{
+    int s;
+    int timeout = PING_RCV_TIMEO;
+    struct ip_addr ping_target;
+    rt_uint32_t send_time;
+    struct _ip_addr
+    {
+        rt_uint8_t addr0, addr1, addr2, addr3;
+    } *addr;
+
+    send_time = 0;
+
+    if(size == 0)
+        size = PING_DATA_SIZE;
+
+    if (inet_aton(target, (struct in_addr*)&ping_target) == 0) return -RT_ERROR;
+    addr = (struct _ip_addr*)&ping_target;
+
+    if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0)
+    {
+        rt_kprintf("create socket failled\n");
+        return -RT_ERROR;
+    }
+
+    lwip_setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
+
+    while (1)
+    {
+        if (ping_send(s, &ping_target, size) == ERR_OK)
+        {
+            rt_kprintf("ping: send %d.%d.%d.%d\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+            ping_recv(s);
+        }
+        else
+        {
+            rt_kprintf("ping: send %d.%d.%d.%d - error\n", addr->addr0, addr->addr1, addr->addr2, addr->addr3);
+        }
+
+        send_time ++;
+        if (send_time >= time) break; /* send ping times reached, stop */
+
+        rt_thread_delay(PING_DELAY); /* take a delay */
+    }
+
+    lwip_close(s);
+
+    return RT_EOK;
+}
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT(ping, ping network host)
+#endif

bsp/ls1cdev/drivers/net/synopGMAC.h

+#ifndef __SYNOPGMAC__H
+#define __SYNOPGMAC__H
+
+#include "synopGMAC_network_interface.h"
+#include "synopGMAC_Host.h"
+#include "synopGMAC_Dev.h"
+#include "synopGMAC_plat.h"
+#include "mii.h"
+#include "types.h"
+
+void rt_hw_eth_init(void);
+
+#endif	/*__SYNOPGMAC__H*/

bsp/ls1cdev/drivers/net/synopGMAC_Host.h

+#ifndef SYNOP_GMAC_HOST_H
+#define SYNOP_GMAC_HOST_H 1
+
+/*
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+*/
+
+#include "synopGMAC_plat.h"
+//#include "synopGMAC_pci_bus_interface.h"
+#include "synopGMAC_Dev.h"
+#include "mii.h"
+
+//#define ENH_DESC
+//#define ENH_DESC_8W
+
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received 	*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+	
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+/*
+struct	PmonInet{
+	struct device sc_dev;
+	void *sc_ih;
+
+	struct arpcom arpcom;
+		
+//	struct mii_data sc_mii;		// MII media information 
+	char  dev_addr[6]; //the net interface's address
+	unsigned long ioaddr;
+
+//	int flags;
+//	int mc_count;
+
+};
+*/	
+
+
+//typedef struct synopGMACAdapterStruct{
+#if 0
+struct synopGMACAdapterStruct{
+
+/*Device Dependent Data structur*/
+struct synopGMACdevice * synopGMACdev;
+
+/*Os/Platform Dependent Data Structures*/
+//struct pci_dev * synopGMACpcidev;
+
+//struct net_device *synopGMACnetdev;
+
+struct net_device_stats synopGMACNetStats;
+//u32 synopGMACPciState[16];
+
+struct PmonInet * PInetdev;
+
+//} synopGMACPciNetworkAdapter;
+}synopGMACNetworkAdapter;
+#endif
+typedef struct synopGMACNetworkAdapter{
+
+/*Device Dependent Data structur*/
+synopGMACdevice * synopGMACdev;
+
+/*Os/Platform Dependent Data Structures*/
+//struct pci_dev * synopGMACpcidev;
+
+//struct net_device *synopGMACnetdev;
+
+struct net_device_stats synopGMACNetStats;
+//u32 synopGMACPciState[16];
+
+//struct PmonInet * PInetdev;
+
+struct mii_if_info mii;
+} synopGMACPciNetworkAdapter;
+
+/*
+static struct mbuf * getmbuf(struct synopGMACNetworkAdapter * tp)
+{
+	struct mbuf *m;
+//	struct PomnInet * tp = adapter->PInetDev;
+
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if(m == NULL){
+		printf("getmbuf failed, Out of memory!!!\n");
+		return  NULL;
+	} else {
+		MCLGET(m, M_DONTWAIT);
+		if ((m->m_flags & M_EXT) == 0) {
+			m_freem(m);
+			return NULL;
+		}
+		if(m->m_data != m->m_ext.ext_buf){
+			printf("m_data not equal to ext_buf!!!\n");
+		}
+	}
+	
+#if defined(__mips__)
+
+//	pci_sync_cache(tp->sc_pc, (vm_offset_t)tp->tx_buffer[entry], len, SYNC_W);
+
+	;
+#define RFA_ALIGNMENT_FUDGE 2
+	m->m_data += RFA_ALIGNMENT_FUDGE;
+#else
+	m->m_data += RFA_ALIGNMENT_FUDGE;
+#endif
+	return m;
+}
+*/
+
+
+
+
+#endif

bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h

+/** \file
+ * Header file for the nework dependent functionality.
+ * The function prototype listed here are linux dependent.
+ *   
+ * \internal
+ * ---------------------------REVISION HISTORY-------------------
+ * Synopsys 			01/Aug/2007		Created
+ */
+ 
+#ifndef SYNOP_GMAC_NETWORK_INTERFACE_H
+#define SYNOP_GMAC_NETWORK_INTERFACE_H 1
+
+#include "synopGMAC_plat.h"
+#include "synopGMAC_Host.h"
+#include "synopGMAC_Dev.h"
+
+//#include <common.h>
+//#include <net.h>
+//#include <linux/stddef.h>
+
+
+#define NET_IF_TIMEOUT (10*HZ)
+#define CHECK_TIME (HZ)
+
+s32  synopGMAC_init_network_interface(char* xname,u64 synopGMACMappedAddr);
+void  synopGMAC_exit_network_interface(void);
+
+s32 synopGMAC_linux_open(struct eth_device *);
+s32 synopGMAC_linux_close(struct eth_device *);
+//s32 synopGMAC_linux_xmit_frames(struct ifnet *);
+struct net_device_stats * synopGMAC_linux_get_stats(struct synopGMACNetworkAdapter *);
+//void synopGMAC_linux_set_multicast_list(struct net_device *);
+//s32 synopGMAC_linux_set_mac_address(struct synopGMACNetwokrAdapter*,void *);
+//s32 synopGMAC_linux_change_mtu(struct net_device *,s32);
+//s32 synopGMAC_linux_do_ioctl(struct ifnet *,struct ifreq *,s32);
+//void synopGMAC_linux_tx_timeout(struct net_device *);
+
+s32 synopGMAC_test(synopGMACdevice * gmacdev_0,synopGMACdevice * gmacdev_1);
+
+void dumpreg(u64 );
+void dumpphyreg();
+
+/*
+ *  gethex(vp,p,n)
+ *      convert n hex digits from p to binary, result in vp,
+ *      rtn 1 on success
+ */
+static int gethex(u8 *vp, char *p, int n)
+{
+        u8 v;
+        int digit;
+
+        for (v = 0; n > 0; n--) {
+                if (*p == 0)
+                        return (0);
+                if (*p >= '0' && *p <= '9')
+                        digit = *p - '0';
+                else if (*p >= 'a' && *p <= 'f')
+                        digit = *p - 'a' + 10;
+                else if (*p >= 'A' && *p <= 'F')
+                        digit = *p - 'A' + 10;
+                else
+                        return (0);
+
+                v <<= 4;
+                v |= digit;
+                p++;
+        }
+        *vp = v;
+        return (1);
+}
+
+#endif /* End of file */

bsp/ls1cdev/drivers/net/synopGMAC_plat.c

+/**\file
+ *  This file defines the wrapper for the platform/OS related functions
+ *  The function definitions needs to be modified according to the platform 
+ *  and the Operating system used.
+ *  This file should be handled with greatest care while porting the driver
+ *  to a different platform running different operating system other than
+ *  Linux 2.6.xx.
+ * \internal
+ * ----------------------------REVISION HISTORY-----------------------------
+ * Synopsys			01/Aug/2007			Created
+ */
+ 
+#include "synopGMAC_plat.h"
+#include "synopGMAC_Dev.h"
+#include <rthw.h>
+#include <rtthread.h>
+extern void flush_cache(unsigned long start_addr, unsigned long size);
+dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va,u32 size)
+{
+	return VA_TO_PA (va);
+	//return UNCACHED_TO_PHYS(va);
+}
+
+
+
+/**
+  * This is a wrapper function for Memory allocation routine. In linux Kernel 
+  * it it kmalloc function
+  * @param[in] bytes in bytes to allocate
+  */
+
+void *plat_alloc_memory(u32 bytes) 
+{
+//return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT);
+	void *buf = (void*)rt_malloc((u32)bytes);
+
+	flush_cache((unsigned long)buf, bytes);
+	return buf;
+}
+
+/**
+  * This is a wrapper function for consistent dma-able Memory allocation routine. 
+  * In linux Kernel, it depends on pci dev structure
+  * @param[in] bytes in bytes to allocate
+  */
+
+//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr) 
+void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) 
+{
+	void *buf;
+	buf = (void*)rt_malloc((u32)(size+16));
+	//CPU_IOFlushDCache( buf,size, SYNC_W);
+	unsigned long i = (unsigned long)buf;
+//	rt_kprintf("size = %d\n", size);
+//	rt_kprintf("bufaddr = %p\n", buf);
+//	rt_kprintf("i%%16 == %d\n", i%16);
+	if(i%16 == 8){
+		i += 8;
+	}
+	else if(i%16 == 4){
+		i += 12;
+	}
+	else if(i%16 == 12){
+		i += 4;
+	}
+
+	flush_cache(i, size);
+	*addr =gmac_dmamap(i, size);
+	buf = (unsigned char *)CACHED_TO_UNCACHED(i);
+//	rt_kprintf("bufaddr = %p\n", buf);
+	return buf;
+}
+
+
+/**
+  * This is a wrapper function for freeing consistent dma-able Memory.
+  * In linux Kernel, it depends on pci dev structure
+  * @param[in] bytes in bytes to allocate
+  */
+
+
+//void plat_free_consistent_dmaable_memory(void * addr) 
+void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr) 
+{
+	rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr)));
+ return;
+}
+
+
+
+/**
+  * This is a wrapper function for Memory free routine. In linux Kernel 
+  * it it kfree function
+  * @param[in] buffer pointer to be freed
+  */
+void plat_free_memory(void *buffer) 
+{
+	rt_free(buffer);
+	return ;
+}
+
+
+
+dma_addr_t plat_dma_map_single(void *hwdev, void *ptr,
+		                    u32 size)
+{
+	    unsigned long addr = (unsigned long) ptr;
+//CPU_IOFlushDCache(addr,size, direction);
+	flush_cache(addr, size);
+return gmac_dmamap(addr, size);
+}
+
+/**
+  * This is a wrapper function for platform dependent delay 
+  * Take care while passing the argument to this function 
+  * @param[in] buffer pointer to be freed
+  */
+void plat_delay(u32 delay)
+{
+	while (delay--);
+	return;
+}
+
+

bsp/ls1cdev/drivers/net/synopGMAC_plat.h

+/**\file
+ *  This file serves as the wrapper for the platform/OS dependent functions
+ *  It is needed to modify these functions accordingly based on the platform and the
+ *  OS. Whenever the synopsys GMAC driver ported on to different platform, this file
+ *  should be handled at most care.
+ *  The corresponding function definitions for non-inline functions are available in 
+ *  synopGMAC_plat.c file.
+ * \internal
+ * -------------------------------------REVISION HISTORY---------------------------
+ * Synopsys 				01/Aug/2007		 	   Created
+ */
+ 
+ 
+#ifndef SYNOP_GMAC_PLAT_H
+#define SYNOP_GMAC_PLAT_H 1
+
+/*	sw
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+*/
+#include "types.h"
+#include "debug.h"
+//#include "mii.h"
+//#include "GMAC_Pmon.h"
+//#include "synopGMAC_Host.h"
+#include <rtthread.h>
+//sw:	copy the type define into here
+#define IOCTL_READ_REGISTER  SIOCDEVPRIVATE+1
+#define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2
+#define IOCTL_READ_IPSTRUCT  SIOCDEVPRIVATE+3
+#define IOCTL_READ_RXDESC    SIOCDEVPRIVATE+4
+#define IOCTL_READ_TXDESC    SIOCDEVPRIVATE+5
+#define IOCTL_POWER_DOWN     SIOCDEVPRIVATE+6
+
+#define SYNOP_GMAC0 1
+
+typedef int bool;
+//typedef unsigned long dma_addr_t;
+
+//sw
+/* write/read MMIO register */
+#define writeb(val, addr) (*(volatile u8*)(addr) = (val))
+#define writew(val, addr) (*(volatile u16*)(addr) = (val))
+#define writel(val, addr) (*(volatile u32*)(addr) = (val))
+#define readb(addr) (*(volatile u8*)(addr))
+#define readw(addr) (*(volatile u16*)(addr))
+#define readl(addr) (*(volatile u32*)(addr))
+
+
+#define KUSEG_ADDR              0x0
+#define CACHED_MEMORY_ADDR      0x80000000
+#define UNCACHED_MEMORY_ADDR    0xa0000000
+#define KSEG2_ADDR              0xc0000000
+#define MAX_MEM_ADDR            0xbe000000
+#define RESERVED_ADDR           0xbfc80000
+
+#define CACHED_TO_PHYS(x)       ((unsigned)(x) & 0x7fffffff)
+#define PHYS_TO_CACHED(x)       ((unsigned)(x) | CACHED_MEMORY_ADDR)
+#define UNCACHED_TO_PHYS(x)     ((unsigned)(x) & 0x1fffffff)
+#define PHYS_TO_UNCACHED(x)     ((unsigned)(x) | UNCACHED_MEMORY_ADDR)
+#define VA_TO_CINDEX(x)         ((unsigned)(x) & 0xffffff | CACHED_MEMORY_ADDR)
+#define CACHED_TO_UNCACHED(x)   (PHYS_TO_UNCACHED(CACHED_TO_PHYS(x)))
+
+#define VA_TO_PA(x)     UNCACHED_TO_PHYS(x)
+
+
+/*	sw
+#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)				
+
+#ifdef DEBUG
+#undef TR
+#  define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
+#else
+# define TR(fmt, args...) // not debugging: nothing 
+#endif
+*/
+/*
+#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)				
+*/
+
+/*
+#ifdef DEBUG
+#undef TR
+#  define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
+#else
+//# define TR(fmt, args...) // not debugging: nothing 
+#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)				
+#endif
+*/
+
+//sw: nothing to display
+#define TR0(fmt, args...) rt_kprintf(fmt, ##args)		
+#define TR(fmt, args...)  rt_kprintf(fmt, ##args) 
+//#define TR rt_kprintf
+
+//typedef int bool;
+enum synopGMAC_boolean
+ { 
+    false = 0,
+    true = 1 
+ };
+
+
+#define DEFAULT_DELAY_VARIABLE  10
+#define DEFAULT_LOOP_VARIABLE   10000
+
+/* There are platform related endian conversions
+ *
+ */
+
+#define LE32_TO_CPU	__le32_to_cpu
+#define BE32_TO_CPU	__be32_to_cpu
+#define CPU_TO_LE32	__cpu_to_le32
+
+/* Error Codes */
+#define ESYNOPGMACNOERR   0
+#define ESYNOPGMACNOMEM   1
+#define ESYNOPGMACPHYERR  2
+#define ESYNOPGMACBUSY    3
+
+struct Network_interface_data
+{
+	u32 unit;
+	u32 addr;
+	u32 data;
+};
+
+
+/**
+  * These are the wrapper function prototypes for OS/platform related routines
+  */ 
+
+void * plat_alloc_memory(u32 );
+void   plat_free_memory(void *);
+
+//void * plat_alloc_consistent_dmaable_memory(struct pci_dev *, u32, u32 *);
+//void   plat_free_consistent_dmaable_memory (struct pci_dev *, u32, void *, u32);
+
+void   plat_delay(u32);
+
+
+/**
+ * The Low level function to read register contents from Hardware.
+ * 
+ * @param[in] pointer to the base of register map  
+ * @param[in] Offset from the base
+ * \return  Returns the register contents 
+ */
+static u32  synopGMACReadReg(u32 RegBase, u32 RegOffset)
+{
+
+  u32 addr;
+  u32 data;
+
+		  addr = RegBase + (u32)RegOffset;
+
+#if 0 //__mips >= 3 && __mips != 32
+	__asm __volatile(
+			".set\tnoreorder\n\t"
+			".set\tmips3\n\t"
+			"ld $8,%1\n\t"
+			"lw $9,0x0($8)\n\t"
+			"nop\n\t"
+			"nop\n\t"
+			"sw $9,%0\n\t"
+			".set\tmips0\n\t"
+			:"=m"(data)
+			:"m"(addr)
+			:"memory","$8","$9"
+			);
+#else
+	data = *(volatile u32 *)addr;
+#endif
+
+#if SYNOP_REG_DEBUG
+  TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
+#endif
+//  rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
+  return data;
+
+}
+
+/**
+ * The Low level function to write to a register in Hardware.
+ * 
+ * @param[in] pointer to the base of register map  
+ * @param[in] Offset from the base
+ * @param[in] Data to be written 
+ * \return  void 
+ */
+static void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData )
+{
+
+  u32 addr;
+
+		  addr = RegBase + (u32)RegOffset;
+//  rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
+#if SYNOP_REG_DEBUG
+  TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
+#endif
+//  writel(RegData,(void *)addr);
+  //printf("GMAC addr = 0x%lx \n",addr);
+#if 0 //__mips >= 3 && __mips != 32
+	__asm __volatile(
+			".set\tnoreorder\n\t"
+			".set\tmips3\n\t"
+			"lw $9,%0\n\t"
+			"ld $8,%1\n\t"
+			"sw $9,0x0($8)\n\t"
+			".set\tmips0\n\t"
+			:
+			:"m"(RegData),"m"(addr)
+			:"memory","$8","$9"
+			);
+#else
+	*(volatile u32 *)addr = RegData;
+#endif
+	if(addr == 0xbfe1100c)
+		DEBUG_MES("regdata = %08x\n", RegData);
+  return;
+}
+
+/**
+ * The Low level function to set bits of a register in Hardware.
+ * 
+ * @param[in] pointer to the base of register map  
+ * @param[in] Offset from the base
+ * @param[in] Bit mask to set bits to logical 1 
+ * \return  void 
+ */
+static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos)
+{
+  //u64 addr = (u64)RegBase + (u64)RegOffset;
+  u32 data;
+  data = synopGMACReadReg(RegBase, RegOffset);
+  data |= BitPos; 
+  synopGMACWriteReg(RegBase, RegOffset, data);
+ // writel(data,(void *)addr);
+#if SYNOP_REG_DEBUG
+  TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
+#endif
+  return;
+}
+
+
+/**
+ * The Low level function to clear bits of a register in Hardware.
+ * 
+ * @param[in] pointer to the base of register map  
+ * @param[in] Offset from the base
+ * @param[in] Bit mask to clear bits to logical 0 
+ * \return  void 
+ */
+static void  synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos)
+{
+  u32 data;
+  data = synopGMACReadReg(RegBase, RegOffset);
+  data &= (~BitPos); 
+  synopGMACWriteReg(RegBase, RegOffset, data);
+#if SYNOP_REG_DEBUG
+  TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
+#endif
+  return;
+}
+
+/**
+ * The Low level function to Check the setting of the bits.
+ * 
+ * @param[in] pointer to the base of register map  
+ * @param[in] Offset from the base
+ * @param[in] Bit mask to set bits to logical 1 
+ * \return  returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
+ * 
+ */
+static bool  synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos)
+{
+
+  u32 data;
+  data = synopGMACReadReg(RegBase, RegOffset);
+  data &= BitPos; 
+  if(data)  return true;
+  else	    return false;
+
+}
+
+
+
+
+
+#endif

bsp/ls1cdev/drivers/net/types.h

+#ifndef __TYPES__H
+#define __TYPES__H
+
+typedef unsigned char uint8_t;
+typedef unsigned long long  u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+typedef signed int s32;
+
+typedef u32 dma_addr_t;
+
+#endif	/*__TYPES__H*/

bsp/ls1cdev/rtconfig.h

@@ -131,15 +131,21 @@
 // <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
 // #define RT_USING_DFS_NFS
 // <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.3.108:/"
+#define RT_NFS_HOST_EXPORT	"192.168.1.254:/"
 // </section>
 
 // <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
-// #define RT_USING_LWIP
+#define RT_USING_LWIP
+#define RT_USING_GMAC_INT_MODE
+#define RT_USING_LWIP141
+//#define RT_LWIP_DEBUG
+#define RT_LWIP_USING_RT_MEM
+
+
 // <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
 #define RT_LWIP_ICMP
 // <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
-// #define RT_LWIP_IGMP
+#define RT_LWIP_IGMP
 // <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
 #define RT_LWIP_UDP
 // <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
@@ -148,10 +154,11 @@
 #define RT_LWIP_DNS
 // <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
 #define RT_LWIP_PBUF_NUM	4
+#define RT_LWIP_PBUF_POOL_BUFSIZE 2048
 // <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
 #define RT_LWIP_TCP_PCB_NUM	3
 // <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
-#define RT_LWIP_TCP_SND_BUF	2048
+#define RT_LWIP_TCP_SND_BUF	4096
 // <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
 #define RT_LWIP_TCP_WND	2048
 // <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
@@ -159,7 +166,7 @@
 // <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
 // #define RT_LWIP_DHCP
 // <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
-#define RT_LWIP_TCP_SEG_NUM	4
+#define RT_LWIP_TCP_SEG_NUM	40
 // <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
 #define RT_LWIP_TCPTHREAD_PRIORITY	12
 // <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
@@ -175,13 +182,13 @@
 // <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
 #define RT_LWIP_IPADDR0 192
 #define RT_LWIP_IPADDR1 168
-#define RT_LWIP_IPADDR2 3
-#define RT_LWIP_IPADDR3 108
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 254
 // <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
 #define RT_LWIP_GWADDR0 192
 #define RT_LWIP_GWADDR1 168
-#define RT_LWIP_GWADDR2 3
-#define RT_LWIP_GWADDR3 1
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 3
 // <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
 #define RT_LWIP_MSKADDR0 255
 #define RT_LWIP_MSKADDR1 255

libcpu/mips/loongson_1c/cpuport.c

@@ -121,5 +121,41 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
 	return (rt_uint8_t *)stk;
 }
 
+#define cache_op(op,addr)                       \
+	    __asm__ __volatile__(                       \
+				    "   .set    push                    \n" \
+				    "   .set    noreorder               \n" \
+				    "   .set    mips3\n\t               \n" \
+				    "   cache   %0, %1                  \n" \
+				    "   .set    pop                 \n" \
+				    :                               \
+				    : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I    0x00
+#else
+#define Hit_Invalidate_I    0x10
+#endif
+#define Hit_Invalidate_D    0x11
+#define CONFIG_SYS_CACHELINE_SIZE   32
+#define Hit_Writeback_Inv_D 0x15
+
+
+void flush_cache(unsigned long start_addr, unsigned long size)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1); 
+	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); 
+
+	while (1) {
+		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(Hit_Invalidate_I, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}   
+}
+
+
 /*@}*/