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体验新版 GitCode,发现更多精彩内容 >>
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557821fd
编写于
10月 19, 2021
作者:
B
BernardXiong
浏览文件
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电子邮件补丁
差异文件
[BSP] update qemu-riscv64-virt for s-mode issue
上级
6b662070
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
40 addition
and
43 deletion
+40
-43
bsp/qemu-riscv-virt64/driver/Kconfig
bsp/qemu-riscv-virt64/driver/Kconfig
+2
-16
bsp/qemu-riscv-virt64/driver/board.c
bsp/qemu-riscv-virt64/driver/board.c
+6
-0
bsp/qemu-riscv-virt64/driver/plic.c
bsp/qemu-riscv-virt64/driver/plic.c
+5
-5
bsp/qemu-riscv-virt64/driver/plic.h
bsp/qemu-riscv-virt64/driver/plic.h
+27
-22
未找到文件。
bsp/qemu-riscv-virt64/driver/Kconfig
浏览文件 @
557821fd
menu "RISCV qemu virt64 configs"
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_TXD_PIN
int "uart1 TXD pin number"
default 20
config BSP_UART1_RXD_PIN
int "uart1 RXD pin number"
default 21
endif
menu "RISC-V QEMU virt64 configs"
config RISCV_S_MODE
bool "RT-Thread run in
riscv smode
"
bool "RT-Thread run in
RISC-V S-Mode(supervisor mode)
"
default y
endmenu
bsp/qemu-riscv-virt64/driver/board.c
浏览文件 @
557821fd
...
...
@@ -68,3 +68,9 @@ void rt_hw_cpu_reset(void)
}
MSH_CMD_EXPORT_ALIAS
(
rt_hw_cpu_reset
,
reboot
,
reset
machine
);
int
rt_sbi_init
(
void
)
{
sbi_init
();
return
0
;
}
INIT_PREV_EXPORT
(
rt_sbi_init
);
bsp/qemu-riscv-virt64/driver/plic.c
浏览文件 @
557821fd
...
...
@@ -35,7 +35,7 @@ void plic_set_priority(int irq, int priority)
*/
void
plic_irq_enable
(
int
irq
)
{
int
hart
=
r_m
hartid
();
int
hart
=
__raw_
hartid
();
*
(
uint32_t
*
)
PLIC_ENABLE
(
hart
)
=
((
*
(
uint32_t
*
)
PLIC_ENABLE
(
hart
))
|
(
1
<<
irq
));
#ifdef RISCV_S_MODE
set_csr
(
sie
,
read_csr
(
sie
)
|
MIP_SEIP
);
...
...
@@ -46,7 +46,7 @@ void plic_irq_enable(int irq)
void
plic_irq_disable
(
int
irq
)
{
int
hart
=
r_m
hartid
();
int
hart
=
__raw_
hartid
();
*
(
uint32_t
*
)
PLIC_ENABLE
(
hart
)
=
(((
*
(
uint32_t
*
)
PLIC_ENABLE
(
hart
))
&
(
~
(
1
<<
irq
))));
}
...
...
@@ -59,7 +59,7 @@ void plic_irq_disable(int irq)
*/
void
plic_set_threshold
(
int
threshold
)
{
int
hart
=
r_m
hartid
();
int
hart
=
__raw_
hartid
();
*
(
uint32_t
*
)
PLIC_THRESHOLD
(
hart
)
=
threshold
;
}
...
...
@@ -77,7 +77,7 @@ void plic_set_threshold(int threshold)
*/
int
plic_claim
(
void
)
{
int
hart
=
r_m
hartid
();
int
hart
=
__raw_
hartid
();
int
irq
=
*
(
uint32_t
*
)
PLIC_CLAIM
(
hart
);
return
irq
;
}
...
...
@@ -94,6 +94,6 @@ int plic_claim(void)
*/
void
plic_complete
(
int
irq
)
{
int
hart
=
r_m
hartid
();
int
hart
=
__raw_
hartid
();
*
(
uint32_t
*
)
PLIC_COMPLETE
(
hart
)
=
irq
;
}
bsp/qemu-riscv-virt64/driver/plic.h
浏览文件 @
557821fd
...
...
@@ -6,48 +6,53 @@
* Change Logs:
* Date Author Notes
* 2021-05-20 bigmagic first version
* 2021-10-20 bernard fix s-mode issue
*/
#ifndef PLIC_H
#define PLIC_H
#include <rtconfig.h>
/*
* This machine puts platform-level interrupt controller (PLIC) here.
* Here only list PLIC registers in Machine mode.
*
*/
#define VIRT_PLIC_BASE 0x0c000000L
#define VIRT_PLIC_BASE 0x0c000000L
#define PLIC_PRIORITY_OFFSET (0x0)
#define PLIC_PENDING_OFFSET (0x1000)
#define PLIC_
PRIORITY_OFFSET (0x0)
#define PLIC_
PENDING_OFFSET (0x1000)
#define PLIC_
ENABLE_STRIDE 0x80
#define PLIC_
CONTEXT_STRIDE 0x1000
#ifndef RISCV_S_MODE
#define PLIC_MENABLE_OFFSET
(0x2000)
#define PLIC_MTHRESHOLD_OFFSET
(0x200000)
#define PLIC_MCLAIM_OFFSET
(0x200004)
#define PLIC_MCOMPLETE_OFFSET
(0x200004)
#define PLIC_MENABLE_OFFSET (0x2000)
#define PLIC_MTHRESHOLD_OFFSET (0x200000)
#define PLIC_MCLAIM_OFFSET (0x200004)
#define PLIC_MCOMPLETE_OFFSET (0x200004)
#define PLIC_ENABLE(hart)
(VIRT_PLIC_BASE + PLIC_MENABLE_OFFSET + (hart) * 0x80
)
#define PLIC_THRESHOLD(hart)
(VIRT_PLIC_BASE + PLIC_MTHRESHOLD_OFFSET + (hart) * 0x1000
)
#define PLIC_CLAIM(hart)
(VIRT_PLIC_BASE + PLIC_MCLAIM_OFFSET + (hart) * 0x1000
)
#define PLIC_COMPLETE(hart)
(VIRT_PLIC_BASE + PLIC_MCOMPLETE_OFFSET + (hart) * 0x1000
)
#define PLIC_ENABLE(hart)
(VIRT_PLIC_BASE + PLIC_MENABLE_OFFSET + (hart * 2) * PLIC_ENABLE_STRIDE
)
#define PLIC_THRESHOLD(hart)
(VIRT_PLIC_BASE + PLIC_MTHRESHOLD_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE
)
#define PLIC_CLAIM(hart)
(VIRT_PLIC_BASE + PLIC_MCLAIM_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE
)
#define PLIC_COMPLETE(hart)
(VIRT_PLIC_BASE + PLIC_MCOMPLETE_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE
)
#else
#define PLIC_SENABLE_OFFSET
(0x2080
)
#define PLIC_STHRESHOLD_OFFSET
(0x201000
)
#define PLIC_SCLAIM_OFFSET
(0x201004
)
#define PLIC_SCOMPLETE_OFFSET
(0x201004
)
#define PLIC_ENABLE(hart)
(VIRT_PLIC_BASE + PLIC_SENABLE_OFFSET + (hart) * 0x80
)
#define PLIC_THRESHOLD(hart)
(VIRT_PLIC_BASE + PLIC_STHRESHOLD_OFFSET + (hart) * 0x1000
)
#define PLIC_CLAIM(hart)
(VIRT_PLIC_BASE + PLIC_SCLAIM_OFFSET + (hart) * 0x1000
)
#define PLIC_COMPLETE(hart)
(VIRT_PLIC_BASE + PLIC_SCOMPLETE_OFFSET + (hart) * 0x1000
)
#define PLIC_SENABLE_OFFSET
(0x2000 + PLIC_ENABLE_STRIDE
)
#define PLIC_STHRESHOLD_OFFSET
(0x200000 + PLIC_CONTEXT_STRIDE
)
#define PLIC_SCLAIM_OFFSET
(0x200004 + PLIC_CONTEXT_STRIDE
)
#define PLIC_SCOMPLETE_OFFSET
(0x200004 + PLIC_CONTEXT_STRIDE
)
#define PLIC_ENABLE(hart)
(VIRT_PLIC_BASE + PLIC_SENABLE_OFFSET + (hart * 2) * PLIC_ENABLE_STRIDE
)
#define PLIC_THRESHOLD(hart)
(VIRT_PLIC_BASE + PLIC_STHRESHOLD_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE
)
#define PLIC_CLAIM(hart)
(VIRT_PLIC_BASE + PLIC_SCLAIM_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE
)
#define PLIC_COMPLETE(hart)
(VIRT_PLIC_BASE + PLIC_SCOMPLETE_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE
)
#endif
#define PLIC_PRIORITY(id) (VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4)
#define PLIC_PENDING(id) (VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32))
#define PLIC_PRIORITY(id)
(VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4)
#define PLIC_PENDING(id)
(VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32))
void
plic_set_priority
(
int
irq
,
int
priority
);
void
plic_irq_enable
(
int
irq
);
...
...
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