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提交 0b13409c 编写于 作者: B BernardXiong
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[BSP] fix compiling issue with libc

上级 3dc820b3
隐藏空白更改
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Showing with 146 addition and 114 deletion
bsp/gd32vf103v-eval/board/board.c
浏览文件 @ 0b13409c
......@@ -8,7 +8,7 @@
* 2019-07-23 tyustli first version
*
*/
#include <stddef.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
......
bsp/gd32vf103v-eval/libraries/SConscript
浏览文件 @ 0b13409c
......@@ -8,7 +8,6 @@ cwd = GetCurrentDir()
src = Glob('GD32VF103_standard_peripheral/Source/*.c')
src += Glob('n22/env_Eclipse/*.c')
src += Glob('n22/stubs/*.c')
src += ['GD32VF103_standard_peripheral/system_gd32vf103.c',
'n22/drivers/n22_func.c',
'n22/env_Eclipse/start.S',
......
bsp/lpc1114/driver/drv_uart.c
浏览文件 @ 0b13409c
......@@ -8,7 +8,7 @@
* 2013-05-18 Bernard The first version for LPC40xx
* 2019-05-05 jg1uaa port to LPC1114
*/
#include <stddef.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
......
bsp/mini2440/drivers/uart.c
浏览文件 @ 0b13409c
/*
* File : uart.c
* Drivers for s3c2440 uarts.
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-09 Jonne Code refactoring for new bsp
*/
#include <stddef.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#define ULCON_OFS 0x00
#define UCON_OFS 0x04
#define UFCON_OFS 0x08
#define UMCON_OFS 0x0c
#define UTRSTAT_OFS 0x10
#define UERSTAT_OFS 0x14
#define UFSTAT_OFS 0x18
#define UMSTAT_OFS 0x1c
#define UTXH_OFS 0x20
#define URXH_OFS 0x24
#define UBRDIV_OFS 0x28
#define ULCON_OFS 0x00
#define UCON_OFS 0x04
#define UFCON_OFS 0x08
#define UMCON_OFS 0x0c
#define UTRSTAT_OFS 0x10
#define UERSTAT_OFS 0x14
#define UFSTAT_OFS 0x18
#define UMSTAT_OFS 0x1c
#define UTXH_OFS 0x20
#define URXH_OFS 0x24
#define UBRDIV_OFS 0x28
#define readl(addr) (*(volatile unsigned long *)(addr))
#define writel(addr, value) (*(volatile unsigned long *)(addr) = value)
#define writel(addr, value) (*(volatile unsigned long *)(addr) = value)
#define PCLK_HZ 50000000
......@@ -33,9 +36,9 @@ struct hw_uart_device
rt_uint32_t irqno;
};
static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct hw_uart_device* uart = serial->parent.user_data;
struct hw_uart_device *uart = serial->parent.user_data;
writel(uart->hw_base + UBRDIV_OFS, PCLK_HZ / (cfg->baud_rate * 16));
......@@ -44,22 +47,22 @@ static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct
writel(uart->hw_base + UFCON_OFS, 0x00);
writel(uart->hw_base + UMCON_OFS, 0x00);
return RT_EOK;
return RT_EOK;
}
static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct hw_uart_device *uart;
struct hw_uart_device *uart;
int mask;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if(uart->irqno == INTUART0)
if (uart->irqno == INTUART0)
{
mask = BIT_SUB_RXD0;
}
else if(uart->irqno == INTUART1)
else if (uart->irqno == INTUART1)
{
mask = BIT_SUB_RXD1;
}
......@@ -73,7 +76,7 @@ static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd,
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
INTSUBMSK |= mask;
break;
case RT_DEVICE_CTRL_SET_INT:
......@@ -86,28 +89,28 @@ static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd,
}
static int s3c2440_putc(struct rt_serial_device *serial, char c)
{
struct hw_uart_device* uart = serial->parent.user_data;
struct hw_uart_device *uart = serial->parent.user_data;
while(!(readl(uart->hw_base + UTRSTAT_OFS) & (1<<2)))
while (!(readl(uart->hw_base + UTRSTAT_OFS) & (1 << 2)))
{
}
writel(uart->hw_base + UTXH_OFS, c);
return 0;
}
static int s3c2440_getc(struct rt_serial_device *serial)
{
struct hw_uart_device* uart = serial->parent.user_data;
struct hw_uart_device *uart = serial->parent.user_data;
int ch = -1;
if(readl(uart->hw_base + UTRSTAT_OFS) & (1<<0))
if (readl(uart->hw_base + UTRSTAT_OFS) & (1 << 0))
{
ch = readl(uart->hw_base + URXH_OFS) & 0x000000FF;
}
return ch;
}
......@@ -116,61 +119,68 @@ static void rt_hw_uart_isr(int irqno, void *param)
struct rt_serial_device *serial = (struct rt_serial_device *)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
/*clear SUBSRCPND*/
if(irqno == INTUART0)
/*clear SUBSRCPND*/
if (irqno == INTUART0)
{
SUBSRCPND = BIT_SUB_RXD0;
}
else if(irqno == INTUART1)
}
else if (irqno == INTUART1)
{
SUBSRCPND = BIT_SUB_RXD1;
}
else
else
{
SUBSRCPND = BIT_SUB_RXD2;
}
}
static struct rt_uart_ops s3c2440_uart_ops = {
.configure = s3c2440_serial_configure,
.control = s3c2440_serial_control,
.putc = s3c2440_putc,
.getc = s3c2440_getc
static struct rt_uart_ops s3c2440_uart_ops =
{
.configure = s3c2440_serial_configure,
.control = s3c2440_serial_control,
.putc = s3c2440_putc,
.getc = s3c2440_getc
};
static struct rt_serial_device _serial0 = {
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
static struct rt_serial_device _serial0 =
{
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
};
static struct hw_uart_device _hwserial0 = {
.hw_base = 0x50000000,
.irqno = INTUART0
static struct hw_uart_device _hwserial0 =
{
.hw_base = 0x50000000,
.irqno = INTUART0
};
static struct rt_serial_device _serial1 = {
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
static struct rt_serial_device _serial1 =
{
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
};
static struct hw_uart_device _hwserial1 = {
.hw_base = 0x50004000,
.irqno = INTUART1
static struct hw_uart_device _hwserial1 =
{
.hw_base = 0x50004000,
.irqno = INTUART1
};
static struct rt_serial_device _serial2 = {
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
static struct rt_serial_device _serial2 =
{
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
};
static struct hw_uart_device _hwserial2 = {
.hw_base = 0x50008000,
.irqno = INTUART2
static struct hw_uart_device _hwserial2 =
{
.hw_base = 0x50008000,
.irqno = INTUART2
};
......@@ -185,7 +195,7 @@ int rt_hw_uart_init(void)
rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial0);
rt_hw_interrupt_install(_hwserial0.irqno, rt_hw_uart_isr, &_serial0, "uart0");
rt_hw_interrupt_umask(INTUART0);
/* register UART1 device */
rt_hw_serial_register(&_serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial1);
rt_hw_interrupt_install(_hwserial1.irqno, rt_hw_uart_isr, &_serial1, "uart1");
......
bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
浏览文件 @ 0b13409c
......@@ -9,9 +9,12 @@
* 2020-10-30 bigmagic first version
*/
#include <rthw.h>
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include <lwip/sys.h>
#include <netif/ethernetif.h>
......@@ -72,12 +75,12 @@ static struct rt_semaphore link_ack;
static inline rt_uint32_t read32(void *addr)
{
return (*((volatile unsigned int*)(addr)));
return (*((volatile unsigned int *)(addr)));
}
static inline void write32(void *addr, rt_uint32_t value)
{
(*((volatile unsigned int*)(addr))) = value;
(*((volatile unsigned int *)(addr))) = value;
}
static void eth_rx_irq(int irq, void *param)
......@@ -380,7 +383,7 @@ static int bcmgenet_gmac_eth_start(void)
/* Update MAC registers based on PHY property */
ret = bcmgenet_adjust_link();
if(ret)
if (ret)
{
rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret);
return ret;
......@@ -416,10 +419,10 @@ static rt_uint32_t prev_recv_cnt = 0;
static rt_uint32_t cur_recv_cnt = 0;
static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
{
void* desc_base;
void *desc_base;
rt_uint32_t length = 0, addr = 0;
rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX);
if(prod_index == index_flag)
if (prod_index == index_flag)
{
cur_recv_cnt = index_flag;
index_flag = 0x7fffffff;
......@@ -428,7 +431,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
}
else
{
if(prev_recv_cnt == prod_index & 0xffff)
if (prev_recv_cnt == (prod_index & 0xffff))
{
return 0;
}
......@@ -437,15 +440,16 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
length = read32(desc_base + DMA_DESC_LENGTH_STATUS);
length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
addr = read32(desc_base + DMA_DESC_ADDRESS_LO);
/* To cater for the IP headepr alignment the hardware does.
* This would actually not be needed if we don't program
* RBUF_ALIGN_2B
*/
rt_hw_cpu_dcache_invalidate(addr,length);
* This would actually not be needed if we don't program
* RBUF_ALIGN_2B
*/
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *) addr, length);
*packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET);
rx_index = rx_index + 1;
if(rx_index >= RX_DESCS)
if (rx_index >= RX_DESCS)
{
rx_index = 0;
}
......@@ -453,7 +457,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
cur_recv_cnt = cur_recv_cnt + 1;
if(cur_recv_cnt > 0xffff)
if (cur_recv_cnt > 0xffff)
{
cur_recv_cnt = 0;
}
......@@ -468,16 +472,16 @@ static int bcmgenet_gmac_eth_send(void *packet, int length)
void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
rt_uint32_t prod_index, cons;
rt_uint32_t tries = 100;
rt_uint32_t prod_index;
prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
rt_hw_cpu_dcache_clean((void*)packet, length);
write32((desc_base + DMA_DESC_ADDRESS_LO), packet);
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)packet, length);
write32((desc_base + DMA_DESC_ADDRESS_LO), (rt_uint32_t)packet);
write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);
......@@ -631,7 +635,7 @@ struct pbuf *rt_eth_rx(rt_device_t device)
if (recv_len > 0)
{
pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
if(pbuf)
if (pbuf)
{
rt_memcpy(pbuf->payload, addr_point, recv_len);
}
......
bsp/raspberry-pi/raspi4-32/driver/mbox.h
浏览文件 @ 0b13409c
......@@ -12,6 +12,7 @@
#define __MBOX_H__
#include <rtthread.h>
#include "board.h"
//https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
//https://github.com/hermanhermitage/videocoreiv
......
bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h
浏览文件 @ 0b13409c
......@@ -11,6 +11,7 @@
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include <stdint.h>
#include<rtdevice.h>
#include<rthw.h>
......
bsp/tm4c123bsp/libraries/Drivers/drv_spi.h
浏览文件 @ 0b13409c
......@@ -11,6 +11,7 @@
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <stdint.h>
#include <rtdevice.h>
#include <rthw.h>
#include "drivers/spi.h"
......
components/drivers/include/drivers/pm.h
浏览文件 @ 0b13409c
......@@ -15,6 +15,7 @@
#ifndef __PM_H__
#define __PM_H__
#include <stdint.h>
#include <rtthread.h>
#ifndef PM_HAS_CUSTOM_CONFIG
......
components/drivers/phy/phy.c
浏览文件 @ 0b13409c
......@@ -8,7 +8,7 @@
* Date Author Notes
* 2020-09-27 wangqiang first version
*/
#include <stddef.h>
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
......
components/net/netdev/src/netdev.c
浏览文件 @ 0b13409c
......@@ -10,6 +10,7 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <rtthread.h>
#include <rthw.h>
......
libcpu/arm/zynqmp-r5/cache.c
浏览文件 @ 0b13409c
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006 - 2021, RT-Thread Development Team
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2021 WangHuachen. All rights reserved.
* SPDX-License-Identifier: MIT
......@@ -9,6 +9,8 @@
* 2020-03-19 WangHuachen first version
* 2021-05-10 WangHuachen add more functions
*/
#include <stdint.h>
#include <rthw.h>
#include <rtdef.h>
......@@ -69,9 +71,10 @@ void Xil_DCacheEnable(void)
#if defined (__GNUC__)
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) == 0x00000000U)
{
/* invalidate the Data cache */
Xil_DCacheInvalidate();
......@@ -93,7 +96,7 @@ void Xil_DCacheDisable(void)
#if defined (__GNUC__)
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
......@@ -126,7 +129,7 @@ void Xil_DCacheInvalidateLine(INTPTR adr)
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
/* Wait for invalidate to complete */
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
......@@ -143,29 +146,33 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
if (len != 0U)
{
end = tempadr + len;
tempend = end;
/* Select L1 Data cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
if ((tempadr & (cacheline-1U)) != 0U) {
if ((tempadr & (cacheline - 1U)) != 0U)
{
tempadr &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempadr);
}
if ((tempend & (cacheline-1U)) != 0U) {
if ((tempend & (cacheline - 1U)) != 0U)
{
tempend &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempend);
}
while (tempadr < tempend) {
while (tempadr < tempend)
{
/* Invalidate Data cache line */
asm_inval_dc_line_mva_poc(tempadr);
/* Invalidate Data cache line */
asm_inval_dc_line_mva_poc(tempadr);
tempadr += cacheline;
tempadr += cacheline;
}
}
......@@ -189,7 +196,7 @@ void Xil_DCacheFlush(void)
#if defined (__GNUC__)
CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg);
mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
#endif
/* Determine Cache Size */
......@@ -204,15 +211,17 @@ void Xil_DCacheFlush(void)
/* Get the cacheline size, way size, index size from csidr */
LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
NumSet = CacheSize/NumWays;
NumSet = CacheSize / NumWays;
NumSet /= (0x00000001U << LineSize);
Way = 0U;
Set = 0U;
/* Invalidate all the cachelines */
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++)
{
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++)
{
C7Reg = Way | Set;
/* Flush by Set/Way */
asm_clean_inval_dc_line_sw(C7Reg);
......@@ -241,7 +250,7 @@ void Xil_DCacheFlushLine(INTPTR adr)
mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
/* Wait for flush to complete */
/* Wait for flush to complete */
dsb();
mtcpsr(currmask);
}
......@@ -256,14 +265,16 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0x00000000U) {
if (len != 0x00000000U)
{
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
LocalAddr &= ~(cacheline - 1U);
while (LocalAddr < end) {
while (LocalAddr < end)
{
/* Flush Data cache line */
asm_clean_inval_dc_line_mva_poc(LocalAddr);
......@@ -301,7 +312,8 @@ void Xil_ICacheEnable(void)
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) == 0x00000000U)
{
/* invalidate the instruction cache */
mtcp(XREG_CP15_INVAL_IC_POU, 0);
......@@ -321,11 +333,11 @@ void Xil_ICacheDisable(void)
/* invalidate the instruction cache */
mtcp(XREG_CP15_INVAL_IC_POU, 0);
/* disable the instruction cache */
/* disable the instruction cache */
#if defined (__GNUC__)
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
......@@ -360,7 +372,7 @@ void Xil_ICacheInvalidateLine(INTPTR adr)
mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
/* Wait for invalidate to complete */
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}
......@@ -374,7 +386,8 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0x00000000U) {
if (len != 0x00000000U)
{
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
......@@ -384,7 +397,8 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
/* Select cache L0 I-cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
while (LocalAddr < end) {
while (LocalAddr < end)
{
/* Invalidate L1 I-cache line */
asm_inval_ic_line_mva_pou(LocalAddr);
......@@ -418,7 +432,7 @@ rt_base_t rt_hw_cpu_icache_status(void)
#if defined (__GNUC__)
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
return CtrlReg & XREG_CP15_CONTROL_I_BIT;
}
......@@ -429,7 +443,7 @@ rt_base_t rt_hw_cpu_dcache_status(void)
#if defined (__GNUC__)
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
return CtrlReg & XREG_CP15_CONTROL_C_BIT;
}
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