提交 088990f7 编写于 作者: wuyangyong's avatar wuyangyong

update enc28j60 driver: ensure enable PHY link changed interrupt.

上级 3ec384d8
...@@ -321,6 +321,8 @@ static rt_err_t enc28j60_init(rt_device_t dev) ...@@ -321,6 +321,8 @@ static rt_err_t enc28j60_init(rt_device_t dev)
enc28j60_phy_write(spi_device, PHCON1, PHCON1_PDPXMD); // full duplex enc28j60_phy_write(spi_device, PHCON1, PHCON1_PDPXMD); // full duplex
// no loopback of transmitted frames // no loopback of transmitted frames
enc28j60_phy_write(spi_device, PHCON2, PHCON2_HDLDIS); enc28j60_phy_write(spi_device, PHCON2, PHCON2_HDLDIS);
/* enable PHY link changed interrupt. */
enc28j60_phy_write(spi_device, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
enc28j60_set_bank(spi_device, ECON2); enc28j60_set_bank(spi_device, ECON2);
spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC); spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC);
......
...@@ -221,6 +221,12 @@ ...@@ -221,6 +221,12 @@
#define PHCON2_TXDIS 0x2000 #define PHCON2_TXDIS 0x2000
#define PHCON2_JABBER 0x0400 #define PHCON2_JABBER 0x0400
#define PHCON2_HDLDIS 0x0100 #define PHCON2_HDLDIS 0x0100
/* ENC28J60 PHY PHIE Register Bit Definitions */
#define PHIE_PLNKIE (1 << 4)
#define PHIE_PGEIE (1 << 1)
/* ENC28J60 PHY PHIR Register Bit Definitions */
#define PHIR_PLNKIF (1 << 4)
#define PHIR_PGEIF (1 << 1)
// ENC28J60 Packet Control Byte Bit Definitions // ENC28J60 Packet Control Byte Bit Definitions
#define PKTCTRL_PHUGEEN 0x08 #define PKTCTRL_PHUGEEN 0x08
......
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