- 05 8月, 2010 7 次提交
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由 Changhwan Youn 提交于
This patch adds the Kconfig and Makefile for the new S5PV310 SoC. It also updates arch/arm Kconfig, Makefile and arch/arm/mm/Kconfig to include support for the new S5PV310. Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Changhwan Youn 提交于
This patch adds timer support for S5PV310. Until now, all S5P SoCs use CONFIG_ARCH_USES_GETTIMEOFFSET macro as a default configuration. Instead,S5PV310 implements clocksource and clock_event_device to support the high resolution timer and tickless system. Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NHyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Changhwan Youn 提交于
This patch adds IRQ support for S5PV310. ARM GIC is installed in S5PV310 instead of VIC which is in every other CPUs in S5P series. Several irq combiners are used to resolve the lack of irq lines in current implementation. Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NHyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Changhwan Youn 提交于
This patch adds clock and pll support for S5PV310. Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NJongpill Lee <boyko.lee@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Changhwan Youn 提交于
This patch adds Samsung S5PV310/S5PC210 CPU support. The S5PV310/S5PC210 integrates a ARM Cortex A9 multi-core. Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NJongpill Lee <boyko.lee@samsung.com> Signed-off-by: NJiseong Oh <jiseong.oh@samsung.com> [kgene.kim@samsung.com: fix build errors] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Changhwan Youn 提交于
The uart offset between channels has been 0x400 for all S5P series and to present virtual and physical offsets, both number 0x400 and S3C_UART_OFFSET have been used together. This patch removes the use of the number 0x400 and expands the virtual mapping size of S3C_VA_UART from 4KB to 512KB to support the CPU with S3C_UART_OFFSET being 0x10000. Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jongpill Lee 提交于
Add support for the FRACVAL register on the newer UART blocks which provides the same function as UDIVSLOT register but the FRACVAL is easier to implement. To support UDIVSLOT register, UDIVSLOT table search is necessary though supporting FRACVAL only needs the index value of UDIVSLOT table. Signed-off-by: NJongpill Lee <boyko.lee@samsung.com> Acked-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 31 7月, 2010 3 次提交
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由 Julia Lawall 提交于
__sa1111_remove always frees its argument, so the subsequent reference to sachip->saved_state represents a use after free. __sa1111_remove does not appear to use the saved_state field, so the patch simply frees it first. A simplified version of the semantic patch that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression E,E2; @@ __sa1111_remove(E) ... ( E = E2 | * E ) // </smpl> Signed-off-by: NJulia Lawall <julia@diku.dk> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
The MMC card detection sense has become really confused with negations at various levels, leading to some platforms not detecting inserted cards. Fix this by converting everything to positive logic throughout, thereby getting rid of these negations. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Gary King 提交于
smp_processor_id() must not be called from a preemptible context (this is checked by CONFIG_DEBUG_PREEMPT). kmap_high_l1_vipt() was doing so. This lead to a problem where the wrong per_cpu kmap_high_l1_vipt_depth could be incremented, causing a BUG_ON(*depth <= 0); in kunmap_high_l1_vipt(). The solution is to move the call to smp_processor_id() after the call to preempt_disable(). Originally by: Andrew Howe <ahowe@nvidia.com> Signed-off-by: NGary King <gking@nvidia.com> Acked-by: NNicolas Pitre <nico.as.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 29 7月, 2010 6 次提交
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由 Russell King 提交于
The ioread/iowrite accessors also need barriers as they're used in place of readl/writel et.al. in portable drivers. Create __iormb() and __iowmb() which are conditionally defined to be barriers dependent on ARM_DMA_MEM_BUFFERABLE, and always use these macros in the accessors. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
When the coherent DMA buffers are mapped as Normal Non-cacheable (ARM_DMA_MEM_BUFFERABLE enabled), buffer accesses are no longer ordered with Device memory accesses causing failures in device drivers that do not use the mandatory memory barriers before starting a DMA transfer. LKML discussions led to the conclusion that such barriers have to be added to the I/O accessors: http://thread.gmane.org/gmane.linux.kernel/683509/focus=686153 http://thread.gmane.org/gmane.linux.ide/46414 http://thread.gmane.org/gmane.linux.kernel.cross-arch/5250 This patch introduces a wmb() barrier to the write*() I/O accessors to handle the situations where Normal Non-cacheable writes are still in the processor (or L2 cache controller) write buffer before a DMA transfer command is issued. For the read*() accessors, a rmb() is introduced after the I/O to avoid speculative loads where the driver polls for a DMA transfer ready bit. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
This patch is in preparation for a subsequent patch which adds barriers to the I/O accessors. Since the mandatory barriers may do an L2 cache sync, this patch avoids a recursive call into l2x0_cache_sync() via the write*() accessors and wmb() and a call into l2x0_cache_sync() with the l2x0_lock held. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
This patch introduces readl*_relaxed()/write*_relaxed() as the main I/O accessors (when __mem_pci is defined). The standard read*()/write*() macros are now based on the relaxed accessors. This patch is in preparation for a subsequent patch which adds barriers to the I/O accessors. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Rabin Vincent 提交于
Don't use writeb() in uncompress.h, to avoid the following build errors when the "Add barriers to the I/O accessors" series is applied. Use __raw_writeb() instead. arch/arm/boot/compressed/misc.o: In function `putc': arch/arm/mach-ux500/include/mach/uncompress.h:41: undefined reference to `outer_cache' Acked-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NRabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Magnus Damm 提交于
Update the compressed boot Makefile for ARM to remove files during clean. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 7月, 2010 1 次提交
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由 Sekhar Nori 提交于
Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD voltage. Pass the right platform data to the TPS6507x driver so it can operate on the DEFDCDC{2,3}_HIGH register to read and change voltage levels. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NLiam Girdwood <lrg@slimlogic.co.uk>
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- 26 7月, 2010 9 次提交
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由 Dmitry Torokhov 提交于
Commit 3fea6026 ("Input: twl40300-keypad - fix handling of "all ground" rows") broke compilation as I managed to use non-existent keycodes. Reported-by: NArjan van de Ven <arjan@infradead.org> Signed-off-by: NDmitry Torokhov <dtor@mail.ru> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Russell King 提交于
Using the parent functions frame pointer to access our arguments is completely wrong, whether or not we're building with frame pointers or not. What we should be using is the stack pointer to get at the word above the registers we stacked ourselves. Reported-by: NBosko Radivojevic <bosko.radivojevic@gmail.com> Tested-by: NBosko Radivojevic <bosko.radivojevic@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Uwe Kleine-König 提交于
qnap_tsx1x_register_flash is only called by qnap_ts219_init and qnap_ts41x_init which both live in .init.text, too. So the move is OK. This fixes the following warning in kirkwood_defconfig: WARNING: vmlinux.o(.text+0x9334): Section mismatch in reference from the function qnap_tsx1x_register_flash() to the variable .init.data:qnap_tsx1x_spi_slave_info The function qnap_tsx1x_register_flash() references the variable __initdata qnap_tsx1x_spi_slave_info. This is often because qnap_tsx1x_register_flash lacks a __initdata annotation or the annotation of qnap_tsx1x_spi_slave_info is wrong. Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: NNicolas Pitre <nico@fluxnic.net> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Uwe Kleine-König 提交于
the different putc variants used an initialized local static variable which is broken since 5de813b6 (ARM: Eliminate decompressor -Dstatic= PIC hack) This needs to be initialized at runtime and so needs to be global. While at it give it a better name. Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jeremy Kerr 提交于
We need mach/hardware.h for CLPS7111_VIRT_BASE. Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jeremy Kerr 提交于
We need a waituart macro. Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jeremy Kerr 提交于
mov rx, =<immediate> isn't valid, use #<immediate> instead. Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jeremy Kerr 提交于
We need asm/memory.h for NS9XXX_CSxSTAT_PHYS (via mach/memory.h). Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jeremy Kerr 提交于
IO_BASE shoule be IO_VIRT, and IO_START should be IO_PHYS. We also need mach/hardware.h for these definitions. Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 7月, 2010 2 次提交
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由 wanzongshun 提交于
Delete a wrong redundant right parenthesis in arch/arm/mach-footbridge/common.c Signed-off-by: NWan ZongShun <mcuos.com@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 wanzongshun 提交于
This patch is to fix nuc900 touchscreen clk definition bug,the .dev_id's name should be 'nuc900-ts', it should be the same to pdev.name. or else, the touchscreen driver will be not working well due to clock engine disabled. Signed-off-by: NWan ZongShun <mcuos.com@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 7月, 2010 1 次提交
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由 Dmitry Torokhov 提交于
The Nokia RX51 board code (arch/arm/mach-omap2/board-rx51-peripherals.c) defines a key map for the matrix keypad keyboard. The hardware seems to use all of the 8 rows and 8 columns of the keypad, although not all possible locations are used. The TWL4030 supports keypads with at most 8 rows and 8 columns. Most keys are defined with a row and column number between 0 and 7, except KEY(0xff, 2, KEY_F9), KEY(0xff, 4, KEY_F10), KEY(0xff, 5, KEY_F11), which represent keycodes that should be emitted when entire row is connected to the ground. since the driver handles this case as if we had an extra column in the key matrix. Unfortunately we do not allocate enough space and end up owerwriting some random memory. Reported-and-tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: stable@kernel.org Signed-off-by: NDmitry Torokhov <dtor@mail.ru>
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- 15 7月, 2010 1 次提交
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由 Nicolas Pitre 提交于
From: Bin Yang <bin.yang@marvell.com> Cc: stable@kernel.org Signed-off-by: NBin Yang <bin.yang@marvell.com> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 13 7月, 2010 5 次提交
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由 pieterg 提交于
The wrong CONFIG defines were checked, and the <mach/audio.h> include was missing Signed-off-by: Npieter <p.grimmerink@inepro.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Acked-by: NDaniel Mack <daniel@caiaq.de> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Eric Miao 提交于
Reported-by: NDylan Cristiani <d.cristiani@idem-tech.it> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Marek Vasut 提交于
This patch: 1) Simpifies the DRI recomputation routine by pulling out the common code 2) Fixes a bug in PXA27x DRI recomputation caused by incorrect parenthesis Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Eric Miao 提交于
Reported-by: NAndrea Adami <andrea.adami@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 10 7月, 2010 1 次提交
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由 Russell King 提交于
CPU: Testing write buffer coherency: ok ------------[ cut here ]------------ WARNING: at kernel/lockdep.c:3145 check_flags+0xcc/0x1dc() Modules linked in: [<c0035120>] (unwind_backtrace+0x0/0xf8) from [<c0355374>] (dump_stack+0x20/0x24) [<c0355374>] (dump_stack+0x20/0x24) from [<c0060c04>] (warn_slowpath_common+0x58/0x70) [<c0060c04>] (warn_slowpath_common+0x58/0x70) from [<c0060c3c>] (warn_slowpath_null+0x20/0x24) [<c0060c3c>] (warn_slowpath_null+0x20/0x24) from [<c008f224>] (check_flags+0xcc/0x1dc) [<c008f224>] (check_flags+0xcc/0x1dc) from [<c00945dc>] (lock_acquire+0x50/0x140) [<c00945dc>] (lock_acquire+0x50/0x140) from [<c0358434>] (_raw_spin_lock+0x50/0x88) [<c0358434>] (_raw_spin_lock+0x50/0x88) from [<c00fd114>] (set_task_comm+0x2c/0x60) [<c00fd114>] (set_task_comm+0x2c/0x60) from [<c007e184>] (kthreadd+0x30/0x108) [<c007e184>] (kthreadd+0x30/0x108) from [<c0030104>] (kernel_thread_exit+0x0/0x8) ---[ end trace 1b75b31a2719ed1c ]--- possible reason: unannotated irqs-on. irq event stamp: 3 hardirqs last enabled at (2): [<c0059bb0>] finish_task_switch+0x48/0xb0 hardirqs last disabled at (3): [<c002f0b0>] ret_slow_syscall+0xc/0x1c softirqs last enabled at (0): [<c005f3e0>] copy_process+0x394/0xe5c softirqs last disabled at (0): [<(null)>] (null) Fix this by ensuring that the lockdep interrupt state is manipulated in the appropriate places. We essentially treat userspace as an entirely separate environment which isn't relevant to lockdep (lockdep doesn't monitor userspace.) We don't tell lockdep that IRQs will be enabled in that environment. Instead, when creating kernel threads (which is a rare event compared to entering/leaving userspace) we have to update the lockdep state. Do this by starting threads with IRQs disabled, and in the kthread helper, tell lockdep that IRQs are enabled, and enable them. This provides lockdep with a consistent view of the current IRQ state in kernel space. This also revert portions of 0d928b0b which didn't fix the problem. Tested-by: NMing Lei <tom.leiming@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 7月, 2010 4 次提交
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由 Linus Walleij 提交于
The MTU wallclock timing fix-up patch was hardwired to the DB8500 causing a regression. This makes it work on the DB5500 as well. Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
Currently, the 32-bit and 64-bit atomic operations on ARM do not include memory constraints in the inline assembly blocks. In the case of barrier-less operations [for example, atomic_add], this means that the compiler may constant fold values which have actually been modified by a call to an atomic operation. This issue can be observed in the atomic64_test routine in <kernel root>/lib/atomic64_test.c: 00000000 <test_atomic64>: 0: e1a0c00d mov ip, sp 4: e92dd830 push {r4, r5, fp, ip, lr, pc} 8: e24cb004 sub fp, ip, #4 c: e24dd008 sub sp, sp, #8 10: e24b3014 sub r3, fp, #20 14: e30d000d movw r0, #53261 ; 0xd00d 18: e3011337 movw r1, #4919 ; 0x1337 1c: e34c0001 movt r0, #49153 ; 0xc001 20: e34a1aa3 movt r1, #43683 ; 0xaaa3 24: e16300f8 strd r0, [r3, #-8]! 28: e30c0afe movw r0, #51966 ; 0xcafe 2c: e30b1eef movw r1, #48879 ; 0xbeef 30: e34d0eaf movt r0, #57007 ; 0xdeaf 34: e34d1ead movt r1, #57005 ; 0xdead 38: e1b34f9f ldrexd r4, [r3] 3c: e1a34f90 strexd r4, r0, [r3] 40: e3340000 teq r4, #0 44: 1afffffb bne 38 <test_atomic64+0x38> 48: e59f0004 ldr r0, [pc, #4] ; 54 <test_atomic64+0x54> 4c: e3a0101e mov r1, #30 50: ebfffffe bl 0 <__bug> 54: 00000000 .word 0x00000000 The atomic64_set (0x38-0x44) writes to the atomic64_t, but the compiler doesn't see this, assumes the test condition is always false and generates an unconditional branch to __bug. The rest of the test is optimised away. This patch adds suitable memory constraints to the atomic operations on ARM to ensure that the compiler is informed of the correct data hazards. We have to use the "Qo" constraints to avoid hitting the GCC anomaly described at http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44492 , where the compiler makes assumptions about the writeback in the addressing mode used by the inline assembly. These constraints forbid the use of auto{inc,dec} addressing modes, so it doesn't matter if we don't use the operand exactly once. Cc: stable@kernel.org Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The atomic64_add_unless function compares an atomic variable with a given value and, if they are not equal, adds another given value to the atomic variable. The function returns zero if the addition did not occur and non-zero otherwise. On ARM, the return value is initialised to 1 in C code. Inline assembly code then performs the atomic64_add_unless operation, setting the return value to 0 iff the addition does not occur. This means that when the addition *does* occur, the value of ret must be preserved across the inline assembly and therefore requires a "+r" constraint rather than the current one of "=&r". Thanks to Nicolas Pitre for helping to spot this. Cc: stable@kernel.org Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Sascha Hauer 提交于
On i.MX35 the L2X0_AUX_CTRL register does not have sensible reset default values. Allow them to be overwritten with the aux_val/aux_mask arguments passed to l2x0_init(). Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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