1. 19 10月, 2015 37 次提交
  2. 12 10月, 2015 1 次提交
    • S
      clk: imx6: Add SPDIF_GCLK clock in clock tree · 84a87250
      Shengjiu Wang 提交于
      Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
      one clock of SPDIF, which is missed before.
      
      We found an issue that imx can't enter low power mode with spdif
      if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
      spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
      clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
      so its parent clock (PLL clock) is prepared, the prepare operation of
      PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
      then it can enter low power mode.
      
      So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
      core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
      SPDIF_GCLK's parent clock is ipg clock.
      Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com>
      Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      84a87250
  3. 09 10月, 2015 1 次提交
  4. 30 9月, 2015 1 次提交