- 19 4月, 2008 3 次提交
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由 Catalin Marinas 提交于
This patch changes the CPU_V7 configuration dependency to allow MACH_REALVIEW_EB. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Paul Brook 提交于
This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: NPaul Brook <paul@codesourcery.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
This patch adds the detection and handling of the ThumbEE extension on ARMv7 CPUs. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 26 1月, 2008 4 次提交
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由 Tzachi Perelstein 提交于
This enables the usage of some old Feroceon cores for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and old Feroceon-2850. Signed-off-by: NTzachi Perelstein <tzachi@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Assaf Hoffman 提交于
The Feroceon is a family of independent ARMv5TE compliant CPU core implementations, supporting a variable depth pipeline and out-of-order execution. The Feroceon is configurable with VFP support, and the later models in the series are superscalar with up to two instructions per clock cycle. This patch adds the initial low-level cache/TLB handling for this core. Signed-off-by: NAssaf Hoffman <hoffman@marvell.com> Reviewed-by: NTzachi Perelstein <tzachi@marvell.com> Reviewed-by: NNicolas Pitre <nico@marvell.com> Reviewed-by: NLennert Buytenhek <buytenh@marvell.com> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Andrew Victor 提交于
Add support for Atmel's AT91CAP9 Customizable Microcontroller family. <http://www.atmel.com/products/AT91CAP/Default.asp> Signed-off-by: NStelian Pop <stelian@popies.net> Signed-off-by: NAndrew Victor <linux@maxim.org.za> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Brian Swetland 提交于
- core header files for arch-msm - Kconfig and Makefiles to enable ARCH_MSM7X00A builds - MSM7X00A specific arch_idle - peripheral iomap and irq number definitions Signed-off-by: NBrian Swetland <swetland@google.com>
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- 16 10月, 2007 1 次提交
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由 eric miao 提交于
Signed-off-by: Neric miao <eric.y.miao@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 13 10月, 2007 1 次提交
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由 Russell King 提交于
PXA3 SoCs are supported by the Xscale3 CPU code rather than the Xscale CPU code. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 7月, 2007 1 次提交
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由 Quinn Jensen 提交于
This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: NQuinn Jensen <quinn.jensen@freescale.com> Acked-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 7月, 2007 5 次提交
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由 Catalin Marinas 提交于
Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
With this patch, Kconfig only selects CPU_HAS_ASID for the MMU case. It also corrects the typo in the v6wbi_tlb_fns definition in pgtable-nommu.h. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
If not MMU and not v6K, access to the TLS register has to be emulated. MMU-less systems do not provide a high page for kuser helpers. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 30 5月, 2007 1 次提交
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由 Catalin Marinas 提交于
We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 5月, 2007 1 次提交
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由 Russell King 提交于
Presently, we check for the minimum ARM architecture that we're building for to determine whether we need ASID support. This is wrong - if we're going to support a range of CPUs which include ARMv6 or higher, we need the ASID. Convert the checks to use a new configuration symbol, and arrange for ARMv6 and higher CPU entries to select it. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 12 5月, 2007 3 次提交
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由 Andrew Victor 提交于
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: NAndrew Victor <andrew@sanpeople.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Andrew Victor 提交于
Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: NNicolas Ferre <nicolas.ferre@rfo.atmel.com> Signed-off-by: NAndrew Victor <andrew@sanpeople.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Kevin Hilman 提交于
Add base kernel support for the TI DaVinci platform. This patch only includes interrupts, timers, CPU identification, serial support and basic power and sleep controller init. More drivers to come. Signed-off-by: NKevin Hilman <khilman@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 5月, 2007 1 次提交
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由 Catalin Marinas 提交于
This patch adds the necessary lines to the Makefile and Kconfig files for enabling the compilation of the ARMv7 CPU support. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 2月, 2007 2 次提交
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由 Uwe Kleine-König 提交于
Signed-off-by: NUwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Robert P. J. Day 提交于
Replace the very few remaining "depends" Kconfig directives with "depends on". Signed-off-by: NRobert P. J. Day <rpjday@mindspring.com> Signed-off-by: NAdrian Bunk <bunk@stusta.de>
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- 12 2月, 2007 1 次提交
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由 Catalin Marinas 提交于
This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 08 2月, 2007 2 次提交
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由 Andrew Victor 提交于
Add support for the Atmel AT91SAM9263 processor. It is similar to the AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc. Original patch from Nicolas Ferre. Signed-off-by: NAndrew Victor <andrew@sanpeople.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 08 12月, 2006 1 次提交
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由 Dan Williams 提交于
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: NDan Williams <dan.j.williams@intel.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 02 12月, 2006 1 次提交
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由 Dan Williams 提交于
Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause crashes, see erratum #42. Cc: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 30 11月, 2006 1 次提交
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由 Matt LaPlante 提交于
Fix various Kconfig typos. Signed-off-by: NMatt LaPlante <kernel1@cyberdogtech.com> Acked-by: NRandy Dunlap <randy.dunlap@oracle.com> Signed-off-by: NAdrian Bunk <bunk@stusta.de>
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- 29 9月, 2006 2 次提交
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由 Hyok S. Choi 提交于
In nommu mode, the exception vector location depends on the platforms. Some of the implementations may have some special exception control forwarding method in their ROM/flash and for some of them has its own re-mapping mechanism by the h/w. This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default. This feature depends on CP15 and does not supported by ARM740. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a dummy abort handler which returns zero for the base restored Data Abort model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up for the base updated Data Abort model cores. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 9月, 2006 8 次提交
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由 Russell King 提交于
Don't offer non-MMU based CPUs for selection when CONFIG_MMU is set. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM946E-S core support which has typically 8KB I&D cache. It has a MPU and supports ARMv5TE instruction set. Because the ARM946E-S core can be synthesizable with various cache size, CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache and a MPU. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM9TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM7TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
By merging of uClinux/ARM, we need to treat various CPU cores which have MMU, MPU or even none for memory management. The memory management coprocessors are controlled by CP15 register set and the ARM core family can be categorized by 5 groups by the register ; G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022, v6 and the derivations sa1100, sa110, xscale, xsc3. G-b. CP15 is MPU : 740, 940, 946, 996, 1156. G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design) G-d. CP15 is exist, but nothing for memory managemnt : 966, 968. G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the family can be defined as : - CPU_CP15 only : G-d - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable) - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable) - !CPU_CP15 : G-e Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 25 9月, 2006 1 次提交
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由 Lennert Buytenhek 提交于
Split the iop3xx mach type into iop32x and iop33x -- split the config symbols, and move the code in the mach-iop3xx directory to the mach-iop32x and mach-iop33x directories. Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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