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提交 d0a9af80 编写于 作者: L Linus Torvalds
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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6 

* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6:
  [VIDEO]: Fix section mismatch in cg3.c
  [SPARC]: sparc64 gcc-4.2.0 20070317 -Werror failure
  [VIDEO] ffb: Fix two DAC handling bugs.
  [SPARC32]: Fix SMP build regression
  [DRM]: Delete sparc64 FFB driver code that never gets built.
上级 c203b33d a7177514
隐藏空白更改
内联 并排
Showing with 77 addition and 1319 deletion
arch/sparc/lib/atomic32.c
浏览文件 @ d0a9af80
......@@ -52,6 +52,7 @@ int atomic_cmpxchg(atomic_t *v, int old, int new)
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
return ret;
}
EXPORT_SYMBOL(atomic_cmpxchg);
int atomic_add_unless(atomic_t *v, int a, int u)
{
......@@ -65,6 +66,7 @@ int atomic_add_unless(atomic_t *v, int a, int u)
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
return ret != u;
}
EXPORT_SYMBOL(atomic_add_unless);
/* Atomic operations are already serializing */
void atomic_set(atomic_t *v, int i)
......
drivers/char/drm/Makefile
浏览文件 @ d0a9af80
......@@ -15,7 +15,6 @@ i810-objs := i810_drv.o i810_dma.o
i830-objs := i830_drv.o i830_dma.o i830_irq.o
i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o
radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
ffb-objs := ffb_drv.o ffb_context.o
sis-objs := sis_drv.o sis_mm.o
savage-objs := savage_drv.o savage_bci.o savage_state.o
via-objs := via_irq.o via_drv.o via_map.o via_mm.o via_dma.o via_verifier.o via_video.o via_dmablit.o
......@@ -36,7 +35,6 @@ obj-$(CONFIG_DRM_MGA) += mga.o
obj-$(CONFIG_DRM_I810) += i810.o
obj-$(CONFIG_DRM_I830) += i830.o
obj-$(CONFIG_DRM_I915) += i915.o
obj-$(CONFIG_DRM_FFB) += ffb.o
obj-$(CONFIG_DRM_SIS) += sis.o
obj-$(CONFIG_DRM_SAVAGE)+= savage.o
obj-$(CONFIG_DRM_VIA) +=via.o
......
drivers/char/drm/ffb_context.c 已删除 100644 → 0
浏览文件 @ c203b33d
/* $Id: ffb_context.c,v 1.5 2001/08/09 17:47:51 davem Exp $
* ffb_context.c: Creator/Creator3D DRI/DRM context switching.
*
* Copyright (C) 2000 David S. Miller (davem@redhat.com)
*
* Almost entirely stolen from tdfx_context.c, see there
* for authors.
*/
#include <asm/upa.h>
#include "ffb.h"
#include "drmP.h"
#include "ffb_drv.h"
static int DRM(alloc_queue) (drm_device_t * dev, int is_2d_only) {
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
int i;
for (i = 0; i < FFB_MAX_CTXS; i++) {
if (fpriv->hw_state[i] == NULL)
break;
}
if (i == FFB_MAX_CTXS)
return -1;
fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL);
if (fpriv->hw_state[i] == NULL)
return -1;
fpriv->hw_state[i]->is_2d_only = is_2d_only;
/* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */
return i + 1;
}
static void ffb_save_context(ffb_dev_priv_t * fpriv, int idx)
{
ffb_fbcPtr ffb = fpriv->regs;
struct ffb_hw_context *ctx;
int i;
ctx = fpriv->hw_state[idx - 1];
if (idx == 0 || ctx == NULL)
return;
if (ctx->is_2d_only) {
/* 2D applications only care about certain pieces
* of state.
*/
ctx->drawop = upa_readl(&ffb->drawop);
ctx->ppc = upa_readl(&ffb->ppc);
ctx->wid = upa_readl(&ffb->wid);
ctx->fg = upa_readl(&ffb->fg);
ctx->bg = upa_readl(&ffb->bg);
ctx->xclip = upa_readl(&ffb->xclip);
ctx->fbc = upa_readl(&ffb->fbc);
ctx->rop = upa_readl(&ffb->rop);
ctx->cmp = upa_readl(&ffb->cmp);
ctx->matchab = upa_readl(&ffb->matchab);
ctx->magnab = upa_readl(&ffb->magnab);
ctx->pmask = upa_readl(&ffb->pmask);
ctx->xpmask = upa_readl(&ffb->xpmask);
ctx->lpat = upa_readl(&ffb->lpat);
ctx->fontxy = upa_readl(&ffb->fontxy);
ctx->fontw = upa_readl(&ffb->fontw);
ctx->fontinc = upa_readl(&ffb->fontinc);
/* stencil/stencilctl only exists on FFB2+ and later
* due to the introduction of 3DRAM-III.
*/
if (fpriv->ffb_type == ffb2_vertical_plus ||
fpriv->ffb_type == ffb2_horizontal_plus) {
ctx->stencil = upa_readl(&ffb->stencil);
ctx->stencilctl = upa_readl(&ffb->stencilctl);
}
for (i = 0; i < 32; i++)
ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
ctx->ucsr = upa_readl(&ffb->ucsr);
return;
}
/* Fetch drawop. */
ctx->drawop = upa_readl(&ffb->drawop);
/* If we were saving the vertex registers, this is where
* we would do it. We would save 32 32-bit words starting
* at ffb->suvtx.
*/
/* Capture rendering attributes. */
ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */
ctx->wid = upa_readl(&ffb->wid); /* Current WID */
ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */
ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */
ctx->consty = upa_readl(&ffb->consty); /* Constant Y */
ctx->constz = upa_readl(&ffb->constz); /* Constant Z */
ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */
ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */
ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */
ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */
ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */
ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */
ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */
ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */
ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */
ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */
ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */
ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */
ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */
ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */
ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */
ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */
ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */
ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */
ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */
ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */
ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */
ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */
ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */
ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */
/* Auxiliary Clips. */
ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min);
ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max);
ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min);
ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max);
ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min);
ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max);
ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min);
ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max);
ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */
ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */
ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */
ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */
/* These registers/features only exist on FFB2 and later chips. */
if (fpriv->ffb_type >= ffb2_prototype) {
ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */
ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */
ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */
ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */
ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */
ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */
ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */
ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */
ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */
/* And stencil/stencilctl only exists on FFB2+ and later
* due to the introduction of 3DRAM-III.
*/
if (fpriv->ffb_type == ffb2_vertical_plus ||
fpriv->ffb_type == ffb2_horizontal_plus) {
ctx->stencil = upa_readl(&ffb->stencil);
ctx->stencilctl = upa_readl(&ffb->stencilctl);
}
}
/* Save the 32x32 area pattern. */
for (i = 0; i < 32; i++)
ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
/* Finally, stash away the User Constol/Status Register. */
ctx->ucsr = upa_readl(&ffb->ucsr);
}
static void ffb_restore_context(ffb_dev_priv_t * fpriv, int old, int idx)
{
ffb_fbcPtr ffb = fpriv->regs;
struct ffb_hw_context *ctx;
int i;
ctx = fpriv->hw_state[idx - 1];
if (idx == 0 || ctx == NULL)
return;
if (ctx->is_2d_only) {
/* 2D applications only care about certain pieces
* of state.
*/
upa_writel(ctx->drawop, &ffb->drawop);
/* If we were restoring the vertex registers, this is where
* we would do it. We would restore 32 32-bit words starting
* at ffb->suvtx.
*/
upa_writel(ctx->ppc, &ffb->ppc);
upa_writel(ctx->wid, &ffb->wid);
upa_writel(ctx->fg, &ffb->fg);
upa_writel(ctx->bg, &ffb->bg);
upa_writel(ctx->xclip, &ffb->xclip);
upa_writel(ctx->fbc, &ffb->fbc);
upa_writel(ctx->rop, &ffb->rop);
upa_writel(ctx->cmp, &ffb->cmp);
upa_writel(ctx->matchab, &ffb->matchab);
upa_writel(ctx->magnab, &ffb->magnab);
upa_writel(ctx->pmask, &ffb->pmask);
upa_writel(ctx->xpmask, &ffb->xpmask);
upa_writel(ctx->lpat, &ffb->lpat);
upa_writel(ctx->fontxy, &ffb->fontxy);
upa_writel(ctx->fontw, &ffb->fontw);
upa_writel(ctx->fontinc, &ffb->fontinc);
/* stencil/stencilctl only exists on FFB2+ and later
* due to the introduction of 3DRAM-III.
*/
if (fpriv->ffb_type == ffb2_vertical_plus ||
fpriv->ffb_type == ffb2_horizontal_plus) {
upa_writel(ctx->stencil, &ffb->stencil);
upa_writel(ctx->stencilctl, &ffb->stencilctl);
upa_writel(0x80000000, &ffb->fbc);
upa_writel((ctx->stencilctl | 0x80000),
&ffb->rawstencilctl);
upa_writel(ctx->fbc, &ffb->fbc);
}
for (i = 0; i < 32; i++)
upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
return;
}
/* Restore drawop. */
upa_writel(ctx->drawop, &ffb->drawop);
/* If we were restoring the vertex registers, this is where
* we would do it. We would restore 32 32-bit words starting
* at ffb->suvtx.
*/
/* Restore rendering attributes. */
upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */
upa_writel(ctx->wid, &ffb->wid); /* Current WID */
upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */
upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */
upa_writel(ctx->consty, &ffb->consty); /* Constant Y */
upa_writel(ctx->constz, &ffb->constz); /* Constant Z */
upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */
upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */
upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */
upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */
upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */
upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */
upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */
upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */
upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */
upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */
upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */
upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */
upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */
upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */
upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */
upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */
upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */
upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */
upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */
upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */
upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */
upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */
upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */
upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */
/* Auxiliary Clips. */
upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min);
upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max);
upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min);
upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max);
upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min);
upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max);
upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min);
upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max);
upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */
upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */
upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */
upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */
/* These registers/features only exist on FFB2 and later chips. */
if (fpriv->ffb_type >= ffb2_prototype) {
upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */
upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */
upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */
upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */
upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */
upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */
upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */
upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */
upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */
/* And stencil/stencilctl only exists on FFB2+ and later
* due to the introduction of 3DRAM-III.
*/
if (fpriv->ffb_type == ffb2_vertical_plus ||
fpriv->ffb_type == ffb2_horizontal_plus) {
/* Unfortunately, there is a hardware bug on
* the FFB2+ chips which prevents a normal write
* to the stencil control register from working
* as it should.
*
* The state controlled by the FFB stencilctl register
* really gets transferred to the per-buffer instances
* of the stencilctl register in the 3DRAM chips.
*
* The bug is that FFB does not update buffer C correctly,
* so we have to do it by hand for them.
*/
/* This will update buffers A and B. */
upa_writel(ctx->stencil, &ffb->stencil);
upa_writel(ctx->stencilctl, &ffb->stencilctl);
/* Force FFB to use buffer C 3dram regs. */
upa_writel(0x80000000, &ffb->fbc);
upa_writel((ctx->stencilctl | 0x80000),
&ffb->rawstencilctl);
/* Now restore the correct FBC controls. */
upa_writel(ctx->fbc, &ffb->fbc);
}
}
/* Restore the 32x32 area pattern. */
for (i = 0; i < 32; i++)
upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
/* Finally, stash away the User Constol/Status Register.
* The only state we really preserve here is the picking
* control.
*/
upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
}
#define FFB_UCSR_FB_BUSY 0x01000000
#define FFB_UCSR_RP_BUSY 0x02000000
#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
static void FFBWait(ffb_fbcPtr ffb)
{
int limit = 100000;
do {
u32 regval = upa_readl(&ffb->ucsr);
if ((regval & FFB_UCSR_ALL_BUSY) == 0)
break;
} while (--limit);
}
int ffb_driver_context_switch(drm_device_t * dev, int old, int new)
{
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
#ifdef DRM_DMA_HISTOGRAM
dev->ctx_start = get_cycles();
#endif
DRM_DEBUG("Context switch from %d to %d\n", old, new);
if (new == dev->last_context || dev->last_context == 0) {
dev->last_context = new;
return 0;
}
FFBWait(fpriv->regs);
ffb_save_context(fpriv, old);
ffb_restore_context(fpriv, old, new);
FFBWait(fpriv->regs);
dev->last_context = new;
return 0;
}
int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
drm_ctx_res_t res;
drm_ctx_t ctx;
int i;
DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
if (copy_from_user(&res, (drm_ctx_res_t __user *) arg, sizeof(res)))
return -EFAULT;
if (res.count >= DRM_RESERVED_CONTEXTS) {
memset(&ctx, 0, sizeof(ctx));
for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
ctx.handle = i;
if (copy_to_user(&res.contexts[i], &i, sizeof(i)))
return -EFAULT;
}
}
res.count = DRM_RESERVED_CONTEXTS;
if (copy_to_user((drm_ctx_res_t __user *) arg, &res, sizeof(res)))
return -EFAULT;
return 0;
}
int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
drm_ctx_t ctx;
int idx;
if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
return -EFAULT;
idx = DRM(alloc_queue) (dev, (ctx.flags & _DRM_CONTEXT_2DONLY));
if (idx < 0)
return -ENFILE;
DRM_DEBUG("%d\n", ctx.handle);
ctx.handle = idx;
if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx)))
return -EFAULT;
return 0;
}
int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
struct ffb_hw_context *hwctx;
drm_ctx_t ctx;
int idx;
if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
return -EFAULT;
idx = ctx.handle;
if (idx <= 0 || idx >= FFB_MAX_CTXS)
return -EINVAL;
hwctx = fpriv->hw_state[idx - 1];
if (hwctx == NULL)
return -EINVAL;
if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0)
hwctx->is_2d_only = 0;
else
hwctx->is_2d_only = 1;
return 0;
}
int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
struct ffb_hw_context *hwctx;
drm_ctx_t ctx;
int idx;
if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
return -EFAULT;
idx = ctx.handle;
if (idx <= 0 || idx >= FFB_MAX_CTXS)
return -EINVAL;
hwctx = fpriv->hw_state[idx - 1];
if (hwctx == NULL)
return -EINVAL;
if (hwctx->is_2d_only != 0)
ctx.flags = _DRM_CONTEXT_2DONLY;
else
ctx.flags = 0;
if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx)))
return -EFAULT;
return 0;
}
int ffb_driver_switchctx(struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg)
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
drm_ctx_t ctx;
if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
return -EFAULT;
DRM_DEBUG("%d\n", ctx.handle);
return ffb_driver_context_switch(dev, dev->last_context, ctx.handle);
}
int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
drm_ctx_t ctx;
if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
return -EFAULT;
DRM_DEBUG("%d\n", ctx.handle);
return 0;
}
int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
drm_ctx_t ctx;
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
int idx;
if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
return -EFAULT;
DRM_DEBUG("%d\n", ctx.handle);
idx = ctx.handle - 1;
if (idx < 0 || idx >= FFB_MAX_CTXS)
return -EINVAL;
kfree(fpriv->hw_state[idx]);
fpriv->hw_state[idx] = NULL;
return 0;
}
void ffb_set_context_ioctls(void)
{
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)].func = ffb_driver_addctx;
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx;
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx;
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx;
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func =
ffb_driver_switchctx;
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx;
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx;
}
drivers/char/drm/ffb_drv.c 已删除 100644 → 0
浏览文件 @ c203b33d
/* $Id: ffb_drv.c,v 1.16 2001/10/18 16:00:24 davem Exp $
* ffb_drv.c: Creator/Creator3D direct rendering driver.
*
* Copyright (C) 2000 David S. Miller (davem@redhat.com)
*/
#include "ffb.h"
#include "drmP.h"
#include "ffb_drv.h"
#include <linux/smp_lock.h>
#include <asm/shmparam.h>
#include <asm/oplib.h>
#include <asm/upa.h>
#define DRIVER_AUTHOR "David S. Miller"
#define DRIVER_NAME "ffb"
#define DRIVER_DESC "Creator/Creator3D"
#define DRIVER_DATE "20000517"
#define DRIVER_MAJOR 0
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 1
typedef struct _ffb_position_t {
int node;
int root;
} ffb_position_t;
static ffb_position_t *ffb_position;
static void get_ffb_type(ffb_dev_priv_t * ffb_priv, int instance)
{
volatile unsigned char *strap_bits;
unsigned char val;
strap_bits = (volatile unsigned char *)
(ffb_priv->card_phys_base + 0x00200000UL);
/* Don't ask, you have to read the value twice for whatever
* reason to get correct contents.
*/
val = upa_readb(strap_bits);
val = upa_readb(strap_bits);
switch (val & 0x78) {
case (0x0 << 5) | (0x0 << 3):
ffb_priv->ffb_type = ffb1_prototype;
printk("ffb%d: Detected FFB1 pre-FCS prototype\n", instance);
break;
case (0x0 << 5) | (0x1 << 3):
ffb_priv->ffb_type = ffb1_standard;
printk("ffb%d: Detected FFB1\n", instance);
break;
case (0x0 << 5) | (0x3 << 3):
ffb_priv->ffb_type = ffb1_speedsort;
printk("ffb%d: Detected FFB1-SpeedSort\n", instance);
break;
case (0x1 << 5) | (0x0 << 3):
ffb_priv->ffb_type = ffb2_prototype;
printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n",
instance);
break;
case (0x1 << 5) | (0x1 << 3):
ffb_priv->ffb_type = ffb2_vertical;
printk("ffb%d: Detected FFB2/vertical\n", instance);
break;
case (0x1 << 5) | (0x2 << 3):
ffb_priv->ffb_type = ffb2_vertical_plus;
printk("ffb%d: Detected FFB2+/vertical\n", instance);
break;
case (0x2 << 5) | (0x0 << 3):
ffb_priv->ffb_type = ffb2_horizontal;
printk("ffb%d: Detected FFB2/horizontal\n", instance);
break;
case (0x2 << 5) | (0x2 << 3):
ffb_priv->ffb_type = ffb2_horizontal;
printk("ffb%d: Detected FFB2+/horizontal\n", instance);
break;
default:
ffb_priv->ffb_type = ffb2_vertical;
printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n",
instance, val);
break;
};
}
static void ffb_apply_upa_parent_ranges(int parent,
struct linux_prom64_registers *regs)
{
struct linux_prom64_ranges ranges[PROMREG_MAX];
char name[128];
int len, i;
prom_getproperty(parent, "name", name, sizeof(name));
if (strcmp(name, "upa") != 0)
return;
len =
prom_getproperty(parent, "ranges", (void *)ranges, sizeof(ranges));
if (len <= 0)
return;
len /= sizeof(struct linux_prom64_ranges);
for (i = 0; i < len; i++) {
struct linux_prom64_ranges *rng = &ranges[i];
u64 phys_addr = regs->phys_addr;
if (phys_addr >= rng->ot_child_base &&
phys_addr < (rng->ot_child_base + rng->or_size)) {
regs->phys_addr -= rng->ot_child_base;
regs->phys_addr += rng->ot_parent_base;
return;
}
}
return;
}
static int ffb_init_one(drm_device_t * dev, int prom_node, int parent_node,
int instance)
{
struct linux_prom64_registers regs[2 * PROMREG_MAX];
ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private;
int i;
ffb_priv->prom_node = prom_node;
if (prom_getproperty(ffb_priv->prom_node, "reg",
(void *)regs, sizeof(regs)) <= 0) {
return -EINVAL;
}
ffb_apply_upa_parent_ranges(parent_node, &regs[0]);
ffb_priv->card_phys_base = regs[0].phys_addr;
ffb_priv->regs = (ffb_fbcPtr)
(regs[0].phys_addr + 0x00600000UL);
get_ffb_type(ffb_priv, instance);
for (i = 0; i < FFB_MAX_CTXS; i++)
ffb_priv->hw_state[i] = NULL;
return 0;
}
static drm_map_t *ffb_find_map(struct file *filp, unsigned long off)
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev;
drm_map_list_t *r_list;
struct list_head *list;
drm_map_t *map;
if (!priv || (dev = priv->dev) == NULL)
return NULL;
list_for_each(list, &dev->maplist->head) {
r_list = (drm_map_list_t *) list;
map = r_list->map;
if (!map)
continue;
if (r_list->user_token == off)
return map;
}
return NULL;
}
unsigned long ffb_get_unmapped_area(struct file *filp,
unsigned long hint,
unsigned long len,
unsigned long pgoff, unsigned long flags)
{
drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT);
unsigned long addr = -ENOMEM;
if (!map)
return get_unmapped_area(NULL, hint, len, pgoff, flags);
if (map->type == _DRM_FRAME_BUFFER || map->type == _DRM_REGISTERS) {
#ifdef HAVE_ARCH_FB_UNMAPPED_AREA
addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags);
#else
addr = get_unmapped_area(NULL, hint, len, pgoff, flags);
#endif
} else if (map->type == _DRM_SHM && SHMLBA > PAGE_SIZE) {
unsigned long slack = SHMLBA - PAGE_SIZE;
addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags);
if (!(addr & ~PAGE_MASK)) {
unsigned long kvirt = (unsigned long)map->handle;
if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
unsigned long koff, aoff;
koff = kvirt & (SHMLBA - 1);
aoff = addr & (SHMLBA - 1);
if (koff < aoff)
koff += SHMLBA;
addr += (koff - aoff);
}
}
} else {
addr = get_unmapped_area(NULL, hint, len, pgoff, flags);
}
return addr;
}
static int ffb_presetup(drm_device_t * dev)
{
ffb_dev_priv_t *ffb_priv;
int ret = 0;
int i = 0;
/* Check for the case where no device was found. */
if (ffb_position == NULL)
return -ENODEV;
/* code used to use numdevs no numdevs anymore */
ffb_priv = kmalloc(sizeof(ffb_dev_priv_t), GFP_KERNEL);
if (!ffb_priv)
return -ENOMEM;
memset(ffb_priv, 0, sizeof(*ffb_priv));
dev->dev_private = ffb_priv;
ret = ffb_init_one(dev, ffb_position[i].node, ffb_position[i].root, i);
return ret;
}
static void ffb_driver_release(drm_device_t * dev, struct file *filp)
{
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock);
int idx;
idx = context - 1;
if (fpriv &&
context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) {
kfree(fpriv->hw_state[idx]);
fpriv->hw_state[idx] = NULL;
}
}
static void ffb_driver_pretakedown(drm_device_t * dev)
{
kfree(dev->dev_private);
}
static int ffb_driver_postcleanup(drm_device_t * dev)
{
kfree(ffb_position);
return 0;
}
static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev,
drm_lock_t * lock)
{
dev->lock.filp = 0;
{
__volatile__ unsigned int *plock = &dev->lock.hw_lock->lock;
unsigned int old, new, prev, ctx;
ctx = lock->context;
do {
old = *plock;
new = ctx;
prev = cmpxchg(plock, old, new);
} while (prev != old);
}
wake_up_interruptible(&dev->lock.lock_queue);
}
static unsigned long ffb_driver_get_map_ofs(drm_map_t * map)
{
return (map->offset & 0xffffffff);
}
static unsigned long ffb_driver_get_reg_ofs(drm_device_t * dev)
{
ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private;
if (ffb_priv)
return ffb_priv->card_phys_base;
return 0;
}
static int postinit(struct drm_device *dev, unsigned long flags)
{
DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
DRIVER_NAME,
DRIVER_MAJOR,
DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE, dev->minor);
return 0;
}
static int version(drm_version_t * version)
{
int len;
version->version_major = DRIVER_MAJOR;
version->version_minor = DRIVER_MINOR;
version->version_patchlevel = DRIVER_PATCHLEVEL;
DRM_COPY(version->name, DRIVER_NAME);
DRM_COPY(version->date, DRIVER_DATE);
DRM_COPY(version->desc, DRIVER_DESC);
return 0;
}
static drm_ioctl_desc_t ioctls[] = {
};
static struct drm_driver driver = {
.driver_features = 0,
.dev_priv_size = sizeof(u32),
.release = ffb_driver_release,
.presetup = ffb_presetup,
.pretakedown = ffb_driver_pretakedown,
.postcleanup = ffb_driver_postcleanup,
.kernel_context_switch = ffb_driver_context_switch,
.kernel_context_switch_unlock = ffb_driver_kernel_context_switch_unlock,
.get_map_ofs = ffb_driver_get_map_ofs,
.get_reg_ofs = ffb_driver_get_reg_ofs,
.postinit = postinit,
.version = version,
.ioctls = ioctls,
.num_ioctls = DRM_ARRAY_SIZE(ioctls),
.fops = {
.owner = THIS_MODULE,
.open = drm_open,
.release = drm_release,
.ioctl = drm_ioctl,
.mmap = drm_mmap,
.poll = drm_poll,
.fasync = drm_fasync,
}
,
};
static int __init ffb_init(void)
{
return -ENODEV;
}
static void __exit ffb_exit(void)
{
}
module_init(ffb_init);
module_exit(ffb_exit);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
drivers/char/drm/ffb_drv.h 已删除 100644 → 0
浏览文件 @ c203b33d
/* $Id: ffb_drv.h,v 1.1 2000/06/01 04:24:39 davem Exp $
* ffb_drv.h: Creator/Creator3D direct rendering driver.
*
* Copyright (C) 2000 David S. Miller (davem@redhat.com)
*/
/* Auxilliary clips. */
typedef struct {
volatile unsigned int min;
volatile unsigned int max;
} ffb_auxclip, *ffb_auxclipPtr;
/* FFB register set. */
typedef struct _ffb_fbc {
/* Next vertex registers, on the right we list which drawops
* use said register and the logical name the register has in
* that context.
*//* DESCRIPTION DRAWOP(NAME) */
/*0x00*/ unsigned int pad1[3];
/* Reserved */
/*0x0c*/ volatile unsigned int alpha;
/* ALPHA Transparency */
/*0x10*/ volatile unsigned int red;
/* RED */
/*0x14*/ volatile unsigned int green;
/* GREEN */
/*0x18*/ volatile unsigned int blue;
/* BLUE */
/*0x1c*/ volatile unsigned int z;
/* DEPTH */
/*0x20*/ volatile unsigned int y;
/* Y triangle(DOYF) */
/* aadot(DYF) */
/* ddline(DYF) */
/* aaline(DYF) */
/*0x24*/ volatile unsigned int x;
/* X triangle(DOXF) */
/* aadot(DXF) */
/* ddline(DXF) */
/* aaline(DXF) */
/*0x28*/ unsigned int pad2[2];
/* Reserved */
/*0x30*/ volatile unsigned int ryf;
/* Y (alias to DOYF) ddline(RYF) */
/* aaline(RYF) */
/* triangle(RYF) */
/*0x34*/ volatile unsigned int rxf;
/* X ddline(RXF) */
/* aaline(RXF) */
/* triangle(RXF) */
/*0x38*/ unsigned int pad3[2];
/* Reserved */
/*0x40*/ volatile unsigned int dmyf;
/* Y (alias to DOYF) triangle(DMYF) */
/*0x44*/ volatile unsigned int dmxf;
/* X triangle(DMXF) */
/*0x48*/ unsigned int pad4[2];
/* Reserved */
/*0x50*/ volatile unsigned int ebyi;
/* Y (alias to RYI) polygon(EBYI) */
/*0x54*/ volatile unsigned int ebxi;
/* X polygon(EBXI) */
/*0x58*/ unsigned int pad5[2];
/* Reserved */
/*0x60*/ volatile unsigned int by;
/* Y brline(RYI) */
/* fastfill(OP) */
/* polygon(YI) */
/* rectangle(YI) */
/* bcopy(SRCY) */
/* vscroll(SRCY) */
/*0x64*/ volatile unsigned int bx;
/* X brline(RXI) */
/* polygon(XI) */
/* rectangle(XI) */
/* bcopy(SRCX) */
/* vscroll(SRCX) */
/* fastfill(GO) */
/*0x68*/ volatile unsigned int dy;
/* destination Y fastfill(DSTY) */
/* bcopy(DSRY) */
/* vscroll(DSRY) */
/*0x6c*/ volatile unsigned int dx;
/* destination X fastfill(DSTX) */
/* bcopy(DSTX) */
/* vscroll(DSTX) */
/*0x70*/ volatile unsigned int bh;
/* Y (alias to RYI) brline(DYI) */
/* dot(DYI) */
/* polygon(ETYI) */
/* Height fastfill(H) */
/* bcopy(H) */
/* vscroll(H) */
/* Y count fastfill(NY) */
/*0x74*/ volatile unsigned int bw;
/* X dot(DXI) */
/* brline(DXI) */
/* polygon(ETXI) */
/* fastfill(W) */
/* bcopy(W) */
/* vscroll(W) */
/* fastfill(NX) */
/*0x78*/ unsigned int pad6[2];
/* Reserved */
/*0x80*/ unsigned int pad7[32];
/* Reserved */
/* Setup Unit's vertex state register */
/*100*/ volatile unsigned int suvtx;
/*104*/ unsigned int pad8[63];
/* Reserved */
/* Frame Buffer Control Registers */
/*200*/ volatile unsigned int ppc;
/* Pixel Processor Control */
/*204*/ volatile unsigned int wid;
/* Current WID */
/*208*/ volatile unsigned int fg;
/* FG data */
/*20c*/ volatile unsigned int bg;
/* BG data */
/*210*/ volatile unsigned int consty;
/* Constant Y */
/*214*/ volatile unsigned int constz;
/* Constant Z */
/*218*/ volatile unsigned int xclip;
/* X Clip */
/*21c*/ volatile unsigned int dcss;
/* Depth Cue Scale Slope */
/*220*/ volatile unsigned int vclipmin;
/* Viewclip XY Min Bounds */
/*224*/ volatile unsigned int vclipmax;
/* Viewclip XY Max Bounds */
/*228*/ volatile unsigned int vclipzmin;
/* Viewclip Z Min Bounds */
/*22c*/ volatile unsigned int vclipzmax;
/* Viewclip Z Max Bounds */
/*230*/ volatile unsigned int dcsf;
/* Depth Cue Scale Front Bound */
/*234*/ volatile unsigned int dcsb;
/* Depth Cue Scale Back Bound */
/*238*/ volatile unsigned int dczf;
/* Depth Cue Z Front */
/*23c*/ volatile unsigned int dczb;
/* Depth Cue Z Back */
/*240*/ unsigned int pad9;
/* Reserved */
/*244*/ volatile unsigned int blendc;
/* Alpha Blend Control */
/*248*/ volatile unsigned int blendc1;
/* Alpha Blend Color 1 */
/*24c*/ volatile unsigned int blendc2;
/* Alpha Blend Color 2 */
/*250*/ volatile unsigned int fbramitc;
/* FB RAM Interleave Test Control */
/*254*/ volatile unsigned int fbc;
/* Frame Buffer Control */
/*258*/ volatile unsigned int rop;
/* Raster OPeration */
/*25c*/ volatile unsigned int cmp;
/* Frame Buffer Compare */
/*260*/ volatile unsigned int matchab;
/* Buffer AB Match Mask */
/*264*/ volatile unsigned int matchc;
/* Buffer C(YZ) Match Mask */
/*268*/ volatile unsigned int magnab;
/* Buffer AB Magnitude Mask */
/*26c*/ volatile unsigned int magnc;
/* Buffer C(YZ) Magnitude Mask */
/*270*/ volatile unsigned int fbcfg0;
/* Frame Buffer Config 0 */
/*274*/ volatile unsigned int fbcfg1;
/* Frame Buffer Config 1 */
/*278*/ volatile unsigned int fbcfg2;
/* Frame Buffer Config 2 */
/*27c*/ volatile unsigned int fbcfg3;
/* Frame Buffer Config 3 */
/*280*/ volatile unsigned int ppcfg;
/* Pixel Processor Config */
/*284*/ volatile unsigned int pick;
/* Picking Control */
/*288*/ volatile unsigned int fillmode;
/* FillMode */
/*28c*/ volatile unsigned int fbramwac;
/* FB RAM Write Address Control */
/*290*/ volatile unsigned int pmask;
/* RGB PlaneMask */
/*294*/ volatile unsigned int xpmask;
/* X PlaneMask */
/*298*/ volatile unsigned int ypmask;
/* Y PlaneMask */
/*29c*/ volatile unsigned int zpmask;
/* Z PlaneMask */
/*2a0*/ ffb_auxclip auxclip[4];
/* Auxilliary Viewport Clip */
/* New 3dRAM III support regs */
/*2c0*/ volatile unsigned int rawblend2;
/*2c4*/ volatile unsigned int rawpreblend;
/*2c8*/ volatile unsigned int rawstencil;
/*2cc*/ volatile unsigned int rawstencilctl;
/*2d0*/ volatile unsigned int threedram1;
/*2d4*/ volatile unsigned int threedram2;
/*2d8*/ volatile unsigned int passin;
/*2dc*/ volatile unsigned int rawclrdepth;
/*2e0*/ volatile unsigned int rawpmask;
/*2e4*/ volatile unsigned int rawcsrc;
/*2e8*/ volatile unsigned int rawmatch;
/*2ec*/ volatile unsigned int rawmagn;
/*2f0*/ volatile unsigned int rawropblend;
/*2f4*/ volatile unsigned int rawcmp;
/*2f8*/ volatile unsigned int rawwac;
/*2fc*/ volatile unsigned int fbramid;
/*300*/ volatile unsigned int drawop;
/* Draw OPeration */
/*304*/ unsigned int pad10[2];
/* Reserved */
/*30c*/ volatile unsigned int lpat;
/* Line Pattern control */
/*310*/ unsigned int pad11;
/* Reserved */
/*314*/ volatile unsigned int fontxy;
/* XY Font coordinate */
/*318*/ volatile unsigned int fontw;
/* Font Width */
/*31c*/ volatile unsigned int fontinc;
/* Font Increment */
/*320*/ volatile unsigned int font;
/* Font bits */
/*324*/ unsigned int pad12[3];
/* Reserved */
/*330*/ volatile unsigned int blend2;
/*334*/ volatile unsigned int preblend;
/*338*/ volatile unsigned int stencil;
/*33c*/ volatile unsigned int stencilctl;
/*340*/ unsigned int pad13[4];
/* Reserved */
/*350*/ volatile unsigned int dcss1;
/* Depth Cue Scale Slope 1 */
/*354*/ volatile unsigned int dcss2;
/* Depth Cue Scale Slope 2 */
/*358*/ volatile unsigned int dcss3;
/* Depth Cue Scale Slope 3 */
/*35c*/ volatile unsigned int widpmask;
/*360*/ volatile unsigned int dcs2;
/*364*/ volatile unsigned int dcs3;
/*368*/ volatile unsigned int dcs4;
/*36c*/ unsigned int pad14;
/* Reserved */
/*370*/ volatile unsigned int dcd2;
/*374*/ volatile unsigned int dcd3;
/*378*/ volatile unsigned int dcd4;
/*37c*/ unsigned int pad15;
/* Reserved */
/*380*/ volatile unsigned int pattern[32];
/* area Pattern */
/*400*/ unsigned int pad16[8];
/* Reserved */
/*420*/ volatile unsigned int reset;
/* chip RESET */
/*424*/ unsigned int pad17[247];
/* Reserved */
/*800*/ volatile unsigned int devid;
/* Device ID */
/*804*/ unsigned int pad18[63];
/* Reserved */
/*900*/ volatile unsigned int ucsr;
/* User Control & Status Register */
/*904*/ unsigned int pad19[31];
/* Reserved */
/*980*/ volatile unsigned int mer;
/* Mode Enable Register */
/*984*/ unsigned int pad20[1439];
/* Reserved */
} ffb_fbc, *ffb_fbcPtr;
struct ffb_hw_context {
int is_2d_only;
unsigned int ppc;
unsigned int wid;
unsigned int fg;
unsigned int bg;
unsigned int consty;
unsigned int constz;
unsigned int xclip;
unsigned int dcss;
unsigned int vclipmin;
unsigned int vclipmax;
unsigned int vclipzmin;
unsigned int vclipzmax;
unsigned int dcsf;
unsigned int dcsb;
unsigned int dczf;
unsigned int dczb;
unsigned int blendc;
unsigned int blendc1;
unsigned int blendc2;
unsigned int fbc;
unsigned int rop;
unsigned int cmp;
unsigned int matchab;
unsigned int matchc;
unsigned int magnab;
unsigned int magnc;
unsigned int pmask;
unsigned int xpmask;
unsigned int ypmask;
unsigned int zpmask;
unsigned int auxclip0min;
unsigned int auxclip0max;
unsigned int auxclip1min;
unsigned int auxclip1max;
unsigned int auxclip2min;
unsigned int auxclip2max;
unsigned int auxclip3min;
unsigned int auxclip3max;
unsigned int drawop;
unsigned int lpat;
unsigned int fontxy;
unsigned int fontw;
unsigned int fontinc;
unsigned int area_pattern[32];
unsigned int ucsr;
unsigned int stencil;
unsigned int stencilctl;
unsigned int dcss1;
unsigned int dcss2;
unsigned int dcss3;
unsigned int dcs2;
unsigned int dcs3;
unsigned int dcs4;
unsigned int dcd2;
unsigned int dcd3;
unsigned int dcd4;
unsigned int mer;
};
#define FFB_MAX_CTXS 32
enum ffb_chip_type {
ffb1_prototype = 0, /* Early pre-FCS FFB */
ffb1_standard, /* First FCS FFB, 100Mhz UPA, 66MHz gclk */
ffb1_speedsort, /* Second FCS FFB, 100Mhz UPA, 75MHz gclk */
ffb2_prototype, /* Early pre-FCS vertical FFB2 */
ffb2_vertical, /* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk,
75(SingleBuffer)/83(DoubleBuffer) MHz fclk */
ffb2_vertical_plus, /* Second FCS FFB2/vertical, same timings */
ffb2_horizontal, /* First FCS FFB2/horizontal, same timings as FFB2/vert */
ffb2_horizontal_plus, /* Second FCS FFB2/horizontal, same timings */
afb_m3, /* FCS Elite3D, 3 float chips */
afb_m6 /* FCS Elite3D, 6 float chips */
};
typedef struct ffb_dev_priv {
/* Misc software state. */
int prom_node;
enum ffb_chip_type ffb_type;
u64 card_phys_base;
struct miscdevice miscdev;
/* Controller registers. */
ffb_fbcPtr regs;
/* Context table. */
struct ffb_hw_context *hw_state[FFB_MAX_CTXS];
} ffb_dev_priv_t;
extern unsigned long ffb_get_unmapped_area(struct file *filp,
unsigned long hint,
unsigned long len,
unsigned long pgoff,
unsigned long flags);
extern void ffb_set_context_ioctls(void);
extern drm_ioctl_desc_t DRM(ioctls)[];
extern int ffb_driver_context_switch(drm_device_t * dev, int old, int new);
drivers/video/cg3.c
浏览文件 @ d0a9af80
......@@ -186,8 +186,7 @@ static int cg3_setcolreg(unsigned regno,
* @blank_mode: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
cg3_blank(int blank, struct fb_info *info)
static int cg3_blank(int blank, struct fb_info *info)
{
struct cg3_par *par = (struct cg3_par *) info->par;
struct cg3_regs __iomem *regs = par->regs;
......@@ -251,8 +250,8 @@ static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
* Initialisation
*/
static void
cg3_init_fix(struct fb_info *info, int linebytes, struct device_node *dp)
static void __devinit cg3_init_fix(struct fb_info *info, int linebytes,
struct device_node *dp)
{
strlcpy(info->fix.id, dp->name, sizeof(info->fix.id));
......@@ -264,8 +263,8 @@ cg3_init_fix(struct fb_info *info, int linebytes, struct device_node *dp)
info->fix.accel = FB_ACCEL_SUN_CGTHREE;
}
static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
struct device_node *dp)
static void __devinit cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
struct device_node *dp)
{
char *params;
char *p;
......@@ -287,36 +286,36 @@ static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
}
}
static u8 cg3regvals_66hz[] __initdata = { /* 1152 x 900, 66 Hz */
static u8 cg3regvals_66hz[] __devinitdata = { /* 1152 x 900, 66 Hz */
0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x20, 0
};
static u8 cg3regvals_76hz[] __initdata = { /* 1152 x 900, 76 Hz */
static u8 cg3regvals_76hz[] __devinitdata = { /* 1152 x 900, 76 Hz */
0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x24, 0
};
static u8 cg3regvals_rdi[] __initdata = { /* 640 x 480, cgRDI */
static u8 cg3regvals_rdi[] __devinitdata = { /* 640 x 480, cgRDI */
0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x22, 0
};
static u8 *cg3_regvals[] __initdata = {
static u8 *cg3_regvals[] __devinitdata = {
cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
};
static u_char cg3_dacvals[] __initdata = {
static u_char cg3_dacvals[] __devinitdata = {
4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
};
static void cg3_do_default_mode(struct cg3_par *par)
static void __devinit cg3_do_default_mode(struct cg3_par *par)
{
enum cg3_type type;
u8 *p;
......@@ -433,7 +432,8 @@ static int __devinit cg3_init_one(struct of_device *op)
return 0;
}
static int __devinit cg3_probe(struct of_device *dev, const struct of_device_id *match)
static int __devinit cg3_probe(struct of_device *dev,
const struct of_device_id *match)
{
struct of_device *op = to_of_device(&dev->dev);
......
drivers/video/ffb.c
浏览文件 @ d0a9af80
......@@ -336,14 +336,30 @@ struct ffb_dac {
u32 value2;
};
#define FFB_DAC_UCTRL 0x1001 /* User Control */
#define FFB_DAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */
#define FFB_DAC_UCTRL_MANREV_SHIFT 8
#define FFB_DAC_TGEN 0x6000 /* Timing Generator */
#define FFB_DAC_TGEN_VIDE 0x00000001 /* Video Enable */
#define FFB_DAC_DID 0x8000 /* Device Identification */
#define FFB_DAC_DID_PNUM 0x0ffff000 /* Device Part Number */
#define FFB_DAC_DID_PNUM_SHIFT 12
#define FFB_DAC_DID_REV 0xf0000000 /* Device Revision */
#define FFB_DAC_DID_REV_SHIFT 28
#define FFB_DAC_CUR_CTRL 0x100
#define FFB_DAC_CUR_CTRL_P0 0x00000001
#define FFB_DAC_CUR_CTRL_P1 0x00000002
struct ffb_par {
spinlock_t lock;
struct ffb_fbc __iomem *fbc;
struct ffb_dac __iomem *dac;
u32 flags;
#define FFB_FLAG_AFB 0x00000001
#define FFB_FLAG_BLANKED 0x00000002
#define FFB_FLAG_AFB 0x00000001 /* AFB m3 or m6 */
#define FFB_FLAG_BLANKED 0x00000002 /* screen is blanked */
#define FFB_FLAG_INVCURSOR 0x00000004 /* DAC has inverted cursor logic */
u32 fg_cache __attribute__((aligned (8)));
u32 bg_cache;
......@@ -354,7 +370,6 @@ struct ffb_par {
unsigned long physbase;
unsigned long fbsize;
int dac_rev;
int board_type;
};
......@@ -426,11 +441,12 @@ static void ffb_switch_from_graph(struct ffb_par *par)
FFBWait(par);
/* Disable cursor. */
upa_writel(0x100, &dac->type2);
if (par->dac_rev <= 2)
upa_writel(FFB_DAC_CUR_CTRL, &dac->type2);
if (par->flags & FFB_FLAG_INVCURSOR)
upa_writel(0, &dac->value2);
else
upa_writel(3, &dac->value2);
upa_writel((FFB_DAC_CUR_CTRL_P0 |
FFB_DAC_CUR_CTRL_P1), &dac->value2);
spin_unlock_irqrestore(&par->lock, flags);
}
......@@ -664,18 +680,18 @@ ffb_blank(int blank, struct fb_info *info)
struct ffb_par *par = (struct ffb_par *) info->par;
struct ffb_dac __iomem *dac = par->dac;
unsigned long flags;
u32 tmp;
u32 val;
int i;
spin_lock_irqsave(&par->lock, flags);
FFBWait(par);
upa_writel(FFB_DAC_TGEN, &dac->type);
val = upa_readl(&dac->value);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
upa_writel(0x6000, &dac->type);
tmp = (upa_readl(&dac->value) | 0x1);
upa_writel(0x6000, &dac->type);
upa_writel(tmp, &dac->value);
val |= FFB_DAC_TGEN_VIDE;
par->flags &= ~FFB_FLAG_BLANKED;
break;
......@@ -683,13 +699,16 @@ ffb_blank(int blank, struct fb_info *info)
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
upa_writel(0x6000, &dac->type);
tmp = (upa_readl(&dac->value) & ~0x1);
upa_writel(0x6000, &dac->type);
upa_writel(tmp, &dac->value);
val &= ~FFB_DAC_TGEN_VIDE;
par->flags |= FFB_FLAG_BLANKED;
break;
}
upa_writel(FFB_DAC_TGEN, &dac->type);
upa_writel(val, &dac->value);
for (i = 0; i < 10; i++) {
upa_writel(FFB_DAC_TGEN, &dac->type);
upa_readl(&dac->value);
}
spin_unlock_irqrestore(&par->lock, flags);
......@@ -894,6 +913,7 @@ static int ffb_init_one(struct of_device *op)
struct ffb_dac __iomem *dac;
struct all_info *all;
int err;
u32 dac_pnum, dac_rev, dac_mrev;
all = kzalloc(sizeof(*all), GFP_KERNEL);
if (!all)
......@@ -948,17 +968,31 @@ static int ffb_init_one(struct of_device *op)
if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
ffb_switch_from_graph(&all->par);
dac = all->par.dac;
upa_writel(0x8000, &dac->type);
all->par.dac_rev = upa_readl(&dac->value) >> 0x1c;
upa_writel(FFB_DAC_DID, &dac->type);
dac_pnum = upa_readl(&dac->value);
dac_rev = (dac_pnum & FFB_DAC_DID_REV) >> FFB_DAC_DID_REV_SHIFT;
dac_pnum = (dac_pnum & FFB_DAC_DID_PNUM) >> FFB_DAC_DID_PNUM_SHIFT;
upa_writel(FFB_DAC_UCTRL, &dac->type);
dac_mrev = upa_readl(&dac->value);
dac_mrev = (dac_mrev & FFB_DAC_UCTRL_MANREV) >>
FFB_DAC_UCTRL_MANREV_SHIFT;
/* Elite3D has different DAC revision numbering, and no DAC revisions
* have the reversed meaning of cursor enable.
* have the reversed meaning of cursor enable. Otherwise, Pacifica 1
* ramdacs with manufacturing revision less than 3 have inverted
* cursor logic. We identify Pacifica 1 as not Pacifica 2, the
* latter having a part number value of 0x236e.
*/
if (all->par.flags & FFB_FLAG_AFB)
all->par.dac_rev = 10;
if ((all->par.flags & FFB_FLAG_AFB) || dac_pnum == 0x236e) {
all->par.flags &= ~FFB_FLAG_INVCURSOR;
} else {
if (dac_mrev < 3)
all->par.flags |= FFB_FLAG_INVCURSOR;
}
ffb_switch_from_graph(&all->par);
/* Unblank it just to be sure. When there are multiple
* FFB/AFB cards in the system, or it is not the OBP
......@@ -993,10 +1027,12 @@ static int ffb_init_one(struct of_device *op)
dev_set_drvdata(&op->dev, all);
printk("%s: %s at %016lx, type %d, DAC revision %d\n",
printk("%s: %s at %016lx, type %d, "
"DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
dp->full_name,
((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
all->par.physbase, all->par.board_type, all->par.dac_rev);
all->par.physbase, all->par.board_type,
dac_pnum, dac_rev, dac_mrev);
return 0;
}
......
include/asm-sparc/mostek.h
浏览文件 @ d0a9af80
......@@ -87,7 +87,7 @@ extern void __iomem *mstk48t02_regs;
#define MSTK_DOW_MASK 0x07
#define MSTK_DOM_MASK 0x3f
#define MSTK_MONTH_MASK 0x1f
#define MSTK_YEAR_MASK 0xff
#define MSTK_YEAR_MASK 0xffU
/* Binary coded decimal conversion macros. */
#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
......
include/asm-sparc64/mostek.h
浏览文件 @ d0a9af80
......@@ -89,7 +89,7 @@ extern void __iomem *mstk48t02_regs;
#define MSTK_DOW_MASK 0x07
#define MSTK_DOM_MASK 0x3f
#define MSTK_MONTH_MASK 0x1f
#define MSTK_YEAR_MASK 0xff
#define MSTK_YEAR_MASK 0xffU
/* Binary coded decimal conversion macros. */
#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
......
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