提交 96983ffe 编写于 作者: K Kevin Cernekee 提交者: Ralf Baechle

MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.

This extends commit a8ca8b64 to cover
MIPSxx-style board cache code.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 a648e811
...@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size) ...@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
*/ */
static void mips_sc_inv(unsigned long addr, unsigned long size) static void mips_sc_inv(unsigned long addr, unsigned long size)
{ {
unsigned long lsize = cpu_scache_line_size();
unsigned long almask = ~(lsize - 1);
cache_op(Hit_Writeback_Inv_SD, addr & almask);
cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
blast_inv_scache_range(addr, addr + size); blast_inv_scache_range(addr, addr + size);
} }
......
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