提交 22b19086 编写于 作者: R Russell King 提交者: Russell King

[ARM] nommu: provide a way for correct control register value selection

Most MMU-based CPUs have a restriction on the setting of the data cache
enable and mmu enable bits in the control register, whereby if the data
cache is enabled, the MMU must also be enabled.  Enabling the data
cache without the MMU is an invalid combination.

However, there are CPUs where the data cache can be enabled without the
MMU.

In order to allow these CPUs to take advantage of that, provide a
method whereby each proc-*.S file defines the control regsiter value
for use with nommu (with the MMU disabled.)  Later on, when we add
support for enabling the MMU on these devices, we can adjust the
"crval" macro to also enable the data cache for nommu.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
上级 264edb35
...@@ -440,11 +440,12 @@ __arm1020_setup: ...@@ -440,11 +440,12 @@ __arm1020_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm1020_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1020_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1020_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.. .... .... .... orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif #endif
...@@ -456,12 +457,9 @@ __arm1020_setup: ...@@ -456,12 +457,9 @@ __arm1020_setup:
* .RVI ZFRS BLDP WCAM * .RVI ZFRS BLDP WCAM
* .011 1001 ..11 0101 * .011 1001 ..11 0101
*/ */
.type arm1020_cr1_clear, #object .type arm1020_crval, #object
.type arm1020_cr1_set, #object arm1020_crval:
arm1020_cr1_clear: crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
.word 0x593f
arm1020_cr1_set:
.word 0x3935
__INITDATA __INITDATA
......
...@@ -422,11 +422,11 @@ __arm1020e_setup: ...@@ -422,11 +422,11 @@ __arm1020e_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm1020e_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1020e_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1020e_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.. .... .... .... orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif #endif
...@@ -438,12 +438,9 @@ __arm1020e_setup: ...@@ -438,12 +438,9 @@ __arm1020e_setup:
* .RVI ZFRS BLDP WCAM * .RVI ZFRS BLDP WCAM
* .011 1001 ..11 0101 * .011 1001 ..11 0101
*/ */
.type arm1020e_cr1_clear, #object .type arm1020e_crval, #object
.type arm1020e_cr1_set, #object arm1020e_crval:
arm1020e_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
.word 0x5f3f
arm1020e_cr1_set:
.word 0x3935
__INITDATA __INITDATA
......
...@@ -404,11 +404,11 @@ __arm1022_setup: ...@@ -404,11 +404,11 @@ __arm1022_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm1022_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1022_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1022_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.............. orr r0, r0, #0x4000 @ .R..............
#endif #endif
...@@ -421,12 +421,9 @@ __arm1022_setup: ...@@ -421,12 +421,9 @@ __arm1022_setup:
* .011 1001 ..11 0101 * .011 1001 ..11 0101
* *
*/ */
.type arm1022_cr1_clear, #object .type arm1022_crval, #object
.type arm1022_cr1_set, #object arm1022_crval:
arm1022_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
.word 0x7f3f
arm1022_cr1_set:
.word 0x3935
__INITDATA __INITDATA
......
...@@ -399,11 +399,11 @@ __arm1026_setup: ...@@ -399,11 +399,11 @@ __arm1026_setup:
mov r0, #4 @ explicitly disable writeback mov r0, #4 @ explicitly disable writeback
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
adr r5, arm1026_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1026_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm1026_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R.. .... .... .... orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif #endif
...@@ -416,12 +416,9 @@ __arm1026_setup: ...@@ -416,12 +416,9 @@ __arm1026_setup:
* .011 1001 ..11 0101 * .011 1001 ..11 0101
* *
*/ */
.type arm1026_cr1_clear, #object .type arm1026_crval, #object
.type arm1026_cr1_set, #object arm1026_crval:
arm1026_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
.word 0x7f3f
arm1026_cr1_set:
.word 0x3935
__INITDATA __INITDATA
......
...@@ -169,11 +169,11 @@ __arm720_setup: ...@@ -169,11 +169,11 @@ __arm720_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
#endif #endif
adr r5, arm720_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm720_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm720_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr @ __ret (head.S) mov pc, lr @ __ret (head.S)
.size __arm720_setup, . - __arm720_setup .size __arm720_setup, . - __arm720_setup
...@@ -183,12 +183,9 @@ __arm720_setup: ...@@ -183,12 +183,9 @@ __arm720_setup:
* ..1. 1001 ..11 1101 * ..1. 1001 ..11 1101
* *
*/ */
.type arm720_cr1_clear, #object .type arm720_crval, #object
.type arm720_cr1_set, #object arm720_crval:
arm720_cr1_clear: crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
.word 0x2f3f
arm720_cr1_set:
.word 0x213d
__INITDATA __INITDATA
......
...@@ -391,11 +391,11 @@ __arm920_setup: ...@@ -391,11 +391,11 @@ __arm920_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm920_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm920_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm920_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __arm920_setup, . - __arm920_setup .size __arm920_setup, . - __arm920_setup
...@@ -405,12 +405,9 @@ __arm920_setup: ...@@ -405,12 +405,9 @@ __arm920_setup:
* ..11 0001 ..11 0101 * ..11 0001 ..11 0101
* *
*/ */
.type arm920_cr1_clear, #object .type arm920_crval, #object
.type arm920_cr1_set, #object arm920_crval:
arm920_cr1_clear: crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
.word 0x3f3f
arm920_cr1_set:
.word 0x3135
__INITDATA __INITDATA
......
...@@ -395,11 +395,11 @@ __arm922_setup: ...@@ -395,11 +395,11 @@ __arm922_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, arm922_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm922_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm922_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __arm922_setup, . - __arm922_setup .size __arm922_setup, . - __arm922_setup
...@@ -409,12 +409,9 @@ __arm922_setup: ...@@ -409,12 +409,9 @@ __arm922_setup:
* ..11 0001 ..11 0101 * ..11 0001 ..11 0101
* *
*/ */
.type arm922_cr1_clear, #object .type arm922_crval, #object
.type arm922_cr1_set, #object arm922_crval:
arm922_cr1_clear: crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
.word 0x3f3f
arm922_cr1_set:
.word 0x3135
__INITDATA __INITDATA
......
...@@ -455,11 +455,10 @@ __arm925_setup: ...@@ -455,11 +455,10 @@ __arm925_setup:
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
adr r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm925_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm925_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... .... orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif #endif
...@@ -472,12 +471,9 @@ __arm925_setup: ...@@ -472,12 +471,9 @@ __arm925_setup:
* .011 0001 ..11 1101 * .011 0001 ..11 1101
* *
*/ */
.type arm925_cr1_clear, #object .type arm925_crval, #object
.type arm925_cr1_set, #object arm925_crval:
arm925_cr1_clear: crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
.word 0x7f3f
arm925_cr1_set:
.word 0x313d
__INITDATA __INITDATA
......
...@@ -404,11 +404,11 @@ __arm926_setup: ...@@ -404,11 +404,11 @@ __arm926_setup:
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
adr r5, arm926_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm926_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, arm926_cr1_set orr r0, r0, r6
orr r0, r0, r5
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... .... orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif #endif
...@@ -421,12 +421,9 @@ __arm926_setup: ...@@ -421,12 +421,9 @@ __arm926_setup:
* .011 0001 ..11 0101 * .011 0001 ..11 0101
* *
*/ */
.type arm926_cr1_clear, #object .type arm926_crval, #object
.type arm926_cr1_set, #object arm926_crval:
arm926_cr1_clear: crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
.word 0x7f3f
arm926_cr1_set:
.word 0x3135
__INITDATA __INITDATA
......
...@@ -49,3 +49,13 @@ ...@@ -49,3 +49,13 @@
.macro asid, rd, rn .macro asid, rd, rn
and \rd, \rn, #255 and \rd, \rn, #255
.endm .endm
.macro crval, clear, mmuset, ucset
#ifdef CONFIG_MMU
.word \clear
.word \mmuset
#else
.word \clear
.word \ucset
#endif
.endm
...@@ -185,11 +185,12 @@ __sa110_setup: ...@@ -185,11 +185,12 @@ __sa110_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, sa110_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa110_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, sa110_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __sa110_setup, . - __sa110_setup .size __sa110_setup, . - __sa110_setup
...@@ -199,12 +200,9 @@ __sa110_setup: ...@@ -199,12 +200,9 @@ __sa110_setup:
* ..01 0001 ..11 1101 * ..01 0001 ..11 1101
* *
*/ */
.type sa110_cr1_clear, #object .type sa110_crval, #object
.type sa110_cr1_set, #object sa110_crval:
sa110_cr1_clear: crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
.word 0x3f3f
sa110_cr1_set:
.word 0x113d
__INITDATA __INITDATA
......
...@@ -198,11 +198,11 @@ __sa1100_setup: ...@@ -198,11 +198,11 @@ __sa1100_setup:
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
#endif #endif
adr r5, sa1100_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4 mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa1100_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, sa1100_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __sa1100_setup, . - __sa1100_setup .size __sa1100_setup, . - __sa1100_setup
...@@ -212,12 +212,9 @@ __sa1100_setup: ...@@ -212,12 +212,9 @@ __sa1100_setup:
* ..11 0001 ..11 1101 * ..11 0001 ..11 1101
* *
*/ */
.type sa1100_cr1_clear, #object .type sa1100_crval, #object
.type sa1100_cr1_set, #object sa1100_crval:
sa1100_cr1_clear: crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
.word 0x3f3f
sa1100_cr1_set:
.word 0x313d
__INITDATA __INITDATA
......
...@@ -212,11 +212,11 @@ __v6_setup: ...@@ -212,11 +212,11 @@ __v6_setup:
orr r0, r0, #(0xf << 20) orr r0, r0, #(0xf << 20)
mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
#endif #endif
adr r5, v6_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
ldr r5, v6_cr1_clear @ get mask for bits to clear
bic r0, r0, r5 @ clear bits them bic r0, r0, r5 @ clear bits them
ldr r5, v6_cr1_set @ get mask for bits to set orr r0, r0, r6 @ set them
orr r0, r0, r5 @ set them
mov pc, lr @ return to head.S:__ret mov pc, lr @ return to head.S:__ret
/* /*
...@@ -225,12 +225,9 @@ __v6_setup: ...@@ -225,12 +225,9 @@ __v6_setup:
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 0 110 0011 1.00 .111 1101 < we want * 0 110 0011 1.00 .111 1101 < we want
*/ */
.type v6_cr1_clear, #object .type v6_crval, #object
.type v6_cr1_set, #object v6_crval:
v6_cr1_clear: crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
.word 0x01e0fb7f
v6_cr1_set:
.word 0x00c0387d
.type v6_processor_functions, #object .type v6_processor_functions, #object
ENTRY(v6_processor_functions) ENTRY(v6_processor_functions)
......
...@@ -426,23 +426,26 @@ __xsc3_setup: ...@@ -426,23 +426,26 @@ __xsc3_setup:
orr r0, r0, #(1 << 10) @ enable L2 for LLR cache orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
#endif #endif
mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
adr r5, xsc3_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ get control register mrc p15, 0, r0, c1, c0, 0 @ get control register
bic r0, r0, #0x0002 @ .... .... .... ..A. bic r0, r0, r5 @ .... .... .... ..A.
orr r0, r0, #0x0005 @ .... .... .... .C.M orr r0, r0, r6 @ .... .... .... .C.M
#if BTB_ENABLE #if BTB_ENABLE
bic r0, r0, #0x0200 @ .... ..R. .... .... orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
orr r0, r0, #0x3900 @ ..VI Z..S .... ....
#else
bic r0, r0, #0x0a00 @ .... Z.R. .... ....
orr r0, r0, #0x3100 @ ..VI ...S .... ....
#endif #endif
#if L2_CACHE_ENABLE #if L2_CACHE_ENABLE
orr r0, r0, #0x4000000 @ L2 enable orr r0, r0, #0x04000000 @ L2 enable
#endif #endif
mov pc, lr mov pc, lr
.size __xsc3_setup, . - __xsc3_setup .size __xsc3_setup, . - __xsc3_setup
.type xsc3_crval, #object
xsc3_crval:
crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
__INITDATA __INITDATA
/* /*
......
...@@ -475,11 +475,12 @@ __xscale_setup: ...@@ -475,11 +475,12 @@ __xscale_setup:
orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
orr r0, r0, #1 << 13 @ Its undefined whether this orr r0, r0, #1 << 13 @ Its undefined whether this
mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
adr r5, xscale_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ get control register mrc p15, 0, r0, c1, c0, 0 @ get control register
ldr r5, xscale_cr1_clear
bic r0, r0, r5 bic r0, r0, r5
ldr r5, xscale_cr1_set orr r0, r0, r6
orr r0, r0, r5
mov pc, lr mov pc, lr
.size __xscale_setup, . - __xscale_setup .size __xscale_setup, . - __xscale_setup
...@@ -489,12 +490,9 @@ __xscale_setup: ...@@ -489,12 +490,9 @@ __xscale_setup:
* ..11 1.01 .... .101 * ..11 1.01 .... .101
* *
*/ */
.type xscale_cr1_clear, #object .type xscale_crval, #object
.type xscale_cr1_set, #object xscale_crval:
xscale_cr1_clear: crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
.word 0x3b07
xscale_cr1_set:
.word 0x3905
__INITDATA __INITDATA
......
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