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提交 21d437cc 编写于 作者: G Giuseppe CAVALLARO 提交者： David S. Miller
浏览文件
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stmmac: rename the gmac as dwmac1000 and split core and dma parts 

Use dwmac1000 naming instead of gmac.
The patch also splits the gmac.c file in two new ones:
dwmac1000_core.c and dwmac1000_dma.c.
This could actually help on some architectures where different
DMA engines are used.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
上级 7e848ae1
隐藏空白更改
内联 并排
Showing with 324 addition and 287 deletion
drivers/net/stmmac/Makefile
浏览文件 @ 21d437cc
obj-$(CONFIG_STMMAC_ETH) += stmmac.o obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o dwmac_lib.o \ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o \
dwmac100.o gmac.o $(stmmac-y) dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100.o $(stmmac-y)
drivers/net/stmmac/common.h
浏览文件 @ 21d437cc
...@@ -224,7 +224,7 @@ struct mac_device_info { ...@@ -224,7 +224,7 @@ struct mac_device_info {
struct mac_link link; struct mac_link link;
}; };
struct mac_device_info *gmac_setup(unsigned long addr); struct mac_device_info *dwmac1000_setup(unsigned long addr);
struct mac_device_info *dwmac100_setup(unsigned long addr); struct mac_device_info *dwmac100_setup(unsigned long addr);
extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
......
drivers/net/stmmac/descs.h
浏览文件 @ 21d437cc
/******************************************************************************* /*******************************************************************************
Header File to describe the DMA descriptors Header File to describe the DMA descriptors.
Use enhanced descriptors in case of GMAC Cores. Enhanced descriptors have been in case of DWMAC1000 Cores.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
......
drivers/net/stmmac/gmac.h → drivers/net/stmmac/dwmac1000.h
浏览文件 @ 21d437cc
...@@ -20,6 +20,10 @@ ...@@ -20,6 +20,10 @@
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/ *******************************************************************************/
#include <linux/netdevice.h>
#include <linux/phy.h>
#include "common.h"
#define GMAC_CONTROL 0x00000000 /* Configuration */ #define GMAC_CONTROL 0x00000000 /* Configuration */
#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
...@@ -32,7 +36,7 @@ ...@@ -32,7 +36,7 @@
#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
enum gmac_irq_status { enum dwmac1000_irq_status {
time_stamp_irq = 0x0200, time_stamp_irq = 0x0200,
mmc_rx_csum_offload_irq = 0x0080, mmc_rx_csum_offload_irq = 0x0080,
mmc_tx_irq = 0x0040, mmc_tx_irq = 0x0040,
...@@ -202,3 +206,16 @@ enum rtc_control { ...@@ -202,3 +206,16 @@ enum rtc_control {
#define GMAC_MMC_RX_INTR 0x104 #define GMAC_MMC_RX_INTR 0x104
#define GMAC_MMC_TX_INTR 0x108 #define GMAC_MMC_TX_INTR 0x108
#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
#undef DWMAC1000_DEBUG
/* #define DWMAC1000__DEBUG */
#undef FRAME_FILTER_DEBUG
/* #define FRAME_FILTER_DEBUG */
#ifdef DWMAC1000__DEBUG
#define DBG(fmt, args...) printk(fmt, ## args)
#else
#define DBG(fmt, args...) do { } while (0)
#endif
extern struct stmmac_dma_ops dwmac1000_dma_ops;
extern struct stmmac_desc_ops dwmac1000_desc_ops;
drivers/net/stmmac/dwmac1000_core.c 0 → 100644
浏览文件 @ 21d437cc
/*******************************************************************************
This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
developing this code.
This only implements the mac core functions for this chip.
Copyright (C) 2007-2009 STMicroelectronics Ltd
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
version 2, as published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
The full GNU General Public License is included in this distribution in
the file called "COPYING".
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/
#include <linux/crc32.h>
#include "dwmac1000.h"
static void dwmac1000_core_init(unsigned long ioaddr)
{
u32 value = readl(ioaddr + GMAC_CONTROL);
value |= GMAC_CORE_INIT;
writel(value, ioaddr + GMAC_CONTROL);
/* STBus Bridge Configuration */
/*writel(0xc5608, ioaddr + 0x00007000);*/
/* Freeze MMC counters */
writel(0x8, ioaddr + GMAC_MMC_CTRL);
/* Mask GMAC interrupts */
writel(0x207, ioaddr + GMAC_INT_MASK);
#ifdef STMMAC_VLAN_TAG_USED
/* Tag detection without filtering */
writel(0x0, ioaddr + GMAC_VLAN_TAG);
#endif
return;
}
static void dwmac1000_dump_regs(unsigned long ioaddr)
{
int i;
pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr);
for (i = 0; i < 55; i++) {
int offset = i * 4;
pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
offset, readl(ioaddr + offset));
}
return;
}
static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
unsigned int reg_n)
{
stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
GMAC_ADDR_LOW(reg_n));
}
static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
unsigned int reg_n)
{
stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
GMAC_ADDR_LOW(reg_n));
}
static void dwmac1000_set_filter(struct net_device *dev)
{
unsigned long ioaddr = dev->base_addr;
unsigned int value = 0;
DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
__func__, dev->mc_count, dev->uc.count);
if (dev->flags & IFF_PROMISC)
value = GMAC_FRAME_FILTER_PR;
else if ((dev->mc_count > HASH_TABLE_SIZE)
|| (dev->flags & IFF_ALLMULTI)) {
value = GMAC_FRAME_FILTER_PM; /* pass all multi */
writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
} else if (dev->mc_count > 0) {
int i;
u32 mc_filter[2];
struct dev_mc_list *mclist;
/* Hash filter for multicast */
value = GMAC_FRAME_FILTER_HMC;
memset(mc_filter, 0, sizeof(mc_filter));
for (i = 0, mclist = dev->mc_list;
mclist && i < dev->mc_count; i++, mclist = mclist->next) {
/* The upper 6 bits of the calculated CRC are used to
index the contens of the hash table */
int bit_nr =
bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
/* The most significant bit determines the register to
* use (H/L) while the other 5 bits determine the bit
* within the register. */
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
}
writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
}
/* Handle multiple unicast addresses (perfect filtering)*/
if (dev->uc.count > GMAC_MAX_UNICAST_ADDRESSES)
/* Switch to promiscuous mode is more than 16 addrs
are required */
value |= GMAC_FRAME_FILTER_PR;
else {
int reg = 1;
struct netdev_hw_addr *ha;
list_for_each_entry(ha, &dev->uc.list, list) {
dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
reg++;
}
}
#ifdef FRAME_FILTER_DEBUG
/* Enable Receive all mode (to debug filtering_fail errors) */
value |= GMAC_FRAME_FILTER_RA;
#endif
writel(value, ioaddr + GMAC_FRAME_FILTER);
DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
return;
}
static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
unsigned int fc, unsigned int pause_time)
{
unsigned int flow = 0;
DBG(KERN_DEBUG "GMAC Flow-Control:\n");
if (fc & FLOW_RX) {
DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
flow |= GMAC_FLOW_CTRL_RFE;
}
if (fc & FLOW_TX) {
DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
flow |= GMAC_FLOW_CTRL_TFE;
}
if (duplex) {
DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
}
writel(flow, ioaddr + GMAC_FLOW_CTRL);
return;
}
static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
{
unsigned int pmt = 0;
if (mode == WAKE_MAGIC) {
DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
pmt |= power_down | magic_pkt_en;
} else if (mode == WAKE_UCAST) {
DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
pmt |= global_unicast;
}
writel(pmt, ioaddr + GMAC_PMT);
return;
}
static void dwmac1000_irq_status(unsigned long ioaddr)
{
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
/* Not used events (e.g. MMC interrupts) are not handled. */
if ((intr_status & mmc_tx_irq))
DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
readl(ioaddr + GMAC_MMC_TX_INTR));
if (unlikely(intr_status & mmc_rx_irq))
DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
readl(ioaddr + GMAC_MMC_RX_INTR));
if (unlikely(intr_status & mmc_rx_csum_offload_irq))
DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
if (unlikely(intr_status & pmt_irq)) {
DBG(KERN_DEBUG "GMAC: received Magic frame\n");
/* clear the PMT bits 5 and 6 by reading the PMT
* status register. */
readl(ioaddr + GMAC_PMT);
}
return;
}
struct stmmac_ops dwmac1000_ops = {
.core_init = dwmac1000_core_init,
.dump_regs = dwmac1000_dump_regs,
.host_irq_status = dwmac1000_irq_status,
.set_filter = dwmac1000_set_filter,
.flow_ctrl = dwmac1000_flow_ctrl,
.pmt = dwmac1000_pmt,
.set_umac_addr = dwmac1000_set_umac_addr,
.get_umac_addr = dwmac1000_get_umac_addr,
};
struct mac_device_info *dwmac1000_setup(unsigned long ioaddr)
{
struct mac_device_info *mac;
u32 uid = readl(ioaddr + GMAC_VERSION);
pr_info("\tDWMAC1000 - user ID: 0x%x, Synopsys ID: 0x%x\n",
((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
mac->mac = &dwmac1000_ops;
mac->desc = &dwmac1000_desc_ops;
mac->dma = &dwmac1000_dma_ops;
mac->pmt = PMT_SUPPORTED;
mac->link.port = GMAC_CONTROL_PS;
mac->link.duplex = GMAC_CONTROL_DM;
mac->link.speed = GMAC_CONTROL_FES;
mac->mii.addr = GMAC_MII_ADDR;
mac->mii.data = GMAC_MII_DATA;
return mac;
}
drivers/net/stmmac/gmac.c → drivers/net/stmmac/dwmac1000_dma.c
浏览文件 @ 21d437cc
...@@ -3,6 +3,8 @@ ...@@ -3,6 +3,8 @@
DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
developing this code. developing this code.
This contains the functions to handle the dma and descriptors.
Copyright (C) 2007-2009 STMicroelectronics Ltd Copyright (C) 2007-2009 STMicroelectronics Ltd
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
...@@ -24,42 +26,11 @@ ...@@ -24,42 +26,11 @@
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/ *******************************************************************************/
#include <linux/netdevice.h> #include "dwmac1000.h"
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include "stmmac.h"
#include "gmac.h"
#include "dwmac_dma.h" #include "dwmac_dma.h"
#undef GMAC_DEBUG static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
/*#define GMAC_DEBUG*/ u32 dma_rx)
#undef FRAME_FILTER_DEBUG
/*#define FRAME_FILTER_DEBUG*/
#ifdef GMAC_DEBUG
#define DBG(fmt, args...) printk(fmt, ## args)
#else
#define DBG(fmt, args...) do { } while (0)
#endif
static void gmac_dump_regs(unsigned long ioaddr)
{
int i;
pr_info("\t----------------------------------------------\n"
"\t GMAC registers (base addr = 0x%8x)\n"
"\t----------------------------------------------\n",
(unsigned int)ioaddr);
for (i = 0; i < 55; i++) {
int offset = i * 4;
pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
offset, readl(ioaddr + offset));
}
return;
}
static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx)
{ {
u32 value = readl(ioaddr + DMA_BUS_MODE); u32 value = readl(ioaddr + DMA_BUS_MODE);
/* DMA SW reset */ /* DMA SW reset */
...@@ -88,7 +59,7 @@ static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx) ...@@ -88,7 +59,7 @@ static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx)
} }
/* Transmit FIFO flush operation */ /* Transmit FIFO flush operation */
static void gmac_flush_tx_fifo(unsigned long ioaddr) static void dwmac1000_flush_tx_fifo(unsigned long ioaddr)
{ {
u32 csr6 = readl(ioaddr + DMA_CONTROL); u32 csr6 = readl(ioaddr + DMA_CONTROL);
writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
...@@ -96,7 +67,7 @@ static void gmac_flush_tx_fifo(unsigned long ioaddr) ...@@ -96,7 +67,7 @@ static void gmac_flush_tx_fifo(unsigned long ioaddr)
do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
} }
static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode, static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
int rxmode) int rxmode)
{ {
u32 csr6 = readl(ioaddr + DMA_CONTROL); u32 csr6 = readl(ioaddr + DMA_CONTROL);
...@@ -149,13 +120,13 @@ static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode, ...@@ -149,13 +120,13 @@ static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode,
} }
/* Not yet implemented --- no RMON module */ /* Not yet implemented --- no RMON module */
static void gmac_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, static void dwmac1000_dma_diagnostic_fr(void *data,
unsigned long ioaddr) struct stmmac_extra_stats *x, unsigned long ioaddr)
{ {
return; return;
} }
static void gmac_dump_dma_regs(unsigned long ioaddr) static void dwmac1000_dump_dma_regs(unsigned long ioaddr)
{ {
int i; int i;
pr_info(" DMA registers\n"); pr_info(" DMA registers\n");
...@@ -170,8 +141,9 @@ static void gmac_dump_dma_regs(unsigned long ioaddr) ...@@ -170,8 +141,9 @@ static void gmac_dump_dma_regs(unsigned long ioaddr)
return; return;
} }
static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, static int dwmac1000_get_tx_frame_status(void *data,
struct dma_desc *p, unsigned long ioaddr) struct stmmac_extra_stats *x,
struct dma_desc *p, unsigned long ioaddr)
{ {
int ret = 0; int ret = 0;
struct net_device_stats *stats = (struct net_device_stats *)data; struct net_device_stats *stats = (struct net_device_stats *)data;
...@@ -186,7 +158,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, ...@@ -186,7 +158,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
if (unlikely(p->des01.etx.frame_flushed)) { if (unlikely(p->des01.etx.frame_flushed)) {
DBG(KERN_ERR "\tframe_flushed error\n"); DBG(KERN_ERR "\tframe_flushed error\n");
x->tx_frame_flushed++; x->tx_frame_flushed++;
gmac_flush_tx_fifo(ioaddr); dwmac1000_flush_tx_fifo(ioaddr);
} }
if (unlikely(p->des01.etx.loss_carrier)) { if (unlikely(p->des01.etx.loss_carrier)) {
...@@ -214,7 +186,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, ...@@ -214,7 +186,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
if (unlikely(p->des01.etx.underflow_error)) { if (unlikely(p->des01.etx.underflow_error)) {
DBG(KERN_ERR "\tunderflow error\n"); DBG(KERN_ERR "\tunderflow error\n");
gmac_flush_tx_fifo(ioaddr); dwmac1000_flush_tx_fifo(ioaddr);
x->tx_underflow++; x->tx_underflow++;
} }
...@@ -226,7 +198,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, ...@@ -226,7 +198,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
if (unlikely(p->des01.etx.payload_error)) { if (unlikely(p->des01.etx.payload_error)) {
DBG(KERN_ERR "\tAddr/Payload csum error\n"); DBG(KERN_ERR "\tAddr/Payload csum error\n");
x->tx_payload_error++; x->tx_payload_error++;
gmac_flush_tx_fifo(ioaddr); dwmac1000_flush_tx_fifo(ioaddr);
} }
ret = -1; ret = -1;
...@@ -246,12 +218,12 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, ...@@ -246,12 +218,12 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
return ret; return ret;
} }
static int gmac_get_tx_len(struct dma_desc *p) static int dwmac1000_get_tx_len(struct dma_desc *p)
{ {
return p->des01.etx.buffer1_size; return p->des01.etx.buffer1_size;
} }
static int gmac_coe_rdes0(int ipc_err, int type, int payload_err) static int dwmac1000_coe_rdes0(int ipc_err, int type, int payload_err)
{ {
int ret = good_frame; int ret = good_frame;
u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7; u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
...@@ -294,8 +266,8 @@ static int gmac_coe_rdes0(int ipc_err, int type, int payload_err) ...@@ -294,8 +266,8 @@ static int gmac_coe_rdes0(int ipc_err, int type, int payload_err)
return ret; return ret;
} }
static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x, static int dwmac1000_get_rx_frame_status(void *data,
struct dma_desc *p) struct stmmac_extra_stats *x, struct dma_desc *p)
{ {
int ret = good_frame; int ret = good_frame;
struct net_device_stats *stats = (struct net_device_stats *)data; struct net_device_stats *stats = (struct net_device_stats *)data;
...@@ -340,7 +312,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x, ...@@ -340,7 +312,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
* It doesn't match with the information reported into the databook. * It doesn't match with the information reported into the databook.
* At any rate, we need to understand if the CSUM hw computation is ok * At any rate, we need to understand if the CSUM hw computation is ok
* and report this info to the upper layers. */ * and report this info to the upper layers. */
ret = gmac_coe_rdes0(p->des01.erx.ipc_csum_error, ret = dwmac1000_coe_rdes0(p->des01.erx.ipc_csum_error,
p->des01.erx.frame_type, p->des01.erx.payload_csum_error); p->des01.erx.frame_type, p->des01.erx.payload_csum_error);
if (unlikely(p->des01.erx.dribbling)) { if (unlikely(p->des01.erx.dribbling)) {
...@@ -371,170 +343,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x, ...@@ -371,170 +343,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
return ret; return ret;
} }
static void gmac_irq_status(unsigned long ioaddr) static void dwmac1000_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
{
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
/* Not used events (e.g. MMC interrupts) are not handled. */
if ((intr_status & mmc_tx_irq))
DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
readl(ioaddr + GMAC_MMC_TX_INTR));
if (unlikely(intr_status & mmc_rx_irq))
DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
readl(ioaddr + GMAC_MMC_RX_INTR));
if (unlikely(intr_status & mmc_rx_csum_offload_irq))
DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
if (unlikely(intr_status & pmt_irq)) {
DBG(KERN_DEBUG "GMAC: received Magic frame\n");
/* clear the PMT bits 5 and 6 by reading the PMT
* status register. */
readl(ioaddr + GMAC_PMT);
}
return;
}
static void gmac_core_init(unsigned long ioaddr)
{
u32 value = readl(ioaddr + GMAC_CONTROL);
value |= GMAC_CORE_INIT;
writel(value, ioaddr + GMAC_CONTROL);
/* Freeze MMC counters */
writel(0x8, ioaddr + GMAC_MMC_CTRL);
/* Mask GMAC interrupts */
writel(0x207, ioaddr + GMAC_INT_MASK);
#ifdef STMMAC_VLAN_TAG_USED
/* Tag detection without filtering */
writel(0x0, ioaddr + GMAC_VLAN_TAG);
#endif
return;
}
static void gmac_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
unsigned int reg_n)
{
stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
GMAC_ADDR_LOW(reg_n));
}
static void gmac_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
unsigned int reg_n)
{
stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
GMAC_ADDR_LOW(reg_n));
}
static void gmac_set_filter(struct net_device *dev)
{
unsigned long ioaddr = dev->base_addr;
unsigned int value = 0;
DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
__func__, dev->mc_count, dev->uc.count);
if (dev->flags & IFF_PROMISC)
value = GMAC_FRAME_FILTER_PR;
else if ((dev->mc_count > HASH_TABLE_SIZE)
|| (dev->flags & IFF_ALLMULTI)) {
value = GMAC_FRAME_FILTER_PM; /* pass all multi */
writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
} else if (dev->mc_count > 0) {
int i;
u32 mc_filter[2];
struct dev_mc_list *mclist;
/* Hash filter for multicast */
value = GMAC_FRAME_FILTER_HMC;
memset(mc_filter, 0, sizeof(mc_filter));
for (i = 0, mclist = dev->mc_list;
mclist && i < dev->mc_count; i++, mclist = mclist->next) {
/* The upper 6 bits of the calculated CRC are used to
index the contens of the hash table */
int bit_nr =
bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
/* The most significant bit determines the register to
* use (H/L) while the other 5 bits determine the bit
* within the register. */
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
}
writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
}
/* Handle multiple unicast addresses (perfect filtering)*/
if (dev->uc.count > GMAC_MAX_UNICAST_ADDRESSES)
/* Switch to promiscuous mode is more than 16 addrs
are required */
value |= GMAC_FRAME_FILTER_PR;
else {
int reg = 1;
struct netdev_hw_addr *ha;
list_for_each_entry(ha, &dev->uc.list, list) {
gmac_set_umac_addr(ioaddr, ha->addr, reg);
reg++;
}
}
#ifdef FRAME_FILTER_DEBUG
/* Enable Receive all mode (to debug filtering_fail errors) */
value |= GMAC_FRAME_FILTER_RA;
#endif
writel(value, ioaddr + GMAC_FRAME_FILTER);
DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
return;
}
static void gmac_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
unsigned int fc, unsigned int pause_time)
{
unsigned int flow = 0;
DBG(KERN_DEBUG "GMAC Flow-Control:\n");
if (fc & FLOW_RX) {
DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
flow |= GMAC_FLOW_CTRL_RFE;
}
if (fc & FLOW_TX) {
DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
flow |= GMAC_FLOW_CTRL_TFE;
}
if (duplex) {
DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
}
writel(flow, ioaddr + GMAC_FLOW_CTRL);
return;
}
static void gmac_pmt(unsigned long ioaddr, unsigned long mode)
{
unsigned int pmt = 0;
if (mode == WAKE_MAGIC) {
DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
pmt |= power_down | magic_pkt_en;
} else if (mode == WAKE_UCAST) {
DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
pmt |= global_unicast;
}
writel(pmt, ioaddr + GMAC_PMT);
return;
}
static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
int disable_rx_ic) int disable_rx_ic)
{ {
int i; int i;
...@@ -552,7 +361,7 @@ static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size, ...@@ -552,7 +361,7 @@ static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
return; return;
} }
static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size) static void dwmac1000_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
{ {
int i; int i;
...@@ -566,32 +375,32 @@ static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size) ...@@ -566,32 +375,32 @@ static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
return; return;
} }
static int gmac_get_tx_owner(struct dma_desc *p) static int dwmac1000_get_tx_owner(struct dma_desc *p)
{ {
return p->des01.etx.own; return p->des01.etx.own;
} }
static int gmac_get_rx_owner(struct dma_desc *p) static int dwmac1000_get_rx_owner(struct dma_desc *p)
{ {
return p->des01.erx.own; return p->des01.erx.own;
} }
static void gmac_set_tx_owner(struct dma_desc *p) static void dwmac1000_set_tx_owner(struct dma_desc *p)
{ {
p->des01.etx.own = 1; p->des01.etx.own = 1;
} }
static void gmac_set_rx_owner(struct dma_desc *p) static void dwmac1000_set_rx_owner(struct dma_desc *p)
{ {
p->des01.erx.own = 1; p->des01.erx.own = 1;
} }
static int gmac_get_tx_ls(struct dma_desc *p) static int dwmac1000_get_tx_ls(struct dma_desc *p)
{ {
return p->des01.etx.last_segment; return p->des01.etx.last_segment;
} }
static void gmac_release_tx_desc(struct dma_desc *p) static void dwmac1000_release_tx_desc(struct dma_desc *p)
{ {
int ter = p->des01.etx.end_ring; int ter = p->des01.etx.end_ring;
...@@ -601,7 +410,7 @@ static void gmac_release_tx_desc(struct dma_desc *p) ...@@ -601,7 +410,7 @@ static void gmac_release_tx_desc(struct dma_desc *p)
return; return;
} }
static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, static void dwmac1000_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
int csum_flag) int csum_flag)
{ {
p->des01.etx.first_segment = is_fs; p->des01.etx.first_segment = is_fs;
...@@ -615,38 +424,27 @@ static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, ...@@ -615,38 +424,27 @@ static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
p->des01.etx.checksum_insertion = cic_full; p->des01.etx.checksum_insertion = cic_full;
} }
static void gmac_clear_tx_ic(struct dma_desc *p) static void dwmac1000_clear_tx_ic(struct dma_desc *p)
{ {
p->des01.etx.interrupt = 0; p->des01.etx.interrupt = 0;
} }
static void gmac_close_tx_desc(struct dma_desc *p) static void dwmac1000_close_tx_desc(struct dma_desc *p)
{ {
p->des01.etx.last_segment = 1; p->des01.etx.last_segment = 1;
p->des01.etx.interrupt = 1; p->des01.etx.interrupt = 1;
} }
static int gmac_get_rx_frame_len(struct dma_desc *p) static int dwmac1000_get_rx_frame_len(struct dma_desc *p)
{ {
return p->des01.erx.frame_length; return p->des01.erx.frame_length;
} }
struct stmmac_ops gmac_ops = { struct stmmac_dma_ops dwmac1000_dma_ops = {
.core_init = gmac_core_init, .init = dwmac1000_dma_init,
.dump_regs = gmac_dump_regs, .dump_regs = dwmac1000_dump_dma_regs,
.host_irq_status = gmac_irq_status, .dma_mode = dwmac1000_dma_operation_mode,
.set_filter = gmac_set_filter, .dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
.flow_ctrl = gmac_flow_ctrl,
.pmt = gmac_pmt,
.set_umac_addr = gmac_set_umac_addr,
.get_umac_addr = gmac_get_umac_addr,
};
struct stmmac_dma_ops gmac_dma_ops = {
.init = gmac_dma_init,
.dump_regs = gmac_dump_dma_regs,
.dma_mode = gmac_dma_operation_mode,
.dma_diagnostic_fr = gmac_dma_diagnostic_fr,
.enable_dma_transmission = dwmac_enable_dma_transmission, .enable_dma_transmission = dwmac_enable_dma_transmission,
.enable_dma_irq = dwmac_enable_dma_irq, .enable_dma_irq = dwmac_enable_dma_irq,
.disable_dma_irq = dwmac_disable_dma_irq, .disable_dma_irq = dwmac_disable_dma_irq,
...@@ -657,44 +455,20 @@ struct stmmac_dma_ops gmac_dma_ops = { ...@@ -657,44 +455,20 @@ struct stmmac_dma_ops gmac_dma_ops = {
.dma_interrupt = dwmac_dma_interrupt, .dma_interrupt = dwmac_dma_interrupt,
}; };
struct stmmac_desc_ops gmac_desc_ops = { struct stmmac_desc_ops dwmac1000_desc_ops = {
.tx_status = gmac_get_tx_frame_status, .tx_status = dwmac1000_get_tx_frame_status,
.rx_status = gmac_get_rx_frame_status, .rx_status = dwmac1000_get_rx_frame_status,
.get_tx_len = gmac_get_tx_len, .get_tx_len = dwmac1000_get_tx_len,
.init_rx_desc = gmac_init_rx_desc, .init_rx_desc = dwmac1000_init_rx_desc,
.init_tx_desc = gmac_init_tx_desc, .init_tx_desc = dwmac1000_init_tx_desc,
.get_tx_owner = gmac_get_tx_owner, .get_tx_owner = dwmac1000_get_tx_owner,
.get_rx_owner = gmac_get_rx_owner, .get_rx_owner = dwmac1000_get_rx_owner,
.release_tx_desc = gmac_release_tx_desc, .release_tx_desc = dwmac1000_release_tx_desc,
.prepare_tx_desc = gmac_prepare_tx_desc, .prepare_tx_desc = dwmac1000_prepare_tx_desc,
.clear_tx_ic = gmac_clear_tx_ic, .clear_tx_ic = dwmac1000_clear_tx_ic,
.close_tx_desc = gmac_close_tx_desc, .close_tx_desc = dwmac1000_close_tx_desc,
.get_tx_ls = gmac_get_tx_ls, .get_tx_ls = dwmac1000_get_tx_ls,
.set_tx_owner = gmac_set_tx_owner, .set_tx_owner = dwmac1000_set_tx_owner,
.set_rx_owner = gmac_set_rx_owner, .set_rx_owner = dwmac1000_set_rx_owner,
.get_rx_frame_len = gmac_get_rx_frame_len, .get_rx_frame_len = dwmac1000_get_rx_frame_len,
}; };
struct mac_device_info *gmac_setup(unsigned long ioaddr)
{
struct mac_device_info *mac;
u32 uid = readl(ioaddr + GMAC_VERSION);
pr_info("\tGMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
mac->mac = &gmac_ops;
mac->desc = &gmac_desc_ops;
mac->dma = &gmac_dma_ops;
mac->pmt = PMT_SUPPORTED;
mac->link.port = GMAC_CONTROL_PS;
mac->link.duplex = GMAC_CONTROL_DM;
mac->link.speed = GMAC_CONTROL_FES;
mac->mii.addr = GMAC_MII_ADDR;
mac->mii.data = GMAC_MII_DATA;
return mac;
}
drivers/net/stmmac/stmmac_main.c
浏览文件 @ 21d437cc
...@@ -1583,7 +1583,7 @@ static int stmmac_mac_device_setup(struct net_device *dev) ...@@ -1583,7 +1583,7 @@ static int stmmac_mac_device_setup(struct net_device *dev)
struct mac_device_info *device; struct mac_device_info *device;
if (priv->is_gmac) if (priv->is_gmac)
device = gmac_setup(ioaddr); device = dwmac1000_setup(ioaddr);
else else
device = dwmac100_setup(ioaddr); device = dwmac100_setup(ioaddr);
......
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