• C
    drm/i915: Only enforce fence limits inside the GTT. · a00b10c3
    Chris Wilson 提交于
    So long as we adhere to the fence registers rules for alignment and no
    overlaps (including with unfenced accesses to linear memory) and account
    for the tiled access in our size allocation, we do not have to allocate
    the full fenced region for the object. This allows us to fight the bloat
    tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside
    the GTT we still suffer the additional alignment constraints, so it doesn't
    magic allow us to render larger scenes without stalls -- we need the
    expanded GTT and fence pipelining to overcome those...]
    Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
    a00b10c3
i915_drv.h 38.6 KB