• M
    ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex · 2c32c65e
    Mark Rutland 提交于
    On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may
    falsely trigger a watchpoint exception, leading to potential data aborts
    during exception return and/or livelock.
    
    This patch resolves the issue in the following ways:
    
      - Replacing our uses of CLREX with a dummy STREX sequence instead (as
        we did for v6 CPUs).
    
      - Removing the clrex code from v7_exit_coherency_flush and derivatives,
        since this only exists as a minor performance improvement when
        non-cached exclusives are in use (Linux doesn't use these).
    
    Benchmarking on a variety of ARM cores revealed no measurable
    performance difference with this change applied, so the change is
    performed unconditionally and no new Kconfig entry is added.
    Signed-off-by: NMark Rutland <mark.rutland@arm.com>
    Signed-off-by: NWill Deacon <will.deacon@arm.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
    2c32c65e
cacheflush.h 15.9 KB