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    [ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2) · 905a09d5
    Eric Miao 提交于
    (20072fd0 lost most of its changes
    somehow, came from a mbox archive applied with git-am.  No idea
    what happened.  This puts back the missing bits.  --rmk)
    
    The initial patch from Lothar, and Lennert make it into a cleaner
    one, modified and tested on PXA320 by Eric Miao.
    
    This patch moves the L2 cache operations out of proc-xsc3.S into
    dedicated outer cache support code.
    
    CACHE_XSC3L2 can be deselected so no L2 cache specific code will be
    linked in, and that L2 enable bit will not be set, this applies to
    the following cases:
    
        a. _only_ PXA300/PXA310 support included and no L2 cache wanted
        b. PXA320 support included, but want L2 be disabled
    
    So the enabling of L2 depends on two things:
    
        - CACHE_XSC3L2 is selected
        - and L2 cache is present
    
    Where the latter is only a safeguard (previous testing shows it works
    OK even when this bit is turned on).
    
    IXP series of processors with XScale3 cannot disable L2 cache for the
    moment since they depend on the L2 cache for its coherent memory, so
    IXP may always select CACHE_XSC3L2.
    
    Other L2 relevant bits are always turned on (i.e. the original code
    enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side
    effects. Specifically, these bits are:
    
       - OC bits in TTBASE register (table walk outer cache attributes)
       - LLR Outer Cache Attributes (OC) in Auxiliary Control Register
    Signed-off-by: NLothar WaÃ&lt;9f&gt;mann <LW@KARO-electronics.de>
    Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
    Signed-off-by: NEric Miao <eric.miao@marvell.com>
    Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
    905a09d5
proc-xsc3.S 12.2 KB