svm.c 44.9 KB
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/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * AMD SVM support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

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#include "kvm_svm.h"
#include "x86_emulate.h"

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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/vmalloc.h>
#include <linux/highmem.h>
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#include <linux/profile.h>
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#include <linux/sched.h>
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#include <asm/desc.h>
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MODULE_AUTHOR("Qumranet");
MODULE_LICENSE("GPL");

#define IOPM_ALLOC_ORDER 2
#define MSRPM_ALLOC_ORDER 1

#define DB_VECTOR 1
#define UD_VECTOR 6
#define GP_VECTOR 13

#define DR7_GD_MASK (1 << 13)
#define DR6_BD_MASK (1 << 13)

#define SEG_TYPE_LDT 2
#define SEG_TYPE_BUSY_TSS16 3

#define KVM_EFER_LMA (1 << 10)
#define KVM_EFER_LME (1 << 8)

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#define SVM_FEATURE_NPT  (1 << 0)
#define SVM_FEATURE_LBRV (1 << 1)
#define SVM_DEATURE_SVML (1 << 2)

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static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
{
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	return container_of(vcpu, struct vcpu_svm, vcpu);
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}

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unsigned long iopm_base;
unsigned long msrpm_base;

struct kvm_ldttss_desc {
	u16 limit0;
	u16 base0;
	unsigned base1 : 8, type : 5, dpl : 2, p : 1;
	unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
	u32 base3;
	u32 zero1;
} __attribute__((packed));

struct svm_cpu_data {
	int cpu;

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	u64 asid_generation;
	u32 max_asid;
	u32 next_asid;
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	struct kvm_ldttss_desc *tss_desc;

	struct page *save_area;
};

static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
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static uint32_t svm_features;
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struct svm_init_data {
	int cpu;
	int r;
};

static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};

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#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
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#define MSRS_RANGE_SIZE 2048
#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)

#define MAX_INST_SIZE 15

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static inline u32 svm_has(u32 feat)
{
	return svm_features & feat;
}

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static unsigned get_addr_size(struct vcpu_svm *svm)
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{
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	struct vmcb_save_area *sa = &svm->vmcb->save;
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	u16 cs_attrib;

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	if (!(sa->cr0 & X86_CR0_PE) || (sa->rflags & X86_EFLAGS_VM))
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		return 2;

	cs_attrib = sa->cs.attrib;

	return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
				(cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
}

static inline u8 pop_irq(struct kvm_vcpu *vcpu)
{
	int word_index = __ffs(vcpu->irq_summary);
	int bit_index = __ffs(vcpu->irq_pending[word_index]);
	int irq = word_index * BITS_PER_LONG + bit_index;

	clear_bit(bit_index, &vcpu->irq_pending[word_index]);
	if (!vcpu->irq_pending[word_index])
		clear_bit(word_index, &vcpu->irq_summary);
	return irq;
}

static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
{
	set_bit(irq, vcpu->irq_pending);
	set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
}

static inline void clgi(void)
{
	asm volatile (SVM_CLGI);
}

static inline void stgi(void)
{
	asm volatile (SVM_STGI);
}

static inline void invlpga(unsigned long addr, u32 asid)
{
	asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
}

static inline unsigned long kvm_read_cr2(void)
{
	unsigned long cr2;

	asm volatile ("mov %%cr2, %0" : "=r" (cr2));
	return cr2;
}

static inline void kvm_write_cr2(unsigned long val)
{
	asm volatile ("mov %0, %%cr2" :: "r" (val));
}

static inline unsigned long read_dr6(void)
{
	unsigned long dr6;

	asm volatile ("mov %%dr6, %0" : "=r" (dr6));
	return dr6;
}

static inline void write_dr6(unsigned long val)
{
	asm volatile ("mov %0, %%dr6" :: "r" (val));
}

static inline unsigned long read_dr7(void)
{
	unsigned long dr7;

	asm volatile ("mov %%dr7, %0" : "=r" (dr7));
	return dr7;
}

static inline void write_dr7(unsigned long val)
{
	asm volatile ("mov %0, %%dr7" :: "r" (val));
}

static inline void force_new_asid(struct kvm_vcpu *vcpu)
{
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	to_svm(vcpu)->asid_generation--;
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}

static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
{
	force_new_asid(vcpu);
}

static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
{
	if (!(efer & KVM_EFER_LMA))
		efer &= ~KVM_EFER_LME;

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	to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
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	vcpu->shadow_efer = efer;
}

static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	svm->vmcb->control.event_inj =		SVM_EVTINJ_VALID |
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						SVM_EVTINJ_VALID_ERR |
						SVM_EVTINJ_TYPE_EXEPT |
						GP_VECTOR;
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	svm->vmcb->control.event_inj_err = error_code;
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}

static void inject_ud(struct kvm_vcpu *vcpu)
{
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	to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
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						SVM_EVTINJ_TYPE_EXEPT |
						UD_VECTOR;
}

static int is_page_fault(uint32_t info)
{
	info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
	return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
}

static int is_external_interrupt(u32 info)
{
	info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
	return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
}

static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	if (!svm->next_rip) {
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		printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
		return;
	}
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	if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
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		printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
		       __FUNCTION__,
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		       svm->vmcb->save.rip,
		       svm->next_rip);
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	}

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	vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
	svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
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	vcpu->interrupt_window_open = 1;
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}

static int has_svm(void)
{
	uint32_t eax, ebx, ecx, edx;

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	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
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		printk(KERN_INFO "has_svm: not amd\n");
		return 0;
	}

	cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
	if (eax < SVM_CPUID_FUNC) {
		printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
		return 0;
	}

	cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
	if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
		printk(KERN_DEBUG "has_svm: svm not available\n");
		return 0;
	}
	return 1;
}

static void svm_hardware_disable(void *garbage)
{
	struct svm_cpu_data *svm_data
		= per_cpu(svm_data, raw_smp_processor_id());

	if (svm_data) {
		uint64_t efer;

		wrmsrl(MSR_VM_HSAVE_PA, 0);
		rdmsrl(MSR_EFER, efer);
		wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
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		per_cpu(svm_data, raw_smp_processor_id()) = NULL;
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		__free_page(svm_data->save_area);
		kfree(svm_data);
	}
}

static void svm_hardware_enable(void *garbage)
{

	struct svm_cpu_data *svm_data;
	uint64_t efer;
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#ifdef CONFIG_X86_64
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	struct desc_ptr gdt_descr;
#else
	struct Xgt_desc_struct gdt_descr;
#endif
	struct desc_struct *gdt;
	int me = raw_smp_processor_id();

	if (!has_svm()) {
		printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
		return;
	}
	svm_data = per_cpu(svm_data, me);

	if (!svm_data) {
		printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
		       me);
		return;
	}

	svm_data->asid_generation = 1;
	svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
	svm_data->next_asid = svm_data->max_asid + 1;
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	svm_features = cpuid_edx(SVM_CPUID_FUNC);
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	asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
	gdt = (struct desc_struct *)gdt_descr.address;
	svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);

	rdmsrl(MSR_EFER, efer);
	wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);

	wrmsrl(MSR_VM_HSAVE_PA,
	       page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
}

static int svm_cpu_init(int cpu)
{
	struct svm_cpu_data *svm_data;
	int r;

	svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
	if (!svm_data)
		return -ENOMEM;
	svm_data->cpu = cpu;
	svm_data->save_area = alloc_page(GFP_KERNEL);
	r = -ENOMEM;
	if (!svm_data->save_area)
		goto err_1;

	per_cpu(svm_data, cpu) = svm_data;

	return 0;

err_1:
	kfree(svm_data);
	return r;

}

static int set_msr_interception(u32 *msrpm, unsigned msr,
				int read, int write)
{
	int i;

	for (i = 0; i < NUM_MSR_MAPS; i++) {
		if (msr >= msrpm_ranges[i] &&
		    msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
			u32 msr_offset = (i * MSRS_IN_RANGE + msr -
					  msrpm_ranges[i]) * 2;

			u32 *base = msrpm + (msr_offset / 32);
			u32 msr_shift = msr_offset % 32;
			u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
			*base = (*base & ~(0x3 << msr_shift)) |
				(mask << msr_shift);
			return 1;
		}
	}
	printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
	return 0;
}

static __init int svm_hardware_setup(void)
{
	int cpu;
	struct page *iopm_pages;
	struct page *msrpm_pages;
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	void *iopm_va, *msrpm_va;
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	int r;

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	kvm_emulator_want_group7_invlpg();
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	iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);

	if (!iopm_pages)
		return -ENOMEM;
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	iopm_va = page_address(iopm_pages);
	memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
	clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
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	iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;


	msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);

	r = -ENOMEM;
	if (!msrpm_pages)
		goto err_1;

	msrpm_va = page_address(msrpm_pages);
	memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
	msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;

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#ifdef CONFIG_X86_64
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	set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
	set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
	set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
	set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
	set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
	set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
#endif
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	set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
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	set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
	set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
	set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);

	for_each_online_cpu(cpu) {
		r = svm_cpu_init(cpu);
		if (r)
			goto err_2;
	}
	return 0;

err_2:
	__free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
	msrpm_base = 0;
err_1:
	__free_pages(iopm_pages, IOPM_ALLOC_ORDER);
	iopm_base = 0;
	return r;
}

static __exit void svm_hardware_unsetup(void)
{
	__free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
	__free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
	iopm_base = msrpm_base = 0;
}

static void init_seg(struct vmcb_seg *seg)
{
	seg->selector = 0;
	seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
		SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
	seg->limit = 0xffff;
	seg->base = 0;
}

static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
{
	seg->selector = 0;
	seg->attrib = SVM_SELECTOR_P_MASK | type;
	seg->limit = 0xffff;
	seg->base = 0;
}

static void init_vmcb(struct vmcb *vmcb)
{
	struct vmcb_control_area *control = &vmcb->control;
	struct vmcb_save_area *save = &vmcb->save;

	control->intercept_cr_read = 	INTERCEPT_CR0_MASK |
					INTERCEPT_CR3_MASK |
					INTERCEPT_CR4_MASK;

	control->intercept_cr_write = 	INTERCEPT_CR0_MASK |
					INTERCEPT_CR3_MASK |
					INTERCEPT_CR4_MASK;

	control->intercept_dr_read = 	INTERCEPT_DR0_MASK |
					INTERCEPT_DR1_MASK |
					INTERCEPT_DR2_MASK |
					INTERCEPT_DR3_MASK;

	control->intercept_dr_write = 	INTERCEPT_DR0_MASK |
					INTERCEPT_DR1_MASK |
					INTERCEPT_DR2_MASK |
					INTERCEPT_DR3_MASK |
					INTERCEPT_DR5_MASK |
					INTERCEPT_DR7_MASK;

	control->intercept_exceptions = 1 << PF_VECTOR;


	control->intercept = 	(1ULL << INTERCEPT_INTR) |
				(1ULL << INTERCEPT_NMI) |
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				(1ULL << INTERCEPT_SMI) |
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		/*
		 * selective cr0 intercept bug?
		 *    	0:   0f 22 d8                mov    %eax,%cr3
		 *	3:   0f 20 c0                mov    %cr0,%eax
		 *	6:   0d 00 00 00 80          or     $0x80000000,%eax
		 *	b:   0f 22 c0                mov    %eax,%cr0
		 * set cr3 ->interception
		 * get cr0 ->interception
		 * set cr0 -> no interception
		 */
		/*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
				(1ULL << INTERCEPT_CPUID) |
				(1ULL << INTERCEPT_HLT) |
				(1ULL << INTERCEPT_INVLPGA) |
				(1ULL << INTERCEPT_IOIO_PROT) |
				(1ULL << INTERCEPT_MSR_PROT) |
				(1ULL << INTERCEPT_TASK_SWITCH) |
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				(1ULL << INTERCEPT_SHUTDOWN) |
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				(1ULL << INTERCEPT_VMRUN) |
				(1ULL << INTERCEPT_VMMCALL) |
				(1ULL << INTERCEPT_VMLOAD) |
				(1ULL << INTERCEPT_VMSAVE) |
				(1ULL << INTERCEPT_STGI) |
				(1ULL << INTERCEPT_CLGI) |
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				(1ULL << INTERCEPT_SKINIT) |
				(1ULL << INTERCEPT_MONITOR) |
				(1ULL << INTERCEPT_MWAIT);
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	control->iopm_base_pa = iopm_base;
	control->msrpm_base_pa = msrpm_base;
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	control->tsc_offset = 0;
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	control->int_ctl = V_INTR_MASKING_MASK;

	init_seg(&save->es);
	init_seg(&save->ss);
	init_seg(&save->ds);
	init_seg(&save->fs);
	init_seg(&save->gs);

	save->cs.selector = 0xf000;
	/* Executable/Readable Code Segment */
	save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
		SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
	save->cs.limit = 0xffff;
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	/*
	 * cs.base should really be 0xffff0000, but vmx can't handle that, so
	 * be consistent with it.
	 *
	 * Replace when we have real mode working for vmx.
	 */
	save->cs.base = 0xf0000;
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	save->gdtr.limit = 0xffff;
	save->idtr.limit = 0xffff;

	init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
	init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);

	save->efer = MSR_EFER_SVME_MASK;

        save->dr6 = 0xffff0ff0;
	save->dr7 = 0x400;
	save->rflags = 2;
	save->rip = 0x0000fff0;

	/*
	 * cr0 val on cpu init should be 0x60000010, we enable cpu
	 * cache by default. the orderly way is to enable cache in bios.
	 */
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	save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
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	save->cr4 = X86_CR4_PAE;
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	/* rdx = ?? */
}

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static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
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{
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	struct vcpu_svm *svm;
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	struct page *page;
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	int err;
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	svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
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	if (!svm) {
		err = -ENOMEM;
		goto out;
	}

	err = kvm_vcpu_init(&svm->vcpu, kvm, id);
	if (err)
		goto free_svm;

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	page = alloc_page(GFP_KERNEL);
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	if (!page) {
		err = -ENOMEM;
		goto uninit;
	}
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	svm->vmcb = page_address(page);
	clear_page(svm->vmcb);
	svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
	svm->asid_generation = 0;
	memset(svm->db_regs, 0, sizeof(svm->db_regs));
	init_vmcb(svm->vmcb);

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	fx_init(&svm->vcpu);
	svm->vcpu.fpu_active = 1;
	svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
	if (svm->vcpu.vcpu_id == 0)
		svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
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	return &svm->vcpu;
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uninit:
	kvm_vcpu_uninit(&svm->vcpu);
free_svm:
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	kfree(svm);
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out:
	return ERR_PTR(err);
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}

static void svm_free_vcpu(struct kvm_vcpu *vcpu)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

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	__free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
	kvm_vcpu_uninit(vcpu);
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	kfree(svm);
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}

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static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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{
630
	struct vcpu_svm *svm = to_svm(vcpu);
631
	int i;
632 633 634 635 636 637 638 639 640 641

	if (unlikely(cpu != vcpu->cpu)) {
		u64 tsc_this, delta;

		/*
		 * Make sure that the guest sees a monotonically
		 * increasing TSC.
		 */
		rdtscll(tsc_this);
		delta = vcpu->host_tsc - tsc_this;
642
		svm->vmcb->control.tsc_offset += delta;
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		vcpu->cpu = cpu;
	}
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	for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
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		rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
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}

static void svm_vcpu_put(struct kvm_vcpu *vcpu)
{
652
	struct vcpu_svm *svm = to_svm(vcpu);
653 654 655
	int i;

	for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
656
		wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
657

658
	rdtscll(vcpu->host_tsc);
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}

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static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
{
}

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static void svm_cache_regs(struct kvm_vcpu *vcpu)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
	vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
	vcpu->rip = svm->vmcb->save.rip;
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}

static void svm_decache_regs(struct kvm_vcpu *vcpu)
{
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	struct vcpu_svm *svm = to_svm(vcpu);
	svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
	svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
	svm->vmcb->save.rip = vcpu->rip;
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}

static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
{
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	return to_svm(vcpu)->vmcb->save.rflags;
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}

static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
{
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	to_svm(vcpu)->vmcb->save.rflags = rflags;
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}

static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
{
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	struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
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	switch (seg) {
	case VCPU_SREG_CS: return &save->cs;
	case VCPU_SREG_DS: return &save->ds;
	case VCPU_SREG_ES: return &save->es;
	case VCPU_SREG_FS: return &save->fs;
	case VCPU_SREG_GS: return &save->gs;
	case VCPU_SREG_SS: return &save->ss;
	case VCPU_SREG_TR: return &save->tr;
	case VCPU_SREG_LDTR: return &save->ldtr;
	}
	BUG();
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	return NULL;
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}

static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
{
	struct vmcb_seg *s = svm_seg(vcpu, seg);

	return s->base;
}

static void svm_get_segment(struct kvm_vcpu *vcpu,
			    struct kvm_segment *var, int seg)
{
	struct vmcb_seg *s = svm_seg(vcpu, seg);

	var->base = s->base;
	var->limit = s->limit;
	var->selector = s->selector;
	var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
	var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
	var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
	var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
	var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
	var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
	var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
	var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
	var->unusable = !var->present;
}

static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
{
	struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);

	*db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
	*l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
}

static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	dt->limit = svm->vmcb->save.idtr.limit;
	dt->base = svm->vmcb->save.idtr.base;
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}

static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	svm->vmcb->save.idtr.limit = dt->limit;
	svm->vmcb->save.idtr.base = dt->base ;
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}

static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	dt->limit = svm->vmcb->save.gdtr.limit;
	dt->base = svm->vmcb->save.gdtr.base;
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}

static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
{
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	struct vcpu_svm *svm = to_svm(vcpu);

	svm->vmcb->save.gdtr.limit = dt->limit;
	svm->vmcb->save.gdtr.base = dt->base ;
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}

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static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
777 778 779
{
}

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static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
{
782 783
	struct vcpu_svm *svm = to_svm(vcpu);

784
#ifdef CONFIG_X86_64
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	if (vcpu->shadow_efer & KVM_EFER_LME) {
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		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
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			vcpu->shadow_efer |= KVM_EFER_LMA;
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			svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
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		}

791
		if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
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			vcpu->shadow_efer &= ~KVM_EFER_LMA;
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			svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
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		}
	}
#endif
797
	if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
798
		svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
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		vcpu->fpu_active = 1;
	}

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	vcpu->cr0 = cr0;
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	cr0 |= X86_CR0_PG | X86_CR0_WP;
	cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
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	svm->vmcb->save.cr0 = cr0;
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}

static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
{
       vcpu->cr4 = cr4;
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       to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
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}

static void svm_set_segment(struct kvm_vcpu *vcpu,
			    struct kvm_segment *var, int seg)
{
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	struct vcpu_svm *svm = to_svm(vcpu);
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	struct vmcb_seg *s = svm_seg(vcpu, seg);

	s->base = var->base;
	s->limit = var->limit;
	s->selector = var->selector;
	if (var->unusable)
		s->attrib = 0;
	else {
		s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
		s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
		s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
		s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
		s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
		s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
		s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
		s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
	}
	if (seg == VCPU_SREG_CS)
836 837
		svm->vmcb->save.cpl
			= (svm->vmcb->save.cs.attrib
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			   >> SVM_SELECTOR_DPL_SHIFT) & 3;

}

/* FIXME:

844 845
	svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
	svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
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*/

static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
{
	return -EOPNOTSUPP;
}

static void load_host_msrs(struct kvm_vcpu *vcpu)
{
856
#ifdef CONFIG_X86_64
857
	wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
858
#endif
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}

static void save_host_msrs(struct kvm_vcpu *vcpu)
{
863
#ifdef CONFIG_X86_64
864
	rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
865
#endif
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}

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static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
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{
	if (svm_data->next_asid > svm_data->max_asid) {
		++svm_data->asid_generation;
		svm_data->next_asid = 1;
873
		svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
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	}

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	svm->vcpu.cpu = svm_data->cpu;
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	svm->asid_generation = svm_data->asid_generation;
	svm->vmcb->control.asid = svm_data->next_asid++;
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}

static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
{
883
	invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed?
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}

static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
{
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	return to_svm(vcpu)->db_regs[dr];
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}

static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
		       int *exception)
{
894 895
	struct vcpu_svm *svm = to_svm(vcpu);

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	*exception = 0;

898 899 900
	if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
		svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
		svm->vmcb->save.dr6 |= DR6_BD_MASK;
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		*exception = DB_VECTOR;
		return;
	}

	switch (dr) {
	case 0 ... 3:
907
		svm->db_regs[dr] = value;
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		return;
	case 4 ... 5:
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		if (vcpu->cr4 & X86_CR4_DE) {
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			*exception = UD_VECTOR;
			return;
		}
	case 7: {
		if (value & ~((1ULL << 32) - 1)) {
			*exception = GP_VECTOR;
			return;
		}
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		svm->vmcb->save.dr7 = value;
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		return;
	}
	default:
		printk(KERN_DEBUG "%s: unexpected dr %u\n",
		       __FUNCTION__, dr);
		*exception = UD_VECTOR;
		return;
	}
}

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static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
932
	u32 exit_int_info = svm->vmcb->control.exit_int_info;
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	struct kvm *kvm = svm->vcpu.kvm;
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	u64 fault_address;
	u32 error_code;
	enum emulation_result er;
937
	int r;
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	if (is_external_interrupt(exit_int_info))
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		push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
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	mutex_lock(&kvm->lock);
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	fault_address  = svm->vmcb->control.exit_info_2;
	error_code = svm->vmcb->control.exit_info_1;
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	r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
947
	if (r < 0) {
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		mutex_unlock(&kvm->lock);
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		return r;
	}
	if (!r) {
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		mutex_unlock(&kvm->lock);
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		return 1;
	}
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	er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
				 error_code);
	mutex_unlock(&kvm->lock);
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	switch (er) {
	case EMULATE_DONE:
		return 1;
	case EMULATE_DO_MMIO:
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		++svm->vcpu.stat.mmio_exits;
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		return 0;
	case EMULATE_FAIL:
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		vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__);
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		break;
	default:
		BUG();
	}

	kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
	return 0;
}

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static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
978
	svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
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	if (!(svm->vcpu.cr0 & X86_CR0_TS))
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		svm->vmcb->save.cr0 &= ~X86_CR0_TS;
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	svm->vcpu.fpu_active = 1;
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	return 1;
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}

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static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
987 988 989 990 991
{
	/*
	 * VMCB is undefined after a SHUTDOWN intercept
	 * so reinitialize it.
	 */
992 993
	clear_page(svm->vmcb);
	init_vmcb(svm->vmcb);
994 995 996 997 998

	kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
	return 0;
}

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static int io_get_override(struct vcpu_svm *svm,
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			  struct vmcb_seg **seg,
			  int *addr_override)
{
	u8 inst[MAX_INST_SIZE];
	unsigned ins_length;
	gva_t rip;
	int i;

1008 1009 1010
	rip =  svm->vmcb->save.rip;
	ins_length = svm->next_rip - rip;
	rip += svm->vmcb->save.cs.base;
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	if (ins_length > MAX_INST_SIZE)
		printk(KERN_DEBUG
		       "%s: inst length err, cs base 0x%llx rip 0x%llx "
		       "next rip 0x%llx ins_length %u\n",
		       __FUNCTION__,
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		       svm->vmcb->save.cs.base,
		       svm->vmcb->save.rip,
		       svm->vmcb->control.exit_info_2,
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		       ins_length);

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	if (emulator_read_std(rip, inst, ins_length, &svm->vcpu)
	    != X86EMUL_CONTINUE)
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		/* #PF */
		return 0;

	*addr_override = 0;
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	*seg = NULL;
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	for (i = 0; i < ins_length; i++)
		switch (inst[i]) {
		case 0xf0:
		case 0xf2:
		case 0xf3:
		case 0x66:
			continue;
		case 0x67:
			*addr_override = 1;
			continue;
		case 0x2e:
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			*seg = &svm->vmcb->save.cs;
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			continue;
		case 0x36:
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			*seg = &svm->vmcb->save.ss;
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			continue;
		case 0x3e:
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			*seg = &svm->vmcb->save.ds;
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			continue;
		case 0x26:
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			*seg = &svm->vmcb->save.es;
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			continue;
		case 0x64:
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			*seg = &svm->vmcb->save.fs;
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			continue;
		case 0x65:
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			*seg = &svm->vmcb->save.gs;
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			continue;
		default:
			return 1;
		}
	printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
	return 0;
}

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static unsigned long io_address(struct vcpu_svm *svm, int ins, gva_t *address)
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{
	unsigned long addr_mask;
	unsigned long *reg;
	struct vmcb_seg *seg;
	int addr_override;
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	struct vmcb_save_area *save_area = &svm->vmcb->save;
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	u16 cs_attrib = save_area->cs.attrib;
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	unsigned addr_size = get_addr_size(svm);
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	if (!io_get_override(svm, &seg, &addr_override))
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		return 0;

	if (addr_override)
		addr_size = (addr_size == 2) ? 4: (addr_size >> 1);

	if (ins) {
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		reg = &svm->vcpu.regs[VCPU_REGS_RDI];
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		seg = &svm->vmcb->save.es;
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	} else {
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		reg = &svm->vcpu.regs[VCPU_REGS_RSI];
1085
		seg = (seg) ? seg : &svm->vmcb->save.ds;
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1086 1087 1088 1089 1090
	}

	addr_mask = ~0ULL >> (64 - (addr_size * 8));

	if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1091
	    !(svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
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		*address = (*reg & addr_mask);
		return addr_mask;
	}

	if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
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		svm_inject_gp(&svm->vcpu, 0);
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1098 1099 1100 1101 1102 1103 1104
		return 0;
	}

	*address = (*reg & addr_mask) + seg->base;
	return addr_mask;
}

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static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
1107
	u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
1108 1109 1110 1111
	int size, down, in, string, rep;
	unsigned port;
	unsigned long count;
	gva_t address = 0;
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1112

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	++svm->vcpu.stat.io_exits;
A
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1114

1115
	svm->next_rip = svm->vmcb->control.exit_info_2;
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1117 1118 1119 1120 1121 1122
	in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
	port = io_info >> 16;
	size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
	string = (io_info & SVM_IOIO_STR_MASK) != 0;
	rep = (io_info & SVM_IOIO_REP_MASK) != 0;
	count = 1;
1123
	down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
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1124

1125
	if (string) {
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1126 1127
		unsigned addr_mask;

1128
		addr_mask = io_address(svm, in, &address);
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1129
		if (!addr_mask) {
A
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1130 1131
			printk(KERN_DEBUG "%s: get io address failed\n",
			       __FUNCTION__);
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1132 1133 1134
			return 1;
		}

1135
		if (rep)
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			count = svm->vcpu.regs[VCPU_REGS_RCX] & addr_mask;
1137
	}
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	return kvm_setup_pio(&svm->vcpu, kvm_run, in, size, count, string,
			     down, address, rep, port);
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}

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static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
	return 1;
}

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static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
A
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1148
{
1149
	svm->next_rip = svm->vmcb->save.rip + 1;
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	skip_emulated_instruction(&svm->vcpu);
	return kvm_emulate_halt(&svm->vcpu);
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}

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static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1155
{
1156
	svm->next_rip = svm->vmcb->save.rip + 3;
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	skip_emulated_instruction(&svm->vcpu);
	return kvm_hypercall(&svm->vcpu, kvm_run);
1159 1160
}

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static int invalid_op_interception(struct vcpu_svm *svm,
				   struct kvm_run *kvm_run)
A
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1163
{
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	inject_ud(&svm->vcpu);
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1165 1166 1167
	return 1;
}

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static int task_switch_interception(struct vcpu_svm *svm,
				    struct kvm_run *kvm_run)
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{
	printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
	kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
	return 0;
}

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static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
1178
	svm->next_rip = svm->vmcb->save.rip + 2;
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	kvm_emulate_cpuid(&svm->vcpu);
1180
	return 1;
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}

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static int emulate_on_interception(struct vcpu_svm *svm,
				   struct kvm_run *kvm_run)
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{
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	if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE)
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		printk(KERN_ERR "%s: failed\n", __FUNCTION__);
	return 1;
}

static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
{
1193 1194
	struct vcpu_svm *svm = to_svm(vcpu);

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	switch (ecx) {
	case MSR_IA32_TIME_STAMP_COUNTER: {
		u64 tsc;

		rdtscll(tsc);
1200
		*data = svm->vmcb->control.tsc_offset + tsc;
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		break;
	}
1203
	case MSR_K6_STAR:
1204
		*data = svm->vmcb->save.star;
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		break;
1206
#ifdef CONFIG_X86_64
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	case MSR_LSTAR:
1208
		*data = svm->vmcb->save.lstar;
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		break;
	case MSR_CSTAR:
1211
		*data = svm->vmcb->save.cstar;
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		break;
	case MSR_KERNEL_GS_BASE:
1214
		*data = svm->vmcb->save.kernel_gs_base;
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		break;
	case MSR_SYSCALL_MASK:
1217
		*data = svm->vmcb->save.sfmask;
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		break;
#endif
	case MSR_IA32_SYSENTER_CS:
1221
		*data = svm->vmcb->save.sysenter_cs;
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		break;
	case MSR_IA32_SYSENTER_EIP:
1224
		*data = svm->vmcb->save.sysenter_eip;
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		break;
	case MSR_IA32_SYSENTER_ESP:
1227
		*data = svm->vmcb->save.sysenter_esp;
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		break;
	default:
1230
		return kvm_get_msr_common(vcpu, ecx, data);
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	}
	return 0;
}

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static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
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	u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
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	u64 data;

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	if (svm_get_msr(&svm->vcpu, ecx, &data))
		svm_inject_gp(&svm->vcpu, 0);
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	else {
1243
		svm->vmcb->save.rax = data & 0xffffffff;
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		svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1245
		svm->next_rip = svm->vmcb->save.rip + 2;
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		skip_emulated_instruction(&svm->vcpu);
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	}
	return 1;
}

static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
{
1253 1254
	struct vcpu_svm *svm = to_svm(vcpu);

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	switch (ecx) {
	case MSR_IA32_TIME_STAMP_COUNTER: {
		u64 tsc;

		rdtscll(tsc);
1260
		svm->vmcb->control.tsc_offset = data - tsc;
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		break;
	}
1263
	case MSR_K6_STAR:
1264
		svm->vmcb->save.star = data;
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		break;
1266
#ifdef CONFIG_X86_64
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	case MSR_LSTAR:
1268
		svm->vmcb->save.lstar = data;
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		break;
	case MSR_CSTAR:
1271
		svm->vmcb->save.cstar = data;
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		break;
	case MSR_KERNEL_GS_BASE:
1274
		svm->vmcb->save.kernel_gs_base = data;
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		break;
	case MSR_SYSCALL_MASK:
1277
		svm->vmcb->save.sfmask = data;
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		break;
#endif
	case MSR_IA32_SYSENTER_CS:
1281
		svm->vmcb->save.sysenter_cs = data;
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		break;
	case MSR_IA32_SYSENTER_EIP:
1284
		svm->vmcb->save.sysenter_eip = data;
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		break;
	case MSR_IA32_SYSENTER_ESP:
1287
		svm->vmcb->save.sysenter_esp = data;
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		break;
	default:
1290
		return kvm_set_msr_common(vcpu, ecx, data);
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	}
	return 0;
}

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static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
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	u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1298
	u64 data = (svm->vmcb->save.rax & -1u)
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		| ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1300
	svm->next_rip = svm->vmcb->save.rip + 2;
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	if (svm_set_msr(&svm->vcpu, ecx, data))
		svm_inject_gp(&svm->vcpu, 0);
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1303
	else
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		skip_emulated_instruction(&svm->vcpu);
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	return 1;
}

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static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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{
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	if (svm->vmcb->control.exit_info_1)
		return wrmsr_interception(svm, kvm_run);
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	else
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		return rdmsr_interception(svm, kvm_run);
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}

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static int interrupt_window_interception(struct vcpu_svm *svm,
1317 1318 1319 1320 1321 1322 1323
				   struct kvm_run *kvm_run)
{
	/*
	 * If the user space waits to inject interrupts, exit as soon as
	 * possible
	 */
	if (kvm_run->request_interrupt_window &&
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	    !svm->vcpu.irq_summary) {
		++svm->vcpu.stat.irq_window_exits;
1326 1327 1328 1329 1330 1331 1332
		kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
		return 0;
	}

	return 1;
}

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static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
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				      struct kvm_run *kvm_run) = {
	[SVM_EXIT_READ_CR0]           		= emulate_on_interception,
	[SVM_EXIT_READ_CR3]           		= emulate_on_interception,
	[SVM_EXIT_READ_CR4]           		= emulate_on_interception,
	/* for now: */
	[SVM_EXIT_WRITE_CR0]          		= emulate_on_interception,
	[SVM_EXIT_WRITE_CR3]          		= emulate_on_interception,
	[SVM_EXIT_WRITE_CR4]          		= emulate_on_interception,
	[SVM_EXIT_READ_DR0] 			= emulate_on_interception,
	[SVM_EXIT_READ_DR1]			= emulate_on_interception,
	[SVM_EXIT_READ_DR2]			= emulate_on_interception,
	[SVM_EXIT_READ_DR3]			= emulate_on_interception,
	[SVM_EXIT_WRITE_DR0]			= emulate_on_interception,
	[SVM_EXIT_WRITE_DR1]			= emulate_on_interception,
	[SVM_EXIT_WRITE_DR2]			= emulate_on_interception,
	[SVM_EXIT_WRITE_DR3]			= emulate_on_interception,
	[SVM_EXIT_WRITE_DR5]			= emulate_on_interception,
	[SVM_EXIT_WRITE_DR7]			= emulate_on_interception,
	[SVM_EXIT_EXCP_BASE + PF_VECTOR] 	= pf_interception,
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	[SVM_EXIT_EXCP_BASE + NM_VECTOR] 	= nm_interception,
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	[SVM_EXIT_INTR] 			= nop_on_interception,
	[SVM_EXIT_NMI]				= nop_on_interception,
	[SVM_EXIT_SMI]				= nop_on_interception,
	[SVM_EXIT_INIT]				= nop_on_interception,
1358
	[SVM_EXIT_VINTR]			= interrupt_window_interception,
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	/* [SVM_EXIT_CR0_SEL_WRITE]		= emulate_on_interception, */
	[SVM_EXIT_CPUID]			= cpuid_interception,
	[SVM_EXIT_HLT]				= halt_interception,
	[SVM_EXIT_INVLPG]			= emulate_on_interception,
	[SVM_EXIT_INVLPGA]			= invalid_op_interception,
	[SVM_EXIT_IOIO] 		  	= io_interception,
	[SVM_EXIT_MSR]				= msr_interception,
	[SVM_EXIT_TASK_SWITCH]			= task_switch_interception,
1367
	[SVM_EXIT_SHUTDOWN]			= shutdown_interception,
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	[SVM_EXIT_VMRUN]			= invalid_op_interception,
1369
	[SVM_EXIT_VMMCALL]			= vmmcall_interception,
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	[SVM_EXIT_VMLOAD]			= invalid_op_interception,
	[SVM_EXIT_VMSAVE]			= invalid_op_interception,
	[SVM_EXIT_STGI]				= invalid_op_interception,
	[SVM_EXIT_CLGI]				= invalid_op_interception,
	[SVM_EXIT_SKINIT]			= invalid_op_interception,
1375 1376
	[SVM_EXIT_MONITOR]			= invalid_op_interception,
	[SVM_EXIT_MWAIT]			= invalid_op_interception,
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};


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static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run)
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1381
{
1382
	u32 exit_code = svm->vmcb->control.exit_code;
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1383

1384
	if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
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	    exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
		printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
		       "exit_code 0x%x\n",
1388
		       __FUNCTION__, svm->vmcb->control.exit_int_info,
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1389 1390
		       exit_code);

1391
	if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
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1392 1393
	    || svm_exit_handlers[exit_code] == 0) {
		kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1394
		kvm_run->hw.hardware_exit_reason = exit_code;
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1395 1396 1397
		return 0;
	}

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	return svm_exit_handlers[exit_code](svm, kvm_run);
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1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
}

static void reload_tss(struct kvm_vcpu *vcpu)
{
	int cpu = raw_smp_processor_id();

	struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
	svm_data->tss_desc->type = 9; //available 32/64-bit TSS
	load_TR_desc();
}

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static void pre_svm_run(struct vcpu_svm *svm)
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1411 1412 1413 1414 1415
{
	int cpu = raw_smp_processor_id();

	struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);

1416
	svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
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1417
	if (svm->vcpu.cpu != cpu ||
1418
	    svm->asid_generation != svm_data->asid_generation)
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		new_asid(svm, svm_data);
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1420 1421 1422
}


1423
static inline void inject_irq(struct vcpu_svm *svm)
A
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1424 1425 1426
{
	struct vmcb_control_area *control;

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	control = &svm->vmcb->control;
	control->int_vector = pop_irq(&svm->vcpu);
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	control->int_ctl &= ~V_INTR_PRIO_MASK;
	control->int_ctl |= V_IRQ_MASK |
		((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
}

1434
static void reput_irq(struct vcpu_svm *svm)
A
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1435
{
R
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1436
	struct vmcb_control_area *control = &svm->vmcb->control;
A
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1437 1438 1439

	if (control->int_ctl & V_IRQ_MASK) {
		control->int_ctl &= ~V_IRQ_MASK;
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1440
		push_irq(&svm->vcpu, control->int_vector);
A
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1441
	}
1442

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	svm->vcpu.interrupt_window_open =
1444 1445 1446
		!(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
}

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1447
static void do_interrupt_requests(struct vcpu_svm *svm,
1448 1449
				       struct kvm_run *kvm_run)
{
1450
	struct vmcb_control_area *control = &svm->vmcb->control;
1451

R
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1452
	svm->vcpu.interrupt_window_open =
1453
		(!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1454
		 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1455

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1456
	if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1457 1458 1459
		/*
		 * If interrupts enabled, and not blocked by sti or mov ss. Good.
		 */
1460
		inject_irq(svm);
1461 1462 1463 1464

	/*
	 * Interrupts blocked.  Wait for unblock.
	 */
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1465 1466
	if (!svm->vcpu.interrupt_window_open &&
	    (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1467 1468 1469 1470 1471
		control->intercept |= 1ULL << INTERCEPT_VINTR;
	} else
		control->intercept &= ~(1ULL << INTERCEPT_VINTR);
}

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static void post_kvm_run_save(struct vcpu_svm *svm,
1473 1474
			      struct kvm_run *kvm_run)
{
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1475 1476 1477
	kvm_run->ready_for_interrupt_injection
		= (svm->vcpu.interrupt_window_open &&
		   svm->vcpu.irq_summary == 0);
1478
	kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
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	kvm_run->cr8 = svm->vcpu.cr8;
	kvm_run->apic_base = svm->vcpu.apic_base;
1481 1482 1483 1484 1485 1486 1487 1488
}

/*
 * Check if userspace requested an interrupt window, and that the
 * interrupt window is open.
 *
 * No need to exit to userspace if we already have an interrupt queued.
 */
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static int dm_request_for_irq_injection(struct vcpu_svm *svm,
1490 1491
					  struct kvm_run *kvm_run)
{
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	return (!svm->vcpu.irq_summary &&
1493
		kvm_run->request_interrupt_window &&
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		svm->vcpu.interrupt_window_open &&
		(svm->vmcb->save.rflags & X86_EFLAGS_IF));
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}

static void save_db_regs(unsigned long *db_regs)
{
1500 1501 1502 1503
	asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
	asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
	asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
	asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
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}

static void load_db_regs(unsigned long *db_regs)
{
1508 1509 1510 1511
	asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
	asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
	asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
	asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
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}

1514 1515 1516 1517 1518
static void svm_flush_tlb(struct kvm_vcpu *vcpu)
{
	force_new_asid(vcpu);
}

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static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
{
1521
	struct vcpu_svm *svm = to_svm(vcpu);
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	u16 fs_selector;
	u16 gs_selector;
	u16 ldt_selector;
1525
	int r;
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again:
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	r = kvm_mmu_reload(vcpu);
	if (unlikely(r))
		return r;

1532
	if (!vcpu->mmio_read_completed)
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		do_interrupt_requests(svm, kvm_run);
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	clgi();

1537 1538 1539 1540 1541
	vcpu->guest_mode = 1;
	if (vcpu->requests)
		if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
		    svm_flush_tlb(vcpu);

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	pre_svm_run(svm);
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	save_host_msrs(vcpu);
	fs_selector = read_fs();
	gs_selector = read_gs();
	ldt_selector = read_ldt();
1548 1549 1550 1551
	svm->host_cr2 = kvm_read_cr2();
	svm->host_dr6 = read_dr6();
	svm->host_dr7 = read_dr7();
	svm->vmcb->save.cr2 = vcpu->cr2;
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1553
	if (svm->vmcb->save.dr7 & 0xff) {
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		write_dr7(0);
1555 1556
		save_db_regs(svm->host_db_regs);
		load_db_regs(svm->db_regs);
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	}
1558

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	if (vcpu->fpu_active) {
1560 1561
		fx_save(&vcpu->host_fx_image);
		fx_restore(&vcpu->guest_fx_image);
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	}
1563

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	asm volatile (
1565
#ifdef CONFIG_X86_64
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		"push %%rbx; push %%rcx; push %%rdx;"
		"push %%rsi; push %%rdi; push %%rbp;"
		"push %%r8;  push %%r9;  push %%r10; push %%r11;"
		"push %%r12; push %%r13; push %%r14; push %%r15;"
#else
		"push %%ebx; push %%ecx; push %%edx;"
		"push %%esi; push %%edi; push %%ebp;"
#endif

1575
#ifdef CONFIG_X86_64
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		"mov %c[rbx](%[svm]), %%rbx \n\t"
		"mov %c[rcx](%[svm]), %%rcx \n\t"
		"mov %c[rdx](%[svm]), %%rdx \n\t"
		"mov %c[rsi](%[svm]), %%rsi \n\t"
		"mov %c[rdi](%[svm]), %%rdi \n\t"
		"mov %c[rbp](%[svm]), %%rbp \n\t"
		"mov %c[r8](%[svm]),  %%r8  \n\t"
		"mov %c[r9](%[svm]),  %%r9  \n\t"
		"mov %c[r10](%[svm]), %%r10 \n\t"
		"mov %c[r11](%[svm]), %%r11 \n\t"
		"mov %c[r12](%[svm]), %%r12 \n\t"
		"mov %c[r13](%[svm]), %%r13 \n\t"
		"mov %c[r14](%[svm]), %%r14 \n\t"
		"mov %c[r15](%[svm]), %%r15 \n\t"
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#else
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		"mov %c[rbx](%[svm]), %%ebx \n\t"
		"mov %c[rcx](%[svm]), %%ecx \n\t"
		"mov %c[rdx](%[svm]), %%edx \n\t"
		"mov %c[rsi](%[svm]), %%esi \n\t"
		"mov %c[rdi](%[svm]), %%edi \n\t"
		"mov %c[rbp](%[svm]), %%ebp \n\t"
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#endif

1599
#ifdef CONFIG_X86_64
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		/* Enter guest mode */
		"push %%rax \n\t"
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		"mov %c[vmcb](%[svm]), %%rax \n\t"
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		SVM_VMLOAD "\n\t"
		SVM_VMRUN "\n\t"
		SVM_VMSAVE "\n\t"
		"pop %%rax \n\t"
#else
		/* Enter guest mode */
		"push %%eax \n\t"
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		"mov %c[vmcb](%[svm]), %%eax \n\t"
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		SVM_VMLOAD "\n\t"
		SVM_VMRUN "\n\t"
		SVM_VMSAVE "\n\t"
		"pop %%eax \n\t"
#endif

		/* Save guest registers, load host registers */
1618
#ifdef CONFIG_X86_64
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		"mov %%rbx, %c[rbx](%[svm]) \n\t"
		"mov %%rcx, %c[rcx](%[svm]) \n\t"
		"mov %%rdx, %c[rdx](%[svm]) \n\t"
		"mov %%rsi, %c[rsi](%[svm]) \n\t"
		"mov %%rdi, %c[rdi](%[svm]) \n\t"
		"mov %%rbp, %c[rbp](%[svm]) \n\t"
		"mov %%r8,  %c[r8](%[svm]) \n\t"
		"mov %%r9,  %c[r9](%[svm]) \n\t"
		"mov %%r10, %c[r10](%[svm]) \n\t"
		"mov %%r11, %c[r11](%[svm]) \n\t"
		"mov %%r12, %c[r12](%[svm]) \n\t"
		"mov %%r13, %c[r13](%[svm]) \n\t"
		"mov %%r14, %c[r14](%[svm]) \n\t"
		"mov %%r15, %c[r15](%[svm]) \n\t"
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		"pop  %%r15; pop  %%r14; pop  %%r13; pop  %%r12;"
		"pop  %%r11; pop  %%r10; pop  %%r9;  pop  %%r8;"
		"pop  %%rbp; pop  %%rdi; pop  %%rsi;"
		"pop  %%rdx; pop  %%rcx; pop  %%rbx; \n\t"
#else
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		"mov %%ebx, %c[rbx](%[svm]) \n\t"
		"mov %%ecx, %c[rcx](%[svm]) \n\t"
		"mov %%edx, %c[rdx](%[svm]) \n\t"
		"mov %%esi, %c[rsi](%[svm]) \n\t"
		"mov %%edi, %c[rdi](%[svm]) \n\t"
		"mov %%ebp, %c[rbp](%[svm]) \n\t"
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1645 1646 1647 1648 1649

		"pop  %%ebp; pop  %%edi; pop  %%esi;"
		"pop  %%edx; pop  %%ecx; pop  %%ebx; \n\t"
#endif
		:
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		: [svm]"a"(svm),
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		  [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
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		  [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
		  [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
		  [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
		  [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
		  [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
		  [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1658
#ifdef CONFIG_X86_64
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		  ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
		  [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
		  [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
		  [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
		  [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
		  [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
		  [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
		  [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
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#endif
		: "cc", "memory" );

1670 1671
	vcpu->guest_mode = 0;

A
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1672
	if (vcpu->fpu_active) {
1673 1674
		fx_save(&vcpu->guest_fx_image);
		fx_restore(&vcpu->host_fx_image);
A
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	}
1676

1677 1678
	if ((svm->vmcb->save.dr7 & 0xff))
		load_db_regs(svm->host_db_regs);
A
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1680
	vcpu->cr2 = svm->vmcb->save.cr2;
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1682 1683 1684
	write_dr6(svm->host_dr6);
	write_dr7(svm->host_dr7);
	kvm_write_cr2(svm->host_cr2);
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	load_fs(fs_selector);
	load_gs(gs_selector);
	load_ldt(ldt_selector);
	load_host_msrs(vcpu);

	reload_tss(vcpu);

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	/*
	 * Profile KVM exit RIPs:
	 */
	if (unlikely(prof_on == KVM_PROFILING))
		profile_hit(KVM_PROFILING,
1698
			(void *)(unsigned long)svm->vmcb->save.rip);
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	stgi();

1702
	reput_irq(svm);
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1704
	svm->next_rip = 0;
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1706
	if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1707 1708
		kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
		kvm_run->fail_entry.hardware_entry_failure_reason
1709
			= svm->vmcb->control.exit_code;
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		post_kvm_run_save(svm, kvm_run);
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		return 0;
	}

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	r = handle_exit(svm, kvm_run);
1715
	if (r > 0) {
A
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		if (signal_pending(current)) {
A
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			++vcpu->stat.signal_exits;
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			post_kvm_run_save(svm, kvm_run);
1719
			kvm_run->exit_reason = KVM_EXIT_INTR;
1720 1721 1722
			return -EINTR;
		}

R
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		if (dm_request_for_irq_injection(svm, kvm_run)) {
A
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			++vcpu->stat.request_irq_exits;
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			post_kvm_run_save(svm, kvm_run);
1726
			kvm_run->exit_reason = KVM_EXIT_INTR;
A
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			return -EINTR;
		}
		kvm_resched(vcpu);
		goto again;
	}
R
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	post_kvm_run_save(svm, kvm_run);
1733
	return r;
A
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}

static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
{
1738 1739 1740
	struct vcpu_svm *svm = to_svm(vcpu);

	svm->vmcb->save.cr3 = root;
A
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	force_new_asid(vcpu);
A
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1742 1743

	if (vcpu->fpu_active) {
1744 1745
		svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
		svm->vmcb->save.cr0 |= X86_CR0_TS;
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		vcpu->fpu_active = 0;
	}
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}

static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
				  unsigned long  addr,
				  uint32_t err_code)
{
1754 1755
	struct vcpu_svm *svm = to_svm(vcpu);
	uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
A
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A
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1757
	++vcpu->stat.pf_guest;
A
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1758 1759 1760

	if (is_page_fault(exit_int_info)) {

1761 1762 1763 1764 1765
		svm->vmcb->control.event_inj_err = 0;
		svm->vmcb->control.event_inj = 	SVM_EVTINJ_VALID |
						SVM_EVTINJ_VALID_ERR |
						SVM_EVTINJ_TYPE_EXEPT |
						DF_VECTOR;
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		return;
	}
	vcpu->cr2 = addr;
1769 1770 1771 1772 1773 1774
	svm->vmcb->save.cr2 = addr;
	svm->vmcb->control.event_inj = 	SVM_EVTINJ_VALID |
					SVM_EVTINJ_VALID_ERR |
					SVM_EVTINJ_TYPE_EXEPT |
					PF_VECTOR;
	svm->vmcb->control.event_inj_err = err_code;
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}


static int is_disabled(void)
{
1780 1781 1782 1783 1784 1785
	u64 vm_cr;

	rdmsrl(MSR_VM_CR, vm_cr);
	if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
		return 1;

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	return 0;
}

I
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static void
svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
{
	/*
	 * Patch in the VMMCALL instruction:
	 */
	hypercall[0] = 0x0f;
	hypercall[1] = 0x01;
	hypercall[2] = 0xd9;
	hypercall[3] = 0xc3;
}

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static struct kvm_arch_ops svm_arch_ops = {
	.cpu_has_kvm_support = has_svm,
	.disabled_by_bios = is_disabled,
	.hardware_setup = svm_hardware_setup,
	.hardware_unsetup = svm_hardware_unsetup,
	.hardware_enable = svm_hardware_enable,
	.hardware_disable = svm_hardware_disable,

	.vcpu_create = svm_create_vcpu,
	.vcpu_free = svm_free_vcpu,

	.vcpu_load = svm_vcpu_load,
	.vcpu_put = svm_vcpu_put,
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	.vcpu_decache = svm_vcpu_decache,
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	.set_guest_debug = svm_guest_debug,
	.get_msr = svm_get_msr,
	.set_msr = svm_set_msr,
	.get_segment_base = svm_get_segment_base,
	.get_segment = svm_get_segment,
	.set_segment = svm_set_segment,
	.get_cs_db_l_bits = svm_get_cs_db_l_bits,
1823
	.decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
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	.set_cr0 = svm_set_cr0,
	.set_cr3 = svm_set_cr3,
	.set_cr4 = svm_set_cr4,
	.set_efer = svm_set_efer,
	.get_idt = svm_get_idt,
	.set_idt = svm_set_idt,
	.get_gdt = svm_get_gdt,
	.set_gdt = svm_set_gdt,
	.get_dr = svm_get_dr,
	.set_dr = svm_set_dr,
	.cache_regs = svm_cache_regs,
	.decache_regs = svm_decache_regs,
	.get_rflags = svm_get_rflags,
	.set_rflags = svm_set_rflags,

	.invlpg = svm_invlpg,
	.tlb_flush = svm_flush_tlb,
	.inject_page_fault = svm_inject_page_fault,

	.inject_gp = svm_inject_gp,

	.run = svm_vcpu_run,
	.skip_emulated_instruction = skip_emulated_instruction,
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	.patch_hypercall = svm_patch_hypercall,
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};

static int __init svm_init(void)
{
1852 1853
	return kvm_init_arch(&svm_arch_ops, sizeof(struct vcpu_svm),
			      THIS_MODULE);
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}

static void __exit svm_exit(void)
{
	kvm_exit_arch();
}

module_init(svm_init)
module_exit(svm_exit)