mpc7448hpc2.dts

/*
 * MPC7448HPC2 (Taiga) board Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 * 2006 Roy Zang <Roy Zang at freescale.com>.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/ {
	model = "mpc7448hpc2";
	compatible = "mpc74xx";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells =<0>;
				
		PowerPC,7448@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;	// 32 bytes
			i-cache-line-size = <20>;	// 32 bytes
			d-cache-size = <8000>;		// L1, 32K bytes
			i-cache-size = <8000>;		// L1, 32K bytes
			timebase-frequency = <0>;	// 33 MHz, from uboot
			clock-frequency = <0>;		// From U-Boot
			bus-frequency = <0>;		// From U-Boot
			32-bit;
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 20000000	// DDR2   512M at 0
		       >;
	};

  	tsi108@c0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "tsi-bridge";
		ranges = <00000000 c0000000 00010000>;
		reg = <c0000000 00010000>;
		bus-frequency = <0>;

		i2c@7000 {
			interrupt-parent = <&mpic>;
			interrupts = <E 0>;
			reg = <7000 400>;
			device_type = "i2c";
			compatible  = "tsi-i2c";
		};

		mdio@6000 {
			device_type = "mdio";
			compatible = "tsi-ethernet";

			phy8: ethernet-phy@6000 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <6000 50>;
				phy-id = <8>;
				device_type = "ethernet-phy";
			};

			phy9: ethernet-phy@6400 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <6000 50>;
				phy-id = <9>;
				device_type = "ethernet-phy";
			};

		};

		ethernet@6200 {
			#size-cells = <0>;
			device_type = "network";
			model = "TSI-ETH";
			compatible = "tsi-ethernet";
			reg = <6000 200>;
			address = [ 00 06 D2 00 00 01 ];
			interrupts = <10 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy8>;
		};

		ethernet@6600 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "TSI-ETH";
			compatible = "tsi-ethernet";
			reg = <6400 200>;
			address = [ 00 06 D2 00 00 02 ];
			interrupts = <11 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy9>;
		};

		serial@7808 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <7808 200>;
			clock-frequency = <3f6b5a00>;
			interrupts = <c 0>;
			interrupt-parent = <&mpic>;
		};

		serial@7c08 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <7c08 200>;
			clock-frequency = <3f6b5a00>;
			interrupts = <d 0>;
			interrupt-parent = <&mpic>;
		};

	  	mpic: pic@7400 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <7400 400>;
			built-in;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
                       	big-endian;
		};
		pci@1000 {
			compatible = "tsi10x";
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = <1000 1000>;
			bus-range = <0 0>;
			ranges = <02000000 0 e0000000 e0000000 0 1A000000	
				  01000000 0 00000000 fa000000 0 00010000>;
			clock-frequency = <7f28154>;
			interrupt-parent = <&mpic>;
			interrupts = <17 2>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <

				/* IDSEL 0x11 */
				0800 0 0 1 &RT0 24 0
				0800 0 0 2 &RT0 25 0
				0800 0 0 3 &RT0 26 0
				0800 0 0 4 &RT0 27 0

				/* IDSEL 0x12 */
				1000 0 0 1 &RT0 25 0
				1000 0 0 2 &RT0 26 0
				1000 0 0 3 &RT0 27 0
				1000 0 0 4 &RT0 24 0

				/* IDSEL 0x13 */
				1800 0 0 1 &RT0 26 0
				1800 0 0 2 &RT0 27 0
				1800 0 0 3 &RT0 24 0
				1800 0 0 4 &RT0 25 0

				/* IDSEL 0x14 */
				2000 0 0 1 &RT0 27 0
				2000 0 0 2 &RT0 24 0
				2000 0 0 3 &RT0 25 0
				2000 0 0 4 &RT0 26 0
				>;

			RT0: router@1180 {
				clock-frequency = <0>;
				interrupt-controller;
				device_type = "pic-router";
				#address-cells = <0>;
				#interrupt-cells = <2>;
				built-in;
				big-endian;
				interrupts = <17 2>;
				interrupt-parent = <&mpic>;
			};
		};
	};

};