proc-v7.S 14.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11
/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
12
#include <linux/init.h>
13 14 15
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
16
#include <asm/hwcap.h>
17 18 19 20 21
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

22 23 24
#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
25
#include "proc-v7-2level.S"
26
#endif
27

28 29
ENTRY(cpu_v7_proc_init)
	mov	pc, lr
30
ENDPROC(cpu_v7_proc_init)
31 32

ENTRY(cpu_v7_proc_fin)
33 34 35 36
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
37
	mov	pc, lr
38
ENDPROC(cpu_v7_proc_fin)
39 40 41 42 43 44 45 46 47

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
48 49 50
 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
51 52
 */
	.align	5
53
	.pushsection	.idmap.text, "ax"
54
ENTRY(cpu_v7_reset)
55 56
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
57
 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
58 59
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
60
	bx	r0
61
ENDPROC(cpu_v7_reset)
62
	.popsection
63 64 65 66 67 68 69 70 71

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
72
	dsb					@ WFI may enter a low-power mode
73
	wfi
74
	mov	pc, lr
75
ENDPROC(cpu_v7_do_idle)
76 77

ENTRY(cpu_v7_dcache_clean_area)
78 79 80 81 82
	ALT_SMP(W(nop))			@ MP extensions imply L1 PTW
	ALT_UP_B(1f)
	mov	pc, lr
1:	dcache_line_size r2, r3
2:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
83 84
	add	r0, r0, r2
	subs	r1, r1, r2
85
	bhi	2b
86
	dsb	ishst
87
	mov	pc, lr
88
ENDPROC(cpu_v7_dcache_clean_area)
89

90
	string	cpu_v7_name, "ARMv7 Processor"
91 92
	.align

93 94
/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
95
.equ	cpu_v7_suspend_size, 4 * 8
96
#ifdef CONFIG_ARM_CPU_SUSPEND
97
ENTRY(cpu_v7_do_suspend)
98
	stmfd	sp!, {r4 - r10, lr}
99
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
100 101
	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
102
#ifdef CONFIG_MMU
103
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
104
	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
105
	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
106
#endif
107 108 109
	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
110
	stmia	r0, {r6 - r11}
111
	ldmfd	sp!, {r4 - r10, pc}
112 113 114 115 116
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
117 118
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
119
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
120
	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
121
	ldmia	r0, {r6 - r11}
122 123
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
124
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
125
#ifndef CONFIG_ARM_LPAE
126 127
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
128
#endif
129 130
	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
131
	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
132 133 134 135
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
136 137 138 139 140
#endif	/* CONFIG_MMU */
	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
141
	isb
142
	dsb
143
	mov	r0, r8			@ control register
144 145
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
#endif

#ifdef CONFIG_CPU_PJ4B
	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
#ifdef CONFIG_PJ4B_ERRATA_4742
ENTRY(cpu_pj4b_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	dsb					@barrier
	mov	pc, lr
ENDPROC(cpu_pj4b_do_idle)
#else
	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
#endif
	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
	globl_equ	cpu_pj4b_do_suspend,	cpu_v7_do_suspend
	globl_equ	cpu_pj4b_do_resume,	cpu_v7_do_resume
	globl_equ	cpu_pj4b_suspend_size,	cpu_v7_suspend_size

169 170
#endif

171 172 173 174 175 176 177 178 179 180 181
/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
P
Pawel Moll 已提交
182
__v7_ca5mp_setup:
183
__v7_ca9mp_setup:
184 185
__v7_cr7mp_setup:
	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
186
	b	1f
P
Pawel Moll 已提交
187
__v7_ca7mp_setup:
188 189 190
__v7_ca15mp_setup:
	mov	r10, #0
1:
191
#ifdef CONFIG_SMP
192 193
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
194
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
195 196 197
	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
198
#endif
199
	b	__v7_setup
200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256

__v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B

/* Auxiliary Debug Modes Control 1 Register */
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */

/* Auxiliary Debug Modes Control 2 Register */
#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)

/* Auxiliary Functional Modes Control Register 0 */
#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */

/* Auxiliary Debug Modes Control 0 Register */
#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */

	/* Auxiliary Debug Modes Control 1 Register */
	mrc	p15, 1,	r0, c15, c1, 1
	orr     r0, r0, #PJ4B_CLEAN_LINE
	orr     r0, r0, #PJ4B_BCK_OFF_STREX
	orr     r0, r0, #PJ4B_INTER_PARITY
	bic	r0, r0, #PJ4B_STATIC_BP
	mcr	p15, 1,	r0, c15, c1, 1

	/* Auxiliary Debug Modes Control 2 Register */
	mrc	p15, 1,	r0, c15, c1, 2
	bic	r0, r0, #PJ4B_FAST_LDR
	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
	mcr	p15, 1,	r0, c15, c1, 2

	/* Auxiliary Functional Modes Control Register 0 */
	mrc	p15, 1,	r0, c15, c2, 0
#ifdef CONFIG_SMP
	orr	r0, r0, #PJ4B_SMP_CFB
#endif
	orr	r0, r0, #PJ4B_L1_PAR_CHK
	orr	r0, r0, #PJ4B_BROADCAST_CACHE
	mcr	p15, 1,	r0, c15, c2, 0

	/* Auxiliary Debug Modes Control 0 Register */
	mrc	p15, 1,	r0, c15, c1, 0
	orr	r0, r0, #PJ4B_WFI_WFE
	mcr	p15, 1,	r0, c15, c1, 0

#endif /* CONFIG_CPU_PJ4B */

257
__v7_setup:
258 259
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
260
	bl      v7_flush_dcache_louis
261
	ldmia	r12, {r0-r5, r7, r9, r11, lr}
262 263 264 265

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
266
	bne	3f
267 268
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
269 270
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number
271

272 273 274 275
	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
276 277
#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)

278 279 280 281
	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
282 283
#endif
#ifdef CONFIG_ARM_ERRATA_458693
284
	teq	r6, #0x20			@ only present in r2p0
285 286 287 288
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
289 290
#endif
#ifdef CONFIG_ARM_ERRATA_460075
291
	teq	r6, #0x20			@ only present in r2p0
292 293 294 295
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
296
#endif
297 298 299 300 301 302 303 304 305 306 307 308
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
309 310 311 312 313 314 315 316 317
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
318
#ifdef CONFIG_ARM_ERRATA_743622
319
	teq	r5, #0x00200000			@ only present in r2p*
320 321 322 323
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
324 325 326
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
	ALT_UP_B(1f)
327 328 329
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
330
1:
331
#endif
332

333 334 335 336 337 338 339 340 341 342 343 344 345
	/* Cortex-A15 Errata */
3:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
	teq	r0, r10
	bne	4f

#ifdef CONFIG_ARM_ERRATA_773022
	cmp	r6, #0x4			@ only present up to r0p4
	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
	orrle	r10, r10, #1 << 1		@ disable loop buffer
	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif

4:	mov	r10, #0
346 347
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
	dsb
348
#ifdef CONFIG_MMU
349
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
350
	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
351 352
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
353 354
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
355 356 357 358 359 360 361 362 363 364 365 366
#endif
#ifndef CONFIG_ARM_THUMBEE
	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
	teq	r0, #(1 << 12)			@ check if ThumbEE is present
	bne	1f
	mov	r5, #0
	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
	orr	r0, r0, #1			@ set the 1st bit in order to
	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
1:
367
#endif
368 369
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
370 371
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
372 373 374 375
#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
376
#endif
377 378 379
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
380
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
381
	mov	pc, lr				@ return to head.S:__ret
382
ENDPROC(__v7_setup)
383

384
	.align	2
385 386 387
__v7_setup_stack:
	.space	4 * 11				@ 11 registers

388 389
	__INITDATA

390 391
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
392 393 394
#ifdef CONFIG_CPU_PJ4B
	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#endif
395

396 397
	.section ".rodata"

398 399
	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
400 401 402 403
	.align

	.section ".proc.info.init", #alloc, #execinstr

404 405 406
	/*
	 * Standard v7 proc info content
	 */
407
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
408
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
409
			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
410
	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
411 412 413
			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
414
	W(b)	\initfunc
415 416
	.long	cpu_arch_name
	.long	cpu_elf_name
417 418
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
419
	.long	cpu_v7_name
420
	.long	\proc_fns
421 422 423
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
424 425
.endm

426
#ifndef CONFIG_ARM_LPAE
P
Pawel Moll 已提交
427 428 429 430 431 432 433 434 435 436
	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

437 438 439 440 441 442 443 444
	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
445
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
446

447 448
#endif	/* CONFIG_ARM_LPAE */

449 450 451
	/*
	 * Marvell PJ4B processor.
	 */
452
#ifdef CONFIG_CPU_PJ4B
453 454
	.type   __v7_pj4b_proc_info, #object
__v7_pj4b_proc_info:
455 456
	.long	0x560f5800
	.long	0xff0fff00
457
	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
458
	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
459
#endif
460

461 462 463 464 465 466 467 468 469 470
	/*
	 * ARM Ltd. Cortex R7 processor.
	 */
	.type	__v7_cr7mp_proc_info, #object
__v7_cr7mp_proc_info:
	.long	0x410fc170
	.long	0xff0ffff0
	__v7_proc __v7_cr7mp_setup
	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info

471 472 473 474 475 476 477
	/*
	 * ARM Ltd. Cortex A7 processor.
	 */
	.type	__v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
	.long	0x410fc070
	.long	0xff0ffff0
478
	__v7_proc __v7_ca7mp_setup
479 480
	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info

481 482 483 484 485 486 487
	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
488
	__v7_proc __v7_ca15mp_setup
489 490
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

491 492 493 494 495 496 497 498 499 500 501 502 503 504 505
	/*
	 * Qualcomm Inc. Krait processors.
	 */
	.type	__krait_proc_info, #object
__krait_proc_info:
	.long	0x510f0400		@ Required ID value
	.long	0xff0ffc00		@ Mask for ID
	/*
	 * Some Krait processors don't indicate support for SDIV and UDIV
	 * instructions in the ARM instruction set, even though they actually
	 * do support them.
	 */
	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	.size	__krait_proc_info, . - __krait_proc_info

506 507 508 509 510 511 512
	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
513
	__v7_proc __v7_setup
514
	.size	__v7_proc_info, . - __v7_proc_info