[BSP] Add i.MXRT libraires.

bsp/imxrt/Libraries/imxrt1050/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/SConscript

+# RT-Thread building script for component
+
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('drivers/*.c') + Glob('*.c')
+
+CPPPATH = [cwd, cwd + '/drivers', cwd + '/utilities']
+CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/gcc/startup_MIMXRT1052.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/arm/startup_MIMXRT1052.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/iar/startup_MIMXRT1052.s']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor.scf

+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVL5A
+**                          MIMXRT1052DVL6A
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.C, 08/2017
+**     Version:             rev. 0.1, 2017-01-10
+**     Build:               b170927
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     1. Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     2. Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     3. Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_flash_config_start           0x60000000
+#define m_flash_config_size            0x00001000
+
+#define m_ivt_start                    0x60001000
+#define m_ivt_size                     0x00001000
+
+#define m_text_start                   0x60002000
+#define m_text_size                    0x1F7FE000
+
+#define m_data_start                   0x20000000
+#define m_data_size                    0x00020000
+
+#define m_ncache_start                 0x81E00000
+#define m_ncache_size                  0x00200000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x1000
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+/* #include "../../rtconfig.h" */
+
+#if (defined(BOARD_USING_HYPERFLASH))
+LR_m_rom_config m_flash_config_start m_flash_config_size      ; load region size_region
+{   
+    RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
+    { 
+        * (.boot_hdr.conf, +FIRST)
+    }  
+}
+
+LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
+{   
+    RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
+    { 
+        * (.boot_hdr.ivt, +FIRST)
+        * (.boot_hdr.boot_data)
+        * (.boot_hdr.dcd_data)
+    }   
+}
+#endif
+
+#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
+
+; load region size_region
+LR_IROM1 m_text_start m_text_size 
+{   
+    ER_IROM1 m_text_start m_text_size ; load address = execution address
+    { 
+        * (RESET,+FIRST)
+        * (InRoot$$Sections)
+        .ANY (+RO)
+    }
+  
+    RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
+    { 
+        .ANY (+RW +ZI)
+    }
+    
+    ARM_LIB_HEAP +0 EMPTY Heap_Size{}   ; Heap region growing up
+    ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
+    RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
+
+    ; ncache RW data
+    RW_m_ncache m_ncache_start m_ncache_size 
+    { 
+        * (NonCacheable.init)
+        * (NonCacheable)
+    }
+}
+
+

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor_sdram.scf

+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 0.1, 2017-01-10
+**     Build:               b180509
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     The Clear BSD License
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_flash_config_start           0x60000000
+#define m_flash_config_size            0x00001000
+
+#define m_ivt_start                    0x60001000
+#define m_ivt_size                     0x00001000
+
+#define m_interrupts_start             0x60002000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x60002400
+#define m_text_size                    0x03FFDC00
+
+#define m_data_start                   0x80000000
+#define m_data_size                    0x01E00000
+
+#define m_ncache_start                 0x81E00000
+#define m_ncache_size                  0x00200000
+
+#define m_data2_start                  0x20000000
+#define m_data2_size                   0x00020000
+
+#define m_data3_start                  0x20200000
+#define m_data3_size                   0x00040000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_rom_config m_flash_config_start m_flash_config_size {   ; load region size_region
+	RW_m_config_text m_flash_config_start m_flash_config_size { ; load address = execution address
+	* (.boot_hdr.conf, +FIRST)
+	}
+}
+
+LR_m_rom_ivt m_ivt_start m_ivt_size {   ; load region size_region
+	RW_m_ivt_text m_ivt_start m_ivt_size { ; load address = execution address
+	* (.boot_hdr.ivt, +FIRST)
+	* (.boot_hdr.boot_data)
+	* (.boot_hdr.dcd_data)
+	}
+}
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size {   ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    *(m_usb_dma_init_data)
+    *(m_usb_dma_noninit_data)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+  RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+}

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_ram.scf

+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 0.1, 2017-01-10
+**     Build:               b180509
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     The Clear BSD License
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x00000400
+#define m_text_size                    0x0001FC00
+
+#define m_data_start                   0x20000000
+#define m_data_size                    0x00020000
+
+#define m_data2_start                  0x20200000
+#define m_data2_size                   0x00040000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size {   ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+}

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram.scf

+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 0.1, 2017-01-10
+**     Build:               b180509
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     The Clear BSD License
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x00000400
+#define m_text_size                    0x0001FC00
+
+#define m_data_start                   0x80000000
+#define m_data_size                    0x01E00000
+
+#define m_ncache_start                 0x81E00000
+#define m_ncache_size                  0x00200000
+
+#define m_data2_start                  0x20000000
+#define m_data2_size                   0x00020000
+
+#define m_data3_start                  0x20200000
+#define m_data3_size                   0x00040000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size {   ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    *(m_usb_dma_init_data)
+    *(m_usb_dma_noninit_data)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+  RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+}

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram_txt.scf

+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 0.1, 2017-01-10
+**     Build:               b180509
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     The Clear BSD License
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start             0x80000000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x80000400
+#define m_text_size                    0x001FFC00
+
+#define m_data_start                   0x20200000
+#define m_data_size                    0x00040000
+
+#define m_data2_start                  0x20000000
+#define m_data2_size                   0x00020000
+
+#define m_data3_start                  0x80200000
+#define m_data3_size                   0x01C00000
+
+#define m_ncache_start                 0x81E00000
+#define m_ncache_size                  0x00200000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size {   ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    *(m_usb_dma_init_data)
+    *(m_usb_dma_noninit_data)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+  RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+}

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.h

+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FSL_LPI2C_CMSIS_H_
+#define _FSL_LPI2C_CMSIS_H_
+
+#include "fsl_common.h"
+#include "Driver_I2C.h"
+#include "RTE_Device.h"
+#include "fsl_lpi2c.h"
+#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
+#include "fsl_dmamux.h"
+#endif
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_lpi2c_dma.h"
+#endif
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+#include "fsl_lpi2c_edma.h"
+#endif
+
+#if defined(LPI2C0)
+extern ARM_DRIVER_I2C Driver_I2C0;
+#endif /* LPI2C0 */
+
+#if defined(LPI2C1)
+extern ARM_DRIVER_I2C Driver_I2C1;
+#endif /* LPI2C1 */
+
+#if defined(LPI2C2)
+extern ARM_DRIVER_I2C Driver_I2C2;
+#endif /* LPI2C2 */
+
+#if defined(LPI2C3)
+extern ARM_DRIVER_I2C Driver_I2C3;
+#endif /* LPI2C3 */
+
+#if defined(LPI2C4)
+extern ARM_DRIVER_I2C Driver_I2C4;
+#endif /* LPI2C4 */
+
+#if defined(LPI2C5)
+extern ARM_DRIVER_I2C Driver_I2C5;
+#endif /* LPI2C5*/
+
+#if defined(LPI2C6)
+extern ARM_DRIVER_I2C Driver_I2C6;
+#endif /* LPI2C6 */
+
+/* I2C Driver state flags */
+#define I2C_FLAG_UNINIT (0)
+#define I2C_FLAG_INIT (1 << 0)
+#define I2C_FLAG_POWER (1 << 1)
+
+#endif /* _FSL_LPI2C_CMSIS_H_ */

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.h

+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FSL_LPSPI_CMSISI_H_
+#define _FSL_LPSPI_CMSISI_H_
+
+#include "fsl_common.h"
+#include "RTE_Device.h"
+#include "Driver_SPI.h"
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+#include "fsl_lpspi_edma.h"
+#endif
+#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
+#include "fsl_dmamux.h"
+#endif
+
+#if defined(LPSPI0)
+extern ARM_DRIVER_SPI Driver_SPI0;
+#endif /* LPSPI0 */
+
+#if defined(LPSPI1)
+extern ARM_DRIVER_SPI Driver_SPI1;
+#endif /* LPSPI1 */
+
+#if defined(LPSPI2)
+extern ARM_DRIVER_SPI Driver_SPI2;
+#endif /* LPSPI2 */
+
+#if defined(LPSPI3)
+extern ARM_DRIVER_SPI Driver_SPI3;
+#endif /* LPSPI3 */
+
+#if defined(LPSPI4)
+extern ARM_DRIVER_SPI Driver_SPI4;
+#endif /* LPSPI4 */
+
+#if defined(LPSPI5)
+extern ARM_DRIVER_SPI Driver_SPI5;
+#endif /* LPSPI5 */
+
+/* SPI Driver state flags */
+#define SPI_FLAG_UNINIT (0)
+#define SPI_FLAG_INIT (1 << 0)
+#define SPI_FLAG_POWER (1 << 1)
+#define SPI_FLAG_CONFIGURED (1 << 2)
+
+#endif

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.h

+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FSL_LPUART_CMSIS_H_
+#define _FSL_LPUART_CMSIS_H_
+
+#include "fsl_common.h"
+#include "Driver_USART.h"
+#include "RTE_Device.h"
+#include "fsl_lpuart.h"
+#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
+#include "fsl_dmamux.h"
+#endif
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_lpuart_dma.h"
+#endif
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+#include "fsl_lpuart_edma.h"
+#endif
+
+#if defined(LPUART0)
+extern ARM_DRIVER_USART Driver_USART0;
+#endif /* LPUART0 */
+
+#if defined(LPUART1)
+extern ARM_DRIVER_USART Driver_USART1;
+#endif /* LPUART1 */
+
+#if defined(LPUART2)
+extern ARM_DRIVER_USART Driver_USART2;
+#endif /* LPUART2 */
+
+#if defined(LPUART3)
+extern ARM_DRIVER_USART Driver_USART3;
+#endif /* LPUART3 */
+
+#if defined(LPUART4)
+extern ARM_DRIVER_USART Driver_USART4;
+#endif /* LPUART4 */
+
+#if defined(LPUART5)
+extern ARM_DRIVER_USART Driver_USART5;
+#endif /* LPUART5 */
+
+#if defined(LPUART6)
+extern ARM_DRIVER_USART Driver_USART6;
+#endif /* LPUART6 */
+
+#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 3)
+
+extern ARM_DRIVER_USART Driver_USART3;
+
+#endif
+
+#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 4)
+
+extern ARM_DRIVER_USART Driver_USART4;
+
+#endif
+
+#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 5)
+extern ARM_DRIVER_USART Driver_USART5;
+
+#endif
+
+/* USART Driver state flags */
+#define USART_FLAG_UNINIT (0)
+#define USART_FLAG_INIT (1 << 0)
+#define USART_FLAG_POWER (1 << 1)
+#define USART_FLAG_CONFIGURED (1 << 2)
+
+#endif /* _FSL_LPUART_CMSIS_H_ */

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.c

+/*
+ * The Clear BSD License
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
+#endif
+
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for ADC module.
+ *
+ * @param base ADC peripheral base address
+ */
+static uint32_t ADC_GetInstance(ADC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to ADC bases for each instance. */
+static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
+
+/*! @brief Pointers to ADC clocks for each instance. */
+static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t ADC_GetInstance(ADC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
+    {
+        if (s_adcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_adcBases));
+
+    return instance;
+}
+
+void ADC_Init(ADC_Type *base, const adc_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32;
+
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+    /* ADCx_CFG */
+    tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
+    tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
+             ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution);
+    if (config->enableOverWrite)
+    {
+        tmp32 |= ADC_CFG_OVWREN_MASK;
+    }
+    if (config->enableLongSample)
+    {
+        tmp32 |= ADC_CFG_ADLSMP_MASK;
+    }
+    if (config->enableLowPower)
+    {
+        tmp32 |= ADC_CFG_ADLPC_MASK;
+    }
+    if (config->enableHighSpeed)
+    {
+        tmp32 |= ADC_CFG_ADHSC_MASK;
+    }
+    base->CFG = tmp32;
+
+    /* ADCx_GC  */
+    tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK);
+    if (config->enableContinuousConversion)
+    {
+        tmp32 |= ADC_GC_ADCO_MASK;
+    }
+    if (config->enableAsynchronousClockOutput)
+    {
+        tmp32 |= ADC_GC_ADACKEN_MASK;
+    }
+    base->GC = tmp32;
+}
+
+void ADC_Deinit(ADC_Type *base)
+{
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+}
+
+void ADC_GetDefaultConfig(adc_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableAsynchronousClockOutput = true;
+    config->enableOverWrite = false;
+    config->enableContinuousConversion = false;
+    config->enableHighSpeed = false;
+    config->enableLowPower = false;
+    config->enableLongSample = false;
+    config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
+    config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
+    config->clockSource = kADC_ClockSourceAD;
+    config->clockDriver = kADC_ClockDriver1;
+    config->resolution = kADC_Resolution12Bit;
+}
+
+void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
+{
+    assert(NULL != config);
+    assert(channelGroup < ADC_HC_COUNT);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_HC_ADCH(config->channelNumber);
+    if (config->enableInterruptOnConversionCompleted)
+    {
+        tmp32 |= ADC_HC_AIEN_MASK;
+    }
+    base->HC[channelGroup] = tmp32;
+}
+
+/*
+ *To complete calibration, the user must follow the below procedure:
+ *  1. Configure ADC_CFG with actual operating values for maximum accuracy.
+ *  2. Configure the ADC_GC values along with CAL bit.
+ *  3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
+ *  4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
+ */
+status_t ADC_DoAutoCalibration(ADC_Type *base)
+{
+    status_t status = kStatus_Success;
+#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
+    bool bHWTrigger = false;
+
+    /* The calibration would be failed when in hardwar mode.
+     * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
+    if (0U != (ADC_CFG_ADTRG_MASK & base->CFG))
+    {
+        bHWTrigger = true;
+        ADC_EnableHardwareTrigger(base, false);
+    }
+#endif
+
+    /* Clear the CALF and launch the calibration. */
+    base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */
+    base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */
+
+    /* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */
+    while (0U != (base->GC & ADC_GC_CAL_MASK))
+    {
+        /* Check the CALF when the calibration is active. */
+        if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag))
+        {
+            status = kStatus_Fail;
+            break;
+        }
+    }
+
+    /* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */
+    if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */
+    {
+        status = kStatus_Fail;
+    }
+    if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */
+    {
+        status = kStatus_Fail;
+    }
+
+    /* Clear conversion done flag. */
+    ADC_GetChannelConversionValue(base, 0U);
+
+#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
+    /* Restore original trigger mode. */
+    if (true == bHWTrigger)
+    {
+        ADC_EnableHardwareTrigger(base, true);
+    }
+#endif
+
+    return status;
+}
+
+void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_OFS_OFS(config->offsetValue);
+    if (config->enableSigned)
+    {
+        tmp32 |= ADC_OFS_SIGN_MASK;
+    }
+    base->OFS = tmp32;
+}
+
+void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
+{
+    uint32_t tmp32;
+
+    tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK);
+    if (NULL == config) /* Pass "NULL" to disable the feature. */
+    {
+        base->GC = tmp32;
+        return;
+    }
+    /* Enable the feature. */
+    tmp32 |= ADC_GC_ACFE_MASK;
+
+    /* Select the hardware compare working mode. */
+    switch (config->hardwareCompareMode)
+    {
+        case kADC_HardwareCompareMode0:
+            break;
+        case kADC_HardwareCompareMode1:
+            tmp32 |= ADC_GC_ACFGT_MASK;
+            break;
+        case kADC_HardwareCompareMode2:
+            tmp32 |= ADC_GC_ACREN_MASK;
+            break;
+        case kADC_HardwareCompareMode3:
+            tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK;
+            break;
+        default:
+            break;
+    }
+    base->GC = tmp32;
+
+    /* Load the compare values. */
+    tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
+    base->CV = tmp32;
+}
+
+void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
+{
+    uint32_t tmp32;
+
+    if (mode == kADC_HardwareAverageDiasable)
+    {
+        base->GC &= ~ADC_GC_AVGE_MASK;
+    }
+    else
+    {
+        tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK;
+        tmp32 |= ADC_CFG_AVGS(mode);
+        base->CFG = tmp32;
+        base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */
+    }
+}
+
+void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
+{
+    uint32_t tmp32 = 0;
+
+    if (0U != (mask & kADC_CalibrationFailedFlag))
+    {
+        tmp32 |= ADC_GS_CALF_MASK;
+    }
+    if (0U != (mask & kADC_ConversionActiveFlag))
+    {
+        tmp32 |= ADC_GS_ADACT_MASK;
+    }
+    base->GS = tmp32;
+}

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.c

+/*
+ * The Clear BSD License
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_aipstz.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.aipstz"
+#endif
+
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
+{
+    uint32_t mask = ((uint32_t)master >> 8) - 1;
+    uint32_t shift = (uint32_t)master & 0xFF;
+    base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
+}
+
+void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
+{
+    volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
+    uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
+    uint32_t shift = (uint32_t)peripheral & 0xFF;
+
+    *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
+}
+
+