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5d32b5d2
编写于
12月 07, 2020
作者:
0
0xcccccccccccc
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
- fix indentations.
上级
0fc2b13b
变更
13
展开全部
隐藏空白更改
内联
并排
Showing
13 changed file
with
1054 addition
and
997 deletion
+1054
-997
bsp/ls2kdev/applications/main.c
bsp/ls2kdev/applications/main.c
+2
-2
bsp/ls2kdev/drivers/board.c
bsp/ls2kdev/drivers/board.c
+3
-3
bsp/ls2kdev/drivers/clk.c
bsp/ls2kdev/drivers/clk.c
+2
-1
bsp/ls2kdev/drivers/drv_gpio.c
bsp/ls2kdev/drivers/drv_gpio.c
+20
-17
bsp/ls2kdev/drivers/drv_pwm.c
bsp/ls2kdev/drivers/drv_pwm.c
+10
-5
bsp/ls2kdev/drivers/drv_rtc.c
bsp/ls2kdev/drivers/drv_rtc.c
+9
-5
bsp/ls2kdev/drivers/drv_spi.c
bsp/ls2kdev/drivers/drv_spi.c
+106
-103
bsp/ls2kdev/drivers/drv_uart.c
bsp/ls2kdev/drivers/drv_uart.c
+36
-35
bsp/ls2kdev/drivers/interrupt.c
bsp/ls2kdev/drivers/interrupt.c
+16
-16
bsp/ls2kdev/drivers/net/mii.c
bsp/ls2kdev/drivers/net/mii.c
+24
-16
bsp/ls2kdev/drivers/net/synopGMAC.c
bsp/ls2kdev/drivers/net/synopGMAC.c
+43
-43
bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
+761
-732
bsp/ls2kdev/drivers/net/synopGMAC_plat.c
bsp/ls2kdev/drivers/net/synopGMAC_plat.c
+22
-19
未找到文件。
bsp/ls2kdev/applications/main.c
浏览文件 @
5d32b5d2
...
...
@@ -10,8 +10,8 @@
#include <rtthread.h>
int
main
(
int
argc
,
char
**
argv
)
{
int
main
(
int
argc
,
char
**
argv
)
{
rt_kprintf
(
"Hi, this is RT-Thread!!
\n
"
);
return
0
;
}
bsp/ls2kdev/drivers/board.c
浏览文件 @
5d32b5d2
...
...
@@ -67,7 +67,7 @@ void rt_hw_timer_handler(void)
*/
void
rt_hw_timer_init
(
void
)
{
write_c0_compare
(
CPU_HZ
/
2
/
RT_TICK_PER_SECOND
);
write_c0_compare
(
CPU_HZ
/
2
/
RT_TICK_PER_SECOND
);
write_c0_count
(
0
);
mips_unmask_cpu_irq
(
7
);
}
...
...
@@ -94,12 +94,12 @@ void rt_hw_board_init(void)
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init
((
void
*
)
RT_HW_HEAP_BEGIN
,
(
void
*
)
RT_HW_HEAP_END
);
rt_system_heap_init
((
void
*
)
RT_HW_HEAP_BEGIN
,
(
void
*
)
RT_HW_HEAP_END
);
#endif
/* init operating system timer */
rt_hw_timer_init
();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init
();
#endif
...
...
bsp/ls2kdev/drivers/clk.c
浏览文件 @
5d32b5d2
...
...
@@ -14,7 +14,8 @@
#include <rtthread.h>
#include "ls2k1000.h"
struct
loongson_pll
{
struct
loongson_pll
{
rt_uint64_t
PLL_SYS_0
;
rt_uint64_t
PLL_SYS_1
;
rt_uint64_t
PLL_DDR_0
;
...
...
bsp/ls2kdev/drivers/drv_gpio.c
浏览文件 @
5d32b5d2
...
...
@@ -25,7 +25,8 @@ static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t
gpio
=
(
void
*
)
device
->
user_data
;
m
=
(
rt_uint64_t
)
1
<<
pin
;
switch
(
mode
)
{
switch
(
mode
)
{
case
PIN_MODE_OUTPUT
:
gpio
->
GPIO0_OEN
&=
~
m
;
break
;
...
...
@@ -52,7 +53,8 @@ static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_base_
struct
loongson_gpio
*
gpio
;
rt_uint64_t
m
;
if
(
pin
<
0
||
pin
>=
60
)
{
if
(
pin
<
0
||
pin
>=
60
)
{
rt_kprintf
(
"error
\n
"
);
return
;
}
...
...
@@ -90,11 +92,11 @@ static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin
gpio
=
(
void
*
)
device
->
user_data
;
if
(
pin
<
4
)
if
(
pin
<
4
)
{
index
=
pin
;
}
else
if
(
pin
<
32
)
else
if
(
pin
<
32
)
{
index
=
5
;
}
...
...
@@ -102,7 +104,7 @@ static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin
{
index
=
6
;
}
_g_gpio_irq_tbl
[
index
].
irq_cb
[
pin
]
=
hdr
;
_g_gpio_irq_tbl
[
index
].
irq_arg
[
pin
]
=
args
;
_g_gpio_irq_tbl
[
index
].
irq_type
[
pin
]
=
mode
;
...
...
@@ -120,11 +122,11 @@ static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin
gpio
=
(
void
*
)
device
->
user_data
;
rt_uint8_t
index
;
if
(
pin
<
4
)
if
(
pin
<
4
)
{
index
=
pin
;
}
else
if
(
pin
<
32
)
else
if
(
pin
<
32
)
{
index
=
5
;
}
...
...
@@ -146,11 +148,11 @@ static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin,
gpio
=
(
void
*
)
device
->
user_data
;
rt_uint8_t
index
;
if
(
pin
<
4
)
if
(
pin
<
4
)
{
index
=
pin
;
}
else
if
(
pin
<
32
)
else
if
(
pin
<
32
)
{
index
=
5
;
}
...
...
@@ -173,23 +175,23 @@ static void gpio_irq_handler(int irq, void *param)
rt_uint32_t
value
;
rt_uint32_t
tmpvalue
;
if
(
irq
==
LS2K_GPIO0_INT_IRQ
)
if
(
irq
==
LS2K_GPIO0_INT_IRQ
)
{
pin
=
0
;
}
else
if
(
irq
==
LS2K_GPIO1_INT_IRQ
)
else
if
(
irq
==
LS2K_GPIO1_INT_IRQ
)
{
pin
=
1
;
}
else
if
(
irq
==
LS2K_GPIO2_INT_IRQ
)
else
if
(
irq
==
LS2K_GPIO2_INT_IRQ
)
{
pin
=
2
;
}
else
if
(
irq
==
LS2K_GPIO3_INT_IRQ
)
else
if
(
irq
==
LS2K_GPIO3_INT_IRQ
)
{
pin
=
3
;
}
else
if
(
irq
==
LS2K_GPIO_INTLO_IRQ
)
else
if
(
irq
==
LS2K_GPIO_INTLO_IRQ
)
{
pin
=
4
;
}
...
...
@@ -197,12 +199,12 @@ static void gpio_irq_handler(int irq, void *param)
{
pin
=
32
;
}
while
(
value
)
{
if
((
value
&
0x1
)
&&
(
irq_def
->
irq_cb
[
pin
]
!=
RT_NULL
))
{
if
(
irq_def
->
state
[
pin
])
if
(
irq_def
->
state
[
pin
])
{
irq_def
->
irq_cb
[
pin
](
irq_def
->
irq_arg
[
pin
]);
}
...
...
@@ -212,7 +214,8 @@ static void gpio_irq_handler(int irq, void *param)
}
}
static
struct
rt_pin_ops
loongson_pin_ops
=
{
static
struct
rt_pin_ops
loongson_pin_ops
=
{
.
pin_mode
=
loongson_pin_mode
,
.
pin_write
=
loongson_pin_write
,
.
pin_read
=
loongson_pin_read
,
...
...
bsp/ls2kdev/drivers/drv_pwm.c
浏览文件 @
5d32b5d2
...
...
@@ -28,7 +28,8 @@
#define CTRL_INVERT (1UL<<9)
#define CTRL_DZONE (1UL<<10)
struct
loongson_pwm
{
struct
loongson_pwm
{
rt_uint32_t
__PAD0
;
rt_uint32_t
low_buffer
;
rt_uint32_t
full_buffer
;
...
...
@@ -91,7 +92,8 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
cfg
=
(
void
*
)
arg
;
switch
(
cmd
)
{
switch
(
cmd
)
{
case
PWM_CMD_ENABLE
:
rc
=
loongson_pwm_enable
(
device
,
cfg
->
channel
);
break
;
...
...
@@ -111,18 +113,21 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
return
rc
;
}
struct
rt_pwm_ops
loongson_pwm_ops
=
{
struct
rt_pwm_ops
loongson_pwm_ops
=
{
.
control
=
loongson_pwm_ioctl
,
};
struct
rt_device_pwm
loongson_pwm
=
{
struct
rt_device_pwm
loongson_pwm
=
{
.
ops
=
&
loongson_pwm_ops
,
};
int
loongson_pwm_init
(
void
)
{
int
rc
=
RT_EOK
;
static
rt_uint32_t
*
priv
[]
=
{
static
rt_uint32_t
*
priv
[]
=
{
(
void
*
)
PWM0_BASE
,
(
void
*
)
PWM1_BASE
,
(
void
*
)
PWM2_BASE
,
...
...
bsp/ls2kdev/drivers/drv_rtc.c
浏览文件 @
5d32b5d2
...
...
@@ -19,7 +19,8 @@
#ifdef RT_USING_RTC
struct
loongson_rtc
{
struct
loongson_rtc
{
rt_uint32_t
sys_toytrim
;
rt_uint32_t
sys_toywrite0
;
rt_uint32_t
sys_toywrite1
;
...
...
@@ -45,7 +46,8 @@ struct loongson_rtc {
#define __BF(number, n, m) __RBF((number>>m), (n-m+1))
#define BF(number, n, m) (m<n ? __BF(number, n, m) : __BF(number, m, n))
struct
rtctime
{
struct
rtctime
{
rt_uint32_t
sys_toyread0
;
rt_uint32_t
sys_toyread1
;
rt_uint32_t
sys_rtcread0
;
...
...
@@ -106,7 +108,7 @@ static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
return
RT_EOK
;
}
static
rt_size_t
rt_rtc_read
(
rt_device_t
dev
,
rt_off_t
pos
,
void
*
buffer
,
rt_size_t
size
)
static
rt_size_t
rt_rtc_read
(
rt_device_t
dev
,
rt_off_t
pos
,
void
*
buffer
,
rt_size_t
size
)
{
return
0
;
}
...
...
@@ -133,7 +135,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
rtctm
.
sys_rtcread0
=
hw_rtc
->
sys_rtcread0
;
tmptime
=
*
localrtctime
(
&
rtctm
);
switch
(
cmd
)
{
switch
(
cmd
)
{
case
RT_DEVICE_CTRL_RTC_GET_TIME
:
*
t
=
mktime
(
&
tmptime
);
break
;
...
...
@@ -164,7 +167,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
int
rt_hw_rtc_init
(
void
)
{
static
struct
rt_device
rtc
=
{
static
struct
rt_device
rtc
=
{
.
type
=
RT_Device_Class_RTC
,
.
init
=
RT_NULL
,
.
open
=
rt_rtc_open
,
...
...
bsp/ls2kdev/drivers/drv_spi.c
浏览文件 @
5d32b5d2
...
...
@@ -11,142 +11,144 @@
static
void
spi_init
(
uint8_t
spre_spr
,
uint8_t
copl
,
uint8_t
cpha
)
{
//rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha);
int
d
;
SET_SPI
(
SPSR
,
0xc0
|
(
spre_spr
&
0
b00000011
));
SET_SPI
(
PARAM
,
0x40
);
SET_SPI
(
PARAM2
,
0x01
);
SET_SPI
(
SPER
,
(
spre_spr
&
0
b00001100
)
>>
2
);
SET_SPI
(
SPCR
,
0x50
|
copl
<<
3
|
cpha
<<
2
);
SET_SPI
(
SOFTCS
,
0xff
);
static
void
spi_init
(
uint8_t
spre_spr
,
uint8_t
copl
,
uint8_t
cpha
)
{
//rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha);
int
d
;
SET_SPI
(
SPSR
,
0xc0
|
(
spre_spr
&
0
b00000011
));
SET_SPI
(
PARAM
,
0x40
);
SET_SPI
(
PARAM2
,
0x01
);
SET_SPI
(
SPER
,
(
spre_spr
&
0
b00001100
)
>>
2
);
SET_SPI
(
SPCR
,
0x50
|
copl
<<
3
|
cpha
<<
2
);
SET_SPI
(
SOFTCS
,
0xff
);
}
static
void
spi_set_csn
(
uint8_t
val
)
//old method
{
SET_SPI
(
SOFTCS
,
val
);
SET_SPI
(
SOFTCS
,
val
);
}
// #define RT_USING_SPI_GPIOCS
#ifdef RT_USING_SPI_GPIOCS
#include <drivers/pin.h>
#include <drivers/pin.h>
#endif
static
void
spi_set_cs
(
unsigned
char
cs
,
int
new_status
)
{
if
(
cs
<
4
){
if
(
cs
<
4
)
{
unsigned
char
val
=
0
;
val
=
GET_SPI
(
SOFTCS
);
val
|=
0x01
<<
cs
;
// csen=1
if
(
new_status
)
// cs = 1
{
val
|=
(
0x10
<<
cs
);
// csn=1
}
else
// cs = 0
{
val
&=
~
(
0x10
<<
cs
);
// csn=0
}
SET_SPI
(
SOFTCS
,
val
);
val
=
GET_SPI
(
SOFTCS
);
val
|=
0x01
<<
cs
;
// csen=1
if
(
new_status
)
// cs = 1
{
val
|=
(
0x10
<<
cs
);
// csn=1
}
else
// cs = 0
{
val
&=
~
(
0x10
<<
cs
);
// csn=0
}
SET_SPI
(
SOFTCS
,
val
);
return
;
return
;
}
#ifdef RT_USING_SPI_GPIOCS
else
{
#ifdef RT_USING_SPI_GPIOCS
else
{
//rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n ");
//rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status);
rt_pin_mode
(
cs
,
PIN_MODE_OUTPUT
);
rt_pin_write
(
cs
,
new_status
);
rt_pin_mode
(
cs
,
PIN_MODE_OUTPUT
);
rt_pin_write
(
cs
,
new_status
);
}
#endif
#endif
}
static
uint8_t
spi_write_for_response
(
uint8_t
data
)
{
uint8_t
val
;
SET_SPI
(
TXFIFO
,
data
);
while
((
GET_SPI
(
SPSR
))
&
RFEMPTY
);
//wait for echo
val
=
GET_SPI
(
RXFIFO
);
return
val
;
uint8_t
val
;
SET_SPI
(
TXFIFO
,
data
);
while
((
GET_SPI
(
SPSR
))
&
RFEMPTY
);
//wait for echo
val
=
GET_SPI
(
RXFIFO
);
return
val
;
}
static
int
cmd_spi_init
(
int
argc
,
char
*
argv
[])
static
int
cmd_spi_init
(
int
argc
,
char
*
argv
[])
{
uint8_t
spre_spr
,
cpol
,
cpha
;
switch
(
argc
)
{
case
2
:
spre_spr
=
strtoul
(
argv
[
1
],
NULL
,
0
);
spi_init
(
spre_spr
,
0
,
0
);
break
;
case
4
:
spre_spr
=
strtoul
(
argv
[
1
],
NULL
,
0
);
cpol
=
strtoul
(
argv
[
2
],
NULL
,
0
);
cpha
=
strtoul
(
argv
[
3
],
NULL
,
0
);
spi_init
(
spre_spr
,
0
,
0
);
break
;
default:
printf
(
"
\n
usage : cmd_spi_init spre_spr <cpol> <cpha>
\n
(cmd_spi_init 0x4 0x0 0x0)
\n
0x4:div8 0xb:div4096
\n
"
);
break
;
}
uint8_t
spre_spr
,
cpol
,
cpha
;
switch
(
argc
)
{
case
2
:
spre_spr
=
strtoul
(
argv
[
1
],
NULL
,
0
);
spi_init
(
spre_spr
,
0
,
0
);
break
;
case
4
:
spre_spr
=
strtoul
(
argv
[
1
],
NULL
,
0
);
cpol
=
strtoul
(
argv
[
2
],
NULL
,
0
);
cpha
=
strtoul
(
argv
[
3
],
NULL
,
0
);
spi_init
(
spre_spr
,
0
,
0
);
break
;
default:
printf
(
"
\n
usage : cmd_spi_init spre_spr <cpol> <cpha>
\n
(cmd_spi_init 0x4 0x0 0x0)
\n
0x4:div8 0xb:div4096
\n
"
);
break
;
}
}
MSH_CMD_EXPORT
(
cmd_spi_init
,
cmd_spi_init
);
MSH_CMD_EXPORT
(
cmd_spi_init
,
cmd_spi_init
);
static
int
cmd_spi_set_csn
(
int
argc
,
char
*
argv
[])
static
int
cmd_spi_set_csn
(
int
argc
,
char
*
argv
[])
{
uint8_t
val
,
csn
;
switch
(
argc
)
{
case
3
:
csn
=
strtoul
(
argv
[
1
],
NULL
,
0
);
val
=
strtoul
(
argv
[
2
],
NULL
,
0
);
spi_set_cs
(
csn
,
val
);
break
;
default:
printf
(
"usage:cmd_spi_set_csn csn val
\n
(0xbf for csn1 enable,0xff for csn1 disable)
\n
"
);
break
;
}
uint8_t
val
,
csn
;
switch
(
argc
)
{
case
3
:
csn
=
strtoul
(
argv
[
1
],
NULL
,
0
);
val
=
strtoul
(
argv
[
2
],
NULL
,
0
);
spi_set_cs
(
csn
,
val
);
break
;
default:
printf
(
"usage:cmd_spi_set_csn csn val
\n
(0xbf for csn1 enable,0xff for csn1 disable)
\n
"
);
break
;
}
}
MSH_CMD_EXPORT
(
cmd_spi_set_csn
,
cmd_spi_set_csn
);
MSH_CMD_EXPORT
(
cmd_spi_set_csn
,
cmd_spi_set_csn
);
static
int
cmd_spi_write
(
int
argc
,
char
*
argv
[])
static
int
cmd_spi_write
(
int
argc
,
char
*
argv
[])
{
uint8_t
data
,
resp
;
switch
(
argc
)
{
case
2
:
data
=
strtoul
(
argv
[
1
],
NULL
,
0
);
resp
=
spi_write_for_response
(
data
);
printf
(
"resp:%2X
\n
"
,
resp
);
break
;
default:
printf
(
"usage:cmd_spi_write data
\n
"
);
break
;
}
uint8_t
data
,
resp
;
switch
(
argc
)
{
case
2
:
data
=
strtoul
(
argv
[
1
],
NULL
,
0
);
resp
=
spi_write_for_response
(
data
);
printf
(
"resp:%2X
\n
"
,
resp
);
break
;
default:
printf
(
"usage:cmd_spi_write data
\n
"
);
break
;
}
}
MSH_CMD_EXPORT
(
cmd_spi_write
,
cmd_spi_write
);
MSH_CMD_EXPORT
(
cmd_spi_write
,
cmd_spi_write
);
static
rt_err_t
configure
(
struct
rt_spi_device
*
device
,
struct
rt_spi_configuration
*
configuration
);
static
rt_uint32_t
xfer
(
struct
rt_spi_device
*
device
,
struct
rt_spi_message
*
message
);
const
static
unsigned
char
SPI_DIV_TABLE
[]
=
{
0
b0000
,
0
b0001
,
0
b0100
,
0
b0010
,
0
b0011
,
0
b0101
,
0
b0110
,
0
b0111
,
0
b1000
,
0
b1001
,
0
b1010
,
0
b1011
};
// 2 4 8 16 32 64 128 256 512 1024 2048 4096
const
static
unsigned
char
SPI_DIV_TABLE
[]
=
{
0
b0000
,
0
b0001
,
0
b0100
,
0
b0010
,
0
b0011
,
0
b0101
,
0
b0110
,
0
b0111
,
0
b1000
,
0
b1001
,
0
b1010
,
0
b1011
};
// 2 4 8 16 32 64 128 256 512 1024 2048 4096
static
rt_err_t
configure
(
struct
rt_spi_device
*
device
,
struct
rt_spi_configuration
*
configuration
)
{
unsigned
char
cpol
=
0
;
unsigned
char
cpha
=
0
;
...
...
@@ -173,21 +175,22 @@ static rt_err_t configure(struct rt_spi_device *device,
cpha
=
0
;
}
//rt_kprintf("configure: cpol:%d cpha:%d\n",cpol,cpha);
float
spi_max_speed
=
((
float
)
APB_MAX_SPEED
)
/
(
8
.
0
/
(
float
)
APB_FREQSCALE
);
float
spi_max_speed
=
((
float
)
APB_MAX_SPEED
)
/
(
8
.
0
/
(
float
)
APB_FREQSCALE
);
//rt_kprintf("spi max speed: %ld\n",(unsigned long)spi_max_speed);
uint64_t
div
=
(
uint64_t
)(
spi_max_speed
/
(
float
)
configuration
->
max_hz
);
uint64_t
div
=
(
uint64_t
)(
spi_max_speed
/
(
float
)
configuration
->
max_hz
);
//rt_kprintf("require speed: %ld\n",configuration->max_hz);
int
ctr
=
0
;
while
(
div
!=
1
&&
ctr
<
12
){
int
ctr
=
0
;
while
(
div
!=
1
&&
ctr
<
12
)
{
ctr
++
;
div
=
div
>>
1
;
div
=
div
>>
1
;
}
//rt_kprintf("spi speed set to: %ld\n",(unsigned long)((spi_max_speed)/(float)(1<<ctr)));
spi_init
(
SPI_DIV_TABLE
[
ctr
],
cpol
,
cpha
);
spi_init
(
SPI_DIV_TABLE
[
ctr
],
cpol
,
cpha
);
return
RT_EOK
;
...
...
@@ -208,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device,
RT_ASSERT
(
NULL
!=
device
);
RT_ASSERT
(
NULL
!=
message
);
cs
=
(
unsigned
char
)(
device
->
parent
.
user_data
);
cs
=
(
unsigned
char
)(
device
->
parent
.
user_data
);
size
=
message
->
length
;
//rt_kprintf("[%s] cs=%d\n", __FUNCTION__, cs);
...
...
@@ -258,9 +261,9 @@ static struct rt_spi_ops loongson_spi_ops =
static
struct
rt_spi_bus
loongson_spi
;
static
int
loongson_spi_init
()
{
{
//rt_kprintf("spi_init\n");
return
rt_spi_bus_register
(
&
loongson_spi
,
"spi"
,
&
loongson_spi_ops
);
return
rt_spi_bus_register
(
&
loongson_spi
,
"spi"
,
&
loongson_spi_ops
);
}
INIT_BOARD_EXPORT
(
loongson_spi_init
);
...
...
bsp/ls2kdev/drivers/drv_uart.c
浏览文件 @
5d32b5d2
...
...
@@ -22,41 +22,42 @@
#define TRUE 1
#define FALSE 0
const
struct
serial_configure
config_uart0
=
{
BAUD_RATE_115200
,
/* 921600 bits/s */
DATA_BITS_8
,
/* 8 databits */
STOP_BITS_1
,
/* 1 stopbit */
PARITY_NONE
,
/* No parity */
BIT_ORDER_LSB
,
/* LSB first sent */
NRZ_NORMAL
,
/* Normal mode */
RT_SERIAL_RB_BUFSZ
,
/* Buffer size */
0
const
struct
serial_configure
config_uart0
=
{
BAUD_RATE_115200
,
/* 921600 bits/s */
DATA_BITS_8
,
/* 8 databits */
STOP_BITS_1
,
/* 1 stopbit */
PARITY_NONE
,
/* No parity */
BIT_ORDER_LSB
,
/* LSB first sent */
NRZ_NORMAL
,
/* Normal mode */
RT_SERIAL_RB_BUFSZ
,
/* Buffer size */
0
};
struct
rt_uart_ls2k
{
void
*
base
;
rt_uint32_t
IRQ
;
};
static
rt_err_t
ls2k_uart_set_buad
(
struct
rt_serial_device
*
serial
,
struct
serial_configure
*
cfg
)
static
rt_err_t
ls2k_uart_set_buad
(
struct
rt_serial_device
*
serial
,
struct
serial_configure
*
cfg
)
{
struct
rt_uart_ls2k
*
uart_dev
=
RT_NULL
;
rt_err_t
ret
=
RT_EOK
;
rt_err_t
ret
=
RT_EOK
;
RT_ASSERT
(
serial
!=
RT_NULL
);
RT_ASSERT
(
cfg
!=
RT_NULL
);
uart_dev
=
(
struct
rt_uart_ls2k
*
)
serial
->
parent
.
user_data
;
uint64_t
brtc
=
(
125000000U
)
/
(
16
*
(
cfg
->
baud_rate
));
UART_LCR
(
uart_dev
->
base
)
=
0x80
;
// Activate buadcfg
UART_LSB
(
uart_dev
->
base
)
=
brtc
&
0xff
;
UART_MSB
(
uart_dev
->
base
)
=
brtc
>>
8
;
if
(((((
short
)
UART_MSB
(
uart_dev
->
base
))
<<
8
)
|
UART_LSB
(
uart_dev
->
base
))
!=
brtc
)
ret
=
RT_ERROR
;
UART_LCR
(
uart_dev
->
base
)
=
CFCR_8BITS
;
// Back to normal
UART_MCR
(
uart_dev
->
base
)
=
MCR_IENABLE
/* | MCR_DTR | MCR_RTS*/
;
UART_IER
(
uart_dev
->
base
)
=
0
;
uint64_t
brtc
=
(
125000000U
)
/
(
16
*
(
cfg
->
baud_rate
));
UART_LCR
(
uart_dev
->
base
)
=
0x80
;
// Activate buadcfg
UART_LSB
(
uart_dev
->
base
)
=
brtc
&
0xff
;
UART_MSB
(
uart_dev
->
base
)
=
brtc
>>
8
;
if
(((((
short
)
UART_MSB
(
uart_dev
->
base
))
<<
8
)
|
UART_LSB
(
uart_dev
->
base
))
!=
brtc
)
ret
=
RT_ERROR
;
UART_LCR
(
uart_dev
->
base
)
=
CFCR_8BITS
;
// Back to normal
UART_MCR
(
uart_dev
->
base
)
=
MCR_IENABLE
/* | MCR_DTR | MCR_RTS*/
;
UART_IER
(
uart_dev
->
base
)
=
0
;
}
static
rt_err_t
ls2k_uart_configure
(
struct
rt_serial_device
*
serial
,
struct
serial_configure
*
cfg
)
{
...
...
@@ -64,9 +65,9 @@ static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct seri
RT_ASSERT
(
serial
!=
RT_NULL
);
RT_ASSERT
(
cfg
!=
RT_NULL
);
ls2k_uart_set_buad
(
serial
,
cfg
);
ls2k_uart_set_buad
(
serial
,
cfg
);
uart_dev
=
(
struct
rt_uart_ls2k
*
)
serial
->
parent
.
user_data
;
HWREG8
(
0xffffffffbfe10428
)
=
0x1f
;
// Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode.
HWREG8
(
0xffffffffbfe10428
)
=
0x1f
;
// Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode.
UART_IER
(
uart_dev
->
base
)
=
0
;
/* clear interrupt */
UART_FCR
(
uart_dev
->
base
)
=
0xc1
;
/* reset UART Rx/Tx */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
...
...
@@ -93,7 +94,7 @@ static rt_err_t ls2k_uart_control(struct rt_serial_device *serial, int cmd, void
case
RT_DEVICE_CTRL_SET_INT
:
/* Enable RX IRQ */
rt_hw_interrupt_umask
(
uart_dev
->
IRQ
);
UART_IER
(
uart_dev
->
base
)
|=
(
IER_IRxE
|
IER_ILE
);
UART_IER
(
uart_dev
->
base
)
|=
(
IER_IRxE
|
IER_ILE
);
break
;
default:
...
...
@@ -187,29 +188,29 @@ struct rt_uart_ls2k uart_dev0 =
struct
rt_uart_ls2k
uart_dev4
=
{
(
void
*
)
UARTx_BASE
(
4
),
LS2K_UART_4_5_6_7_IRQ
,
LS2K_UART_4_5_6_7_IRQ
,
};
struct
rt_serial_device
serial
,
serial4
;
struct
rt_serial_device
serial
,
serial4
;
void
rt_hw_uart_init
(
void
)
{
//UART0_1_ENABLE=0xff;
struct
rt_uart_ls2k
*
uart
,
*
uart4
;
struct
rt_uart_ls2k
*
uart
,
*
uart4
;
struct
serial_configure
config
=
RT_SERIAL_CONFIG_DEFAULT
;
uart
=
&
uart_dev0
;
uart4
=
&
uart_dev4
;
uart4
=
&
uart_dev4
;
serial
.
ops
=
&
ls2k_uart_ops
;
serial
.
config
=
config_uart0
;
serial4
.
ops
=
&
ls2k_uart_ops
;
serial4
.
config
=
config
;
serial4
.
ops
=
&
ls2k_uart_ops
;
serial4
.
config
=
config
;
rt_hw_interrupt_install
(
uart
->
IRQ
,
uart_irq_handler
,
&
serial
,
"UART0"
);
...
...
@@ -223,8 +224,8 @@ void rt_hw_uart_init(void)
rt_hw_serial_register
(
&
serial4
,
"uart4"
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
,
&
uart_dev4
);
}
/*@}*/
bsp/ls2kdev/drivers/interrupt.c
浏览文件 @
5d32b5d2
...
...
@@ -58,24 +58,24 @@ static void liointc_init(void)
//set irq mode
void
liointc_set_irq_mode
(
int
irq
,
int
mode
)
{
if
(
irq
<
32
)
if
(
irq
<
32
)
{
if
(
mode
==
PIN_IRQ_MODE_RISING
)
if
(
mode
==
PIN_IRQ_MODE_RISING
)
{
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x0
<<
(
irq
));
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x1
<<
(
irq
));
}
else
if
(
mode
==
PIN_IRQ_MODE_FALLING
)
else
if
(
mode
==
PIN_IRQ_MODE_FALLING
)
{
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x1
<<
(
irq
));
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x1
<<
(
irq
));
}
else
if
(
mode
==
PIN_IRQ_MODE_HIGH_LEVEL
)
else
if
(
mode
==
PIN_IRQ_MODE_HIGH_LEVEL
)
{
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x1
<<
(
irq
));
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x0
<<
(
irq
));
}
else
if
(
mode
==
PIN_IRQ_MODE_LOW_LEVEL
)
else
if
(
mode
==
PIN_IRQ_MODE_LOW_LEVEL
)
{
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x0
<<
(
irq
));
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x0
<<
(
irq
));
...
...
@@ -88,22 +88,22 @@ void liointc_set_irq_mode(int irq, int mode)
}
else
{
if
(
mode
==
PIN_IRQ_MODE_RISING
)
if
(
mode
==
PIN_IRQ_MODE_RISING
)
{
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x0
<<
(
irq
-
32
));
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x1
<<
(
irq
-
32
));
}
else
if
(
mode
==
PIN_IRQ_MODE_FALLING
)
else
if
(
mode
==
PIN_IRQ_MODE_FALLING
)
{
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x1
<<
(
irq
-
32
));
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x1
<<
(
irq
-
32
));
}
else
if
(
mode
==
PIN_IRQ_MODE_HIGH_LEVEL
)
else
if
(
mode
==
PIN_IRQ_MODE_HIGH_LEVEL
)
{
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x1
<<
(
irq
-
32
));
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x0
<<
(
irq
-
32
));
}
else
if
(
mode
==
PIN_IRQ_MODE_LOW_LEVEL
)
else
if
(
mode
==
PIN_IRQ_MODE_LOW_LEVEL
)
{
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_POL
)
|=
(
0x0
<<
(
irq
-
32
));
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_EDGE
)
|=
(
0x0
<<
(
irq
-
32
));
...
...
@@ -166,7 +166,7 @@ void rt_hw_interrupt_init(void)
}
rt_isr_handler_t
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
handler
,
void
*
param
,
const
char
*
name
)
void
*
param
,
const
char
*
name
)
{
rt_isr_handler_t
old_handler
=
RT_NULL
;
...
...
@@ -181,7 +181,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
irq_handle_table
[
vector
].
param
=
param
;
}
if
(
vector
<=
32
)
if
(
vector
<=
32
)
{
mips_unmask_cpu_irq
(
2
);
}
...
...
@@ -189,7 +189,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
{
mips_unmask_cpu_irq
(
3
);
}
return
old_handler
;
}
...
...
@@ -213,11 +213,11 @@ void rt_do_mips_cpu_irq(rt_uint32_t ip)
void
rt_hw_interrupt_umask
(
int
irq
)
{
if
(
irq
<
LIOINTC0_IRQBASE
+
32
)
if
(
irq
<
LIOINTC0_IRQBASE
+
32
)
{
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_ENABLE
)
=
(
1
<<
irq
);
}
else
if
(
irq
<
LIOINTC1_IRQBASE
+
32
)
else
if
(
irq
<
LIOINTC1_IRQBASE
+
32
)
{
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_ENABLE
)
=
(
1
<<
(
irq
-
32
));
}
...
...
@@ -225,11 +225,11 @@ void rt_hw_interrupt_umask(int irq)
void
rt_hw_interrupt_mask
(
int
irq
)
{
if
(
irq
<
LIOINTC0_IRQBASE
+
32
)
if
(
irq
<
LIOINTC0_IRQBASE
+
32
)
{
HWREG32
(
LIOINTC0_BASE
+
LIOINTC_REG_INTC_DISABLE
)
=
(
1
<<
irq
);
}
else
if
(
irq
<
LIOINTC1_IRQBASE
+
32
)
else
if
(
irq
<
LIOINTC1_IRQBASE
+
32
)
{
HWREG32
(
LIOINTC1_BASE
+
LIOINTC_REG_INTC_DISABLE
)
=
(
1
<<
(
irq
-
32
));
}
...
...
bsp/ls2kdev/drivers/net/mii.c
浏览文件 @
5d32b5d2
...
...
@@ -9,7 +9,7 @@
*/
#include "mii.h"
static
inline
unsigned
int
mii_nway_result
(
unsigned
int
negotiated
)
static
inline
unsigned
int
mii_nway_result
(
unsigned
int
negotiated
)
{
unsigned
int
ret
;
...
...
@@ -32,7 +32,8 @@ static int mii_check_gmii_support(struct mii_if_info *mii)
int
reg
;
reg
=
mii
->
mdio_read
(
mii
->
dev
,
mii
->
phy_id
,
MII_BMSR
);
if
(
reg
&
BMSR_ESTATEN
)
{
if
(
reg
&
BMSR_ESTATEN
)
{
reg
=
mii
->
mdio_read
(
mii
->
dev
,
mii
->
phy_id
,
MII_ESTATUS
);
if
(
reg
&
(
ESTATUS_1000_TFULL
|
ESTATUS_1000_THALF
))
return
1
;
...
...
@@ -43,7 +44,7 @@ static int mii_check_gmii_support(struct mii_if_info *mii)
static
int
mii_ethtool_gset
(
struct
mii_if_info
*
mii
,
struct
ethtool_cmd
*
ecmd
)
{
struct
synopGMACNetworkAdapter
*
dev
=
mii
->
dev
;
struct
synopGMACNetworkAdapter
*
dev
=
mii
->
dev
;
u32
advert
,
bmcr
,
lpa
,
nego
;
u32
advert2
=
0
,
bmcr2
=
0
,
lpa2
=
0
;
...
...
@@ -53,7 +54,7 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
SUPPORTED_Autoneg
|
SUPPORTED_TP
|
SUPPORTED_MII
);
if
(
mii
->
supports_gmii
)
ecmd
->
supported
|=
SUPPORTED_1000baseT_Half
|
SUPPORTED_1000baseT_Full
;
SUPPORTED_1000baseT_Full
;
/* only supports twisted-pair */
ecmd
->
port
=
PORT_MII
;
...
...
@@ -84,36 +85,43 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
bmcr
=
mii
->
mdio_read
(
dev
,
mii
->
phy_id
,
MII_BMCR
);
lpa
=
mii
->
mdio_read
(
dev
,
mii
->
phy_id
,
MII_LPA
);
if
(
mii
->
supports_gmii
)
{
if
(
mii
->
supports_gmii
)
{
bmcr2
=
mii
->
mdio_read
(
dev
,
mii
->
phy_id
,
MII_CTRL1000
);
lpa2
=
mii
->
mdio_read
(
dev
,
mii
->
phy_id
,
MII_STAT1000
);
}
if
(
bmcr
&
BMCR_ANENABLE
)
{
if
(
bmcr
&
BMCR_ANENABLE
)
{
ecmd
->
advertising
|=
ADVERTISED_Autoneg
;
ecmd
->
autoneg
=
AUTONEG_ENABLE
;
nego
=
mii_nway_result
(
advert
&
lpa
);
if
((
bmcr2
&
(
ADVERTISE_1000HALF
|
ADVERTISE_1000FULL
))
&
(
lpa2
>>
2
))
if
((
bmcr2
&
(
ADVERTISE_1000HALF
|
ADVERTISE_1000FULL
))
&
(
lpa2
>>
2
))
ecmd
->
speed
=
SPEED_1000
;
else
if
(
nego
==
LPA_100FULL
||
nego
==
LPA_100HALF
)
ecmd
->
speed
=
SPEED_100
;
else
ecmd
->
speed
=
SPEED_10
;
if
((
lpa2
&
LPA_1000FULL
)
||
nego
==
LPA_100FULL
||
nego
==
LPA_10FULL
)
{
nego
==
LPA_10FULL
)
{
ecmd
->
duplex
=
DUPLEX_FULL
;
mii
->
full_duplex
=
1
;
}
else
{
}
else
{
ecmd
->
duplex
=
DUPLEX_HALF
;
mii
->
full_duplex
=
0
;
}
}
else
{
}
else
{
ecmd
->
autoneg
=
AUTONEG_DISABLE
;
ecmd
->
speed
=
((
bmcr
&
BMCR_SPEED1000
&&
(
bmcr
&
BMCR_SPEED100
)
==
0
)
?
SPEED_1000
:
(
bmcr
&
BMCR_SPEED100
)
?
SPEED_100
:
SPEED_10
);
ecmd
->
speed
=
((
bmcr
&
BMCR_SPEED1000
&&
(
bmcr
&
BMCR_SPEED100
)
==
0
)
?
SPEED_1000
:
(
bmcr
&
BMCR_SPEED100
)
?
SPEED_100
:
SPEED_10
);
ecmd
->
duplex
=
(
bmcr
&
BMCR_FULLDPLX
)
?
DUPLEX_FULL
:
DUPLEX_HALF
;
}
...
...
@@ -122,7 +130,7 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
return
0
;
}
static
int
mii_link_ok
(
struct
mii_if_info
*
mii
)
static
int
mii_link_ok
(
struct
mii_if_info
*
mii
)
{
/* first, a dummy read, needed to latch some MII phys */
mii
->
mdio_read
(
mii
->
dev
,
mii
->
phy_id
,
MII_BMSR
);
...
...
bsp/ls2kdev/drivers/net/synopGMAC.c
浏览文件 @
5d32b5d2
...
...
@@ -119,7 +119,7 @@ s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice *gmacdev, u32 no_of_desc, u32
gmacdev
->
TxDescCount
=
0
;
first_desc
=
(
DmaDesc
*
)
plat_alloc_consistent_dmaable_memory
(
gmacdev
,
sizeof
(
DmaDesc
)
*
(
no_of_desc
),
&
dma_addr
);
if
(
first_desc
==
NULL
)
{
rt_kprintf
(
"Error in Tx Descriptors memory allocation
\n
"
);
...
...
@@ -300,7 +300,7 @@ static rt_err_t eth_init(rt_device_t device)
{
struct
eth_device
*
eth_device
=
(
struct
eth_device
*
)
device
;
RT_ASSERT
(
eth_device
!=
RT_NULL
);
s32
ijk
;
s32
status
=
0
;
u64
dma_addr
;
...
...
@@ -490,7 +490,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
dma_addr
=
plat_dma_map_single
(
gmacdev
,
(
void
*
)
pbuf
,
p
->
tot_len
);
status
=
synopGMAC_set_tx_qptr
(
gmacdev
,
dma_addr
,
p
->
tot_len
,
pbuf
,
0
,
0
,
0
,
offload_needed
,
&
index
,
dpr
);
if
(
status
<
0
)
{
rt_kprintf
(
"%s No More Free Tx Descriptors
\n
"
,
__FUNCTION__
);
...
...
@@ -501,7 +501,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
}
synopGMAC_resume_dma_tx
(
gmacdev
);
s32
desc_index
;
u64
data1
,
data2
;
...
...
@@ -598,48 +598,48 @@ struct pbuf *rt_eth_rx(rt_device_t device)
}
/*Handle the Receive Descriptors*/
desc_index
=
synopGMAC_get_rx_qptr
(
gmacdev
,
&
status
,
&
dma_addr1
,
NULL
,
&
data1
,
&
dma_addr2
,
NULL
,
&
data2
);
desc_index
=
synopGMAC_get_rx_qptr
(
gmacdev
,
&
status
,
&
dma_addr1
,
NULL
,
&
data1
,
&
dma_addr2
,
NULL
,
&
data2
);
if
(((
u32
)
desc_index
>=
RECEIVE_DESC_SIZE
)
&&
(
desc_index
!=
-
1
))
{
rt_kprintf
(
"host receive descriptor address pointer = 0x%08x
\n
"
,
synopGMACReadReg
(
gmacdev
->
DmaBase
,
DmaRxCurrDesc
));
rt_kprintf
(
"host receive buffer = 0x%08x
\n
"
,
synopGMACReadReg
(
gmacdev
->
DmaBase
,
DmaRxCurrAddr
));
rt_kprintf
(
"desc_index error!!!!,tick = %d
\n
"
,
rt_tick_get
());
while
(
1
);
}
if
(((
u32
)
desc_index
>=
RECEIVE_DESC_SIZE
)
&&
(
desc_index
!=
-
1
))
if
(
desc_index
>=
0
&&
data1
!=
0
)
{
DEBUG_MES
(
"Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x
\n
"
,
desc_index
,
dma_addr1
,
status
);
if
(
synopGMAC_is_rx_desc_valid
(
status
)
||
SYNOP_PHY_LOOPBACK
)
{
rt_kprintf
(
"host receive descriptor address pointer = 0x%08x
\n
"
,
synopGMACReadReg
(
gmacdev
->
DmaBase
,
DmaRxCurrDesc
));
rt_kprintf
(
"host receive buffer = 0x%08x
\n
"
,
synopGMACReadReg
(
gmacdev
->
DmaBase
,
DmaRxCurrAddr
));
rt_kprintf
(
"desc_index error!!!!,tick = %d
\n
"
,
rt_tick_get
());
while
(
1
);
dma_addr1
=
plat_dma_map_single
(
gmacdev
,
(
void
*
)
data1
,
RX_BUF_SIZE
);
len
=
synopGMAC_get_rx_desc_frame_length
(
status
)
-
4
;
//Not interested in Ethernet CRC bytes
pbuf
=
pbuf_alloc
(
PBUF_LINK
,
len
,
PBUF_RAM
);
if
(
pbuf
==
0
)
rt_kprintf
(
"===error in pbuf_alloc
\n
"
);
rt_memcpy
(
pbuf
->
payload
,
(
char
*
)
data1
,
len
);
DEBUG_MES
(
"==get pkg len: %d
\n
"
,
len
);
}
if
(
desc_index
>=
0
&&
data1
!=
0
)
else
{
rt_kprintf
(
"s: %08x
\n
"
,
status
);
adapter
->
synopGMACNetStats
.
rx_errors
++
;
adapter
->
synopGMACNetStats
.
collisions
+=
synopGMAC_is_rx_frame_collision
(
status
);
adapter
->
synopGMACNetStats
.
rx_crc_errors
+=
synopGMAC_is_rx_crc
(
status
);
adapter
->
synopGMACNetStats
.
rx_frame_errors
+=
synopGMAC_is_frame_dribbling_errors
(
status
);
adapter
->
synopGMACNetStats
.
rx_length_errors
+=
synopGMAC_is_rx_frame_length_errors
(
status
);
}
desc_index
=
synopGMAC_set_rx_qptr
(
gmacdev
,
dma_addr1
,
RX_BUF_SIZE
,
(
u64
)
data1
,
0
,
0
,
0
);
if
(
desc_index
<
0
)
{
DEBUG_MES
(
"Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x
\n
"
,
desc_index
,
dma_addr1
,
status
);
if
(
synopGMAC_is_rx_desc_valid
(
status
)
||
SYNOP_PHY_LOOPBACK
)
{
dma_addr1
=
plat_dma_map_single
(
gmacdev
,
(
void
*
)
data1
,
RX_BUF_SIZE
);
len
=
synopGMAC_get_rx_desc_frame_length
(
status
)
-
4
;
//Not interested in Ethernet CRC bytes
pbuf
=
pbuf_alloc
(
PBUF_LINK
,
len
,
PBUF_RAM
);
if
(
pbuf
==
0
)
rt_kprintf
(
"===error in pbuf_alloc
\n
"
);
rt_memcpy
(
pbuf
->
payload
,
(
char
*
)
data1
,
len
);
DEBUG_MES
(
"==get pkg len: %d
\n
"
,
len
);
}
else
{
rt_kprintf
(
"s: %08x
\n
"
,
status
);
adapter
->
synopGMACNetStats
.
rx_errors
++
;
adapter
->
synopGMACNetStats
.
collisions
+=
synopGMAC_is_rx_frame_collision
(
status
);
adapter
->
synopGMACNetStats
.
rx_crc_errors
+=
synopGMAC_is_rx_crc
(
status
);
adapter
->
synopGMACNetStats
.
rx_frame_errors
+=
synopGMAC_is_frame_dribbling_errors
(
status
);
adapter
->
synopGMACNetStats
.
rx_length_errors
+=
synopGMAC_is_rx_frame_length_errors
(
status
);
}
desc_index
=
synopGMAC_set_rx_qptr
(
gmacdev
,
dma_addr1
,
RX_BUF_SIZE
,
(
u64
)
data1
,
0
,
0
,
0
);
if
(
desc_index
<
0
)
{
#if SYNOP_RX_DEBUG
rt_kprintf
(
"Cannot set Rx Descriptor for data1 %08x
\n
"
,
(
u32
)
data1
);
rt_kprintf
(
"Cannot set Rx Descriptor for data1 %08x
\n
"
,
(
u32
)
data1
);
#endif
plat_free_memory
((
void
*
)
data1
);
}
plat_free_memory
((
void
*
)
data1
);
}
}
rt_sem_release
(
&
sem_lock
);
DEBUG_MES
(
"%s : before return
\n
"
,
__FUNCTION__
);
return
pbuf
;
...
...
@@ -930,7 +930,7 @@ int rt_hw_eth_init(void)
rt_kprintf
(
"Error in Memory Allocataion, Founction : %s
\n
"
,
__FUNCTION__
);
}
memset
((
char
*
)
synopGMACadapter
,
0
,
sizeof
(
struct
synopGMACNetworkAdapter
));
synopGMACadapter
->
synopGMACdev
=
NULL
;
synopGMACadapter
->
synopGMACdev
=
(
synopGMACdevice
*
)
plat_alloc_memory
(
sizeof
(
synopGMACdevice
));
...
...
@@ -940,13 +940,13 @@ int rt_hw_eth_init(void)
}
memset
((
char
*
)
synopGMACadapter
->
synopGMACdev
,
0
,
sizeof
(
synopGMACdevice
));
/*
* Attach the device to MAC struct This will configure all the required base addresses
* such as Mac base, configuration base, phy base address(out of 32 possible phys)
* */
synopGMAC_attach
(
synopGMACadapter
->
synopGMACdev
,
(
gmac_base
+
MACBASE
),
gmac_base
+
DMABASE
,
DEFAULT_PHY_BASE
,
mac_addr0
);
init_phy
(
synopGMACadapter
->
synopGMACdev
);
synopGMAC_reset
(
synopGMACadapter
->
synopGMACdev
);
...
...
@@ -980,7 +980,7 @@ int rt_hw_eth_init(void)
eth_dev
.
parent
.
eth_tx
=
rt_eth_tx
;
eth_dev
.
parent
.
eth_rx
=
rt_eth_rx
;
eth_device_init
(
&
(
eth_dev
.
parent
),
"e0"
);
eth_device_linkchange
(
&
eth_dev
.
parent
,
RT_TRUE
);
//linkup the e0 for lwip to check
return
0
;
...
...
bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
浏览文件 @
5d32b5d2
此差异已折叠。
点击以展开。
bsp/ls2kdev/drivers/net/synopGMAC_plat.c
浏览文件 @
5d32b5d2
...
...
@@ -33,49 +33,52 @@ void flush_cache(unsigned long start_addr, unsigned long size)
}
//convert virtual address to physical address
dma_addr_t
__attribute__
((
weak
))
gmac_dmamap
(
unsigned
long
va
,
u32
size
)
dma_addr_t
__attribute__
((
weak
))
gmac_dmamap
(
unsigned
long
va
,
u32
size
)
{
return
VA_TO_PA
(
va
);
return
VA_TO_PA
(
va
);
//return UNCACHED_TO_PHYS(va);
}
/**
* This is a wrapper function for Memory allocation routine. In linux Kernel
* This is a wrapper function for Memory allocation routine. In linux Kernel
* it it kmalloc function
* @param[in] bytes in bytes to allocate
*/
void
*
plat_alloc_memory
(
u32
bytes
)
void
*
plat_alloc_memory
(
u32
bytes
)
{
//return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT);
void
*
buf
=
(
void
*
)
rt_malloc
((
u32
)
bytes
);
void
*
buf
=
(
void
*
)
rt_malloc
((
u32
)
bytes
);
flush_cache
((
unsigned
long
)
buf
,
bytes
);
return
buf
;
}
/**
* This is a wrapper function for consistent dma-able Memory allocation routine.
* This is a wrapper function for consistent dma-able Memory allocation routine.
* In linux Kernel, it depends on pci dev structure
* @param[in] bytes in bytes to allocate
*/
//allocate a space aligned to 16-byte boundary without cache
void
*
plat_alloc_consistent_dmaable_memory
(
synopGMACdevice
*
pcidev
,
u32
size
,
u32
*
addr
)
void
*
plat_alloc_consistent_dmaable_memory
(
synopGMACdevice
*
pcidev
,
u32
size
,
u32
*
addr
)
{
void
*
buf
;
buf
=
(
void
*
)
rt_malloc
((
u32
)(
size
+
16
));
buf
=
(
void
*
)
rt_malloc
((
u32
)(
size
+
16
));
//CPU_IOFlushDCache( buf,size, SYNC_W);
unsigned
long
i
=
(
unsigned
long
)
buf
;
// rt_kprintf("size = %d\n", size);
// rt_kprintf("bufaddr = %p\n", buf);
// rt_kprintf("i%%16 == %d\n", i%16);
if
(
i
%
16
==
8
){
if
(
i
%
16
==
8
)
{
i
+=
8
;
}
else
if
(
i
%
16
==
4
){
else
if
(
i
%
16
==
4
)
{
i
+=
12
;
}
else
if
(
i
%
16
==
12
){
else
if
(
i
%
16
==
12
)
{
i
+=
4
;
}
...
...
@@ -91,26 +94,26 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3
* In linux Kernel, it depends on pci dev structure
* @param[in] bytes in bytes to allocate
*/
//void plat_free_consistent_dmaable_memory(void * addr)
void
plat_free_consistent_dmaable_memory
(
synopGMACdevice
*
pcidev
,
u32
size
,
void
*
addr
,
u64
dma_addr
)
//void plat_free_consistent_dmaable_memory(void * addr)
void
plat_free_consistent_dmaable_memory
(
synopGMACdevice
*
pcidev
,
u32
size
,
void
*
addr
,
u64
dma_addr
)
{
rt_free
((
void
*
)
PHYS_TO_CACHED
(
UNCACHED_TO_PHYS
(
addr
)));
rt_free
((
void
*
)
PHYS_TO_CACHED
(
UNCACHED_TO_PHYS
(
addr
)));
return
;
}
/**
* This is a wrapper function for Memory free routine. In linux Kernel
* This is a wrapper function for Memory free routine. In linux Kernel
* it it kfree function
* @param[in] buffer pointer to be freed
*/
void
plat_free_memory
(
void
*
buffer
)
void
plat_free_memory
(
void
*
buffer
)
{
rt_free
(
buffer
);
return
;
}
//convert virtual address to physical address and flush cache
dma_addr_t
plat_dma_map_single
(
void
*
hwdev
,
void
*
ptr
,
u32
size
)
dma_addr_t
plat_dma_map_single
(
void
*
hwdev
,
void
*
ptr
,
u32
size
)
{
unsigned
long
addr
=
(
unsigned
long
)
ptr
;
//CPU_IOFlushDCache(addr,size, direction);
...
...
@@ -119,8 +122,8 @@ dma_addr_t plat_dma_map_single(void *hwdev,void *ptr,u32 size)
}
/**
* This is a wrapper function for platform dependent delay
* Take care while passing the argument to this function
* This is a wrapper function for platform dependent delay
* Take care while passing the argument to this function
* @param[in] buffer pointer to be freed
*/
void
plat_delay
(
u32
delay
)
...
...
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