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体验新版 GitCode,发现更多精彩内容 >>
提交
3b07c8d5
编写于
10月 12, 2020
作者:
W
WangQiang
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
修改了imxrt1052-nxp-evk的BSP的以太网相关配置,用于适配PHY模型
上级
502378cf
变更
7
隐藏空白更改
内联
并排
Showing
7 changed file
with
175 addition
and
546 deletion
+175
-546
bsp/imxrt/imxrt1052-nxp-evk/.config
bsp/imxrt/imxrt1052-nxp-evk/.config
+86
-14
bsp/imxrt/imxrt1052-nxp-evk/SConstruct
bsp/imxrt/imxrt1052-nxp-evk/SConstruct
+3
-0
bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig
bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig
+29
-7
bsp/imxrt/imxrt1052-nxp-evk/board/SConscript
bsp/imxrt/imxrt1052-nxp-evk/board/SConscript
+0
-4
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c
+0
-315
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h
+0
-200
bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h
bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h
+57
-6
未找到文件。
bsp/imxrt/imxrt1052-nxp-evk/.config
浏览文件 @
3b07c8d5
...
...
@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX
=
8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE
=
4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
...
...
@@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE
=
y
CONFIG_RT_CONSOLEBUF_SIZE
=
128
CONFIG_RT_CONSOLE_DEVICE_NAME
=
"uart1"
CONFIG_RT_VER_NUM
=
0
x40001
CONFIG_RT_VER_NUM
=
0
x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
...
...
@@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
#
CONFIG_RT_USING_DEVICE_IPC
=
y
CONFIG_RT_PIPE_BUFSZ
=
512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL
=
y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ
=
64
...
...
@@ -115,12 +118,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_CPUTIME
=
y
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PHY
=
y
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
...
...
@@ -128,10 +132,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
#
Using WiFi
#
# CONFIG_RT_USING_TOUCH is not set
#
CONFIG_RT_USING_HWCRYPTO is not set
#
CONFIG_RT_USING_PULSE_ENCODER is not set
#
CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
...
...
@@ -145,6 +149,7 @@ CONFIG_RT_USING_PIN=y
#
CONFIG_RT_USING_LIBC
=
y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
...
...
@@ -156,19 +161,79 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_SAL is not set
#
#
light weight TCP/IP stack
#
Network interface device
#
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_NETDEV
=
y
CONFIG_NETDEV_USING_IFCONFIG
=
y
CONFIG_NETDEV_USING_PING
=
y
CONFIG_NETDEV_USING_NETSTAT
=
y
CONFIG_NETDEV_USING_AUTO_DEFAULT
=
y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4
=
1
CONFIG_NETDEV_IPV6
=
0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
#
Modbus master and slave
stack
#
light weight TCP/IP
stack
#
# CONFIG_RT_USING_MODBUS is not set
CONFIG_RT_USING_LWIP
=
y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202
=
y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT
=
4
CONFIG_RT_LWIP_IGMP
=
y
CONFIG_RT_LWIP_ICMP
=
y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS
=
y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR
=
"192.168.1.200"
CONFIG_RT_LWIP_GWADDR
=
"192.168.1.1"
CONFIG_RT_LWIP_MSKADDR
=
"255.255.255.0"
CONFIG_RT_LWIP_UDP
=
y
CONFIG_RT_LWIP_TCP
=
y
CONFIG_RT_LWIP_RAW
=
y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN
=
8
CONFIG_RT_LWIP_PBUF_NUM
=
16
CONFIG_RT_LWIP_RAW_PCB_NUM
=
4
CONFIG_RT_LWIP_UDP_PCB_NUM
=
4
CONFIG_RT_LWIP_TCP_PCB_NUM
=
4
CONFIG_RT_LWIP_TCP_SEG_NUM
=
40
CONFIG_RT_LWIP_TCP_SND_BUF
=
8196
CONFIG_RT_LWIP_TCP_WND
=
8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY
=
10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE
=
8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE
=
1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY
=
12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE
=
1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE
=
8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK
=
1
CONFIG_LWIP_NETIF_LINK_CALLBACK
=
1
CONFIG_SO_REUSE
=
1
CONFIG_LWIP_SO_RCVTIMEO
=
1
CONFIG_LWIP_SO_SNDTIMEO
=
1
CONFIG_LWIP_SO_RCVBUF
=
1
CONFIG_LWIP_SO_LINGER
=
0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK
=
0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING
=
y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
...
...
@@ -178,7 +243,6 @@ CONFIG_RT_USING_LIBC=y
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
...
...
@@ -230,13 +294,12 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT
HUB
is not set
# CONFIG_PKG_USING_TENCENT_IOT
KIT
is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
#
# security packages
...
...
@@ -294,6 +357,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
...
...
@@ -310,7 +374,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
#
# miscellaneous packages
...
...
@@ -354,10 +417,19 @@ CONFIG_BSP_USING_LPUART=y
CONFIG_BSP_USING_LPUART1
=
y
# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_LPUART3 is not set
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDRAM is not set
CONFIG_BSP_USING_ETH
=
y
CONFIG_BSP_USING_PHY
=
y
CONFIG_PHY_DEVICE_ADDRESS
=
2
CONFIG_PHY_USING_KSZ8081
=
y
CONFIG_PHY_RESET_PORT
=
1
CONFIG_PHY_RESET_PIN
=
9
CONFIG_FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
=
y
#
# Board extended module Drivers
...
...
bsp/imxrt/imxrt1052-nxp-evk/SConstruct
浏览文件 @
3b07c8d5
...
...
@@ -67,5 +67,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons
# include drivers
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
'drivers'
,
'SConscript'
)))
# include peripherals
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
'peripherals'
,
'SConscript'
)))
# make a building
DoBuilding
(
TARGET
,
objs
)
bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig
浏览文件 @
3b07c8d5
...
...
@@ -96,19 +96,41 @@ menu "Onboard Peripheral Drivers"
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select PHY_USING_KSZ8081
select RT_USING_NETDEV
default n
if BSP_USING_ETH
config PHY_USING_KSZ8081
bool "i.MX RT1050EVKB uses ksz8081 phy"
config BSP_USING_PHY
select RT_USING_PHY
bool "Enable ethernet phy"
default y
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
if BSP_USING_PHY
config PHY_DEVICE_ADDRESS
int "Specify address of phy device"
default 2
config PHY_USING_KSZ8081
bool "i.MX RT1064EVK uses ksz8081 phy"
default y
if PHY_USING_KSZ8081
config PHY_RESET_PORT
int "indicate port of reset"
default 1
config PHY_RESET_PIN
int "indicate pin of reset"
default 9
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
endif
endif
endif
endmenu
...
...
bsp/imxrt/imxrt1052-nxp-evk/board/SConscript
浏览文件 @
3b07c8d5
...
...
@@ -12,10 +12,6 @@ MCUX_Config/pin_mux.c
CPPPATH
=
[
cwd
,
cwd
+
'/MCUX_Config'
,
cwd
+
'/ports'
]
CPPDEFINES
=
[
'CPU_MIMXRT1052DVL6B'
,
'SKIP_SYSCLK_INIT'
,
'EVK_MCIMXRM'
,
'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1'
,
'XIP_EXTERNAL_FLASH=1'
]
if
GetDepend
([
'PHY_USING_KSZ8081'
]):
src
+=
Glob
(
'ports/phyksz8081/fsl_phy.c'
)
CPPPATH
+=
[
cwd
+
'/ports/phyksz8081'
]
group
=
DefineGroup
(
'Drivers'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
,
CPPDEFINES
=
CPPDEFINES
)
Return
(
'group'
)
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c
已删除
100644 → 0
浏览文件 @
502378cf
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_phy.h"
#include <rtthread.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern
uint32_t
ENET_GetInstance
(
ENET_Type
*
base
);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern
clock_ip_name_t
s_enetClock
[
FSL_FEATURE_SOC_ENET_COUNT
];
#endif
/* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
status_t
PHY_Init
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
srcClock_Hz
)
{
uint32_t
bssReg
;
uint32_t
counter
=
PHY_TIMEOUT_COUNT
;
uint32_t
idReg
=
0
;
status_t
result
=
kStatus_Success
;
uint32_t
instance
=
ENET_GetInstance
(
base
);
uint32_t
timeDelay
;
uint32_t
ctlReg
=
0
;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock
(
s_enetClock
[
instance
]);
#endif
/* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI
(
base
,
srcClock_Hz
,
false
);
/* Initialization after PHY stars to work. */
while
((
idReg
!=
PHY_CONTROL_ID1
)
&&
(
counter
!=
0
))
{
PHY_Read
(
base
,
phyAddr
,
PHY_ID1_REG
,
&
idReg
);
counter
--
;
}
if
(
!
counter
)
{
return
kStatus_Fail
;
}
/* Reset PHY. */
counter
=
PHY_TIMEOUT_COUNT
;
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
PHY_BCTL_RESET_MASK
);
if
(
result
==
kStatus_Success
)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
uint32_t
data
=
0
;
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
&
data
);
if
(
result
!=
kStatus_Success
)
{
return
result
;
}
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
(
data
|
PHY_CTL2_REFCLK_SELECT_MASK
));
if
(
result
!=
kStatus_Success
)
{
return
result
;
}
#endif
/* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
/* Set the negotiation. */
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_AUTONEG_ADVERTISE_REG
,
(
PHY_100BASETX_FULLDUPLEX_MASK
|
PHY_100BASETX_HALFDUPLEX_MASK
|
PHY_10BASETX_FULLDUPLEX_MASK
|
PHY_10BASETX_HALFDUPLEX_MASK
|
0x1U
));
if
(
result
==
kStatus_Success
)
{
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
(
PHY_BCTL_AUTONEG_MASK
|
PHY_BCTL_RESTART_AUTONEG_MASK
));
if
(
result
==
kStatus_Success
)
{
/* Check auto negotiation complete. */
while
(
counter
--
)
{
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_BASICSTATUS_REG
,
&
bssReg
);
if
(
result
==
kStatus_Success
)
{
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL1_REG
,
&
ctlReg
);
if
(((
bssReg
&
PHY_BSTATUS_AUTONEGCOMP_MASK
)
!=
0
)
&&
(
ctlReg
&
PHY_LINK_READY_MASK
))
{
/* Wait a moment for Phy status stable. */
for
(
timeDelay
=
0
;
timeDelay
<
PHY_TIMEOUT_COUNT
;
timeDelay
++
)
{
__ASM
(
"nop"
);
}
break
;
}
}
if
(
!
counter
)
{
return
kStatus_PHY_AutoNegotiateFail
;
}
}
}
}
}
return
result
;
}
status_t
PHY_Write
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
data
)
{
uint32_t
counter
;
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
/* Starts a SMI write command. */
ENET_StartSMIWrite
(
base
,
phyAddr
,
phyReg
,
kENET_MiiWriteValidFrame
,
data
);
/* Wait for SMI complete. */
for
(
counter
=
PHY_TIMEOUT_COUNT
;
counter
>
0
;
counter
--
)
{
if
(
ENET_GetInterruptStatus
(
base
)
&
ENET_EIR_MII_MASK
)
{
break
;
}
}
/* Check for timeout. */
if
(
!
counter
)
{
return
kStatus_PHY_SMIVisitTimeout
;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
return
kStatus_Success
;
}
status_t
PHY_Read
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
*
dataPtr
)
{
assert
(
dataPtr
);
uint32_t
counter
;
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
/* Starts a SMI read command operation. */
ENET_StartSMIRead
(
base
,
phyAddr
,
phyReg
,
kENET_MiiReadValidFrame
);
/* Wait for MII complete. */
for
(
counter
=
PHY_TIMEOUT_COUNT
;
counter
>
0
;
counter
--
)
{
if
(
ENET_GetInterruptStatus
(
base
)
&
ENET_EIR_MII_MASK
)
{
break
;
}
}
/* Check for timeout. */
if
(
!
counter
)
{
return
kStatus_PHY_SMIVisitTimeout
;
}
/* Get data from MII register. */
*
dataPtr
=
ENET_ReadSMIData
(
base
);
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
return
kStatus_Success
;
}
status_t
PHY_EnableLoopback
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_loop_t
mode
,
phy_speed_t
speed
,
bool
enable
)
{
status_t
result
;
uint32_t
data
=
0
;
/* Set the loop mode. */
if
(
enable
)
{
if
(
mode
==
kPHY_LocalLoop
)
{
if
(
speed
==
kPHY_Speed100M
)
{
data
=
PHY_BCTL_SPEED_100M_MASK
|
PHY_BCTL_DUPLEX_MASK
|
PHY_BCTL_LOOP_MASK
;
}
else
{
data
=
PHY_BCTL_DUPLEX_MASK
|
PHY_BCTL_LOOP_MASK
;
}
return
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
data
);
}
else
{
/* First read the current status in control register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
return
PHY_Write
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
(
data
|
PHY_CTL2_REMOTELOOP_MASK
));
}
}
}
else
{
/* Disable the loop mode. */
if
(
mode
==
kPHY_LocalLoop
)
{
/* First read the current status in control register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
data
&=
~
PHY_BCTL_LOOP_MASK
;
return
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
(
data
|
PHY_BCTL_RESTART_AUTONEG_MASK
));
}
}
else
{
/* First read the current status in control one register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
return
PHY_Write
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
(
data
&
~
PHY_CTL2_REMOTELOOP_MASK
));
}
}
}
return
result
;
}
status_t
PHY_GetLinkStatus
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
bool
*
status
)
{
assert
(
status
);
status_t
result
=
kStatus_Success
;
uint32_t
data
;
/* Read the basic status register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_BASICSTATUS_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
if
(
!
(
PHY_BSTATUS_LINKSTATUS_MASK
&
data
))
{
/* link down. */
*
status
=
false
;
}
else
{
/* link up. */
*
status
=
true
;
}
}
return
result
;
}
status_t
PHY_GetLinkSpeedDuplex
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_speed_t
*
speed
,
phy_duplex_t
*
duplex
)
{
assert
(
duplex
);
status_t
result
=
kStatus_Success
;
uint32_t
data
,
ctlReg
;
/* Read the control two register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL1_REG
,
&
ctlReg
);
if
(
result
==
kStatus_Success
)
{
data
=
ctlReg
&
PHY_CTL1_SPEEDUPLX_MASK
;
if
((
PHY_CTL1_10FULLDUPLEX_MASK
==
data
)
||
(
PHY_CTL1_100FULLDUPLEX_MASK
==
data
))
{
/* Full duplex. */
*
duplex
=
kPHY_FullDuplex
;
}
else
{
/* Half duplex. */
*
duplex
=
kPHY_HalfDuplex
;
}
data
=
ctlReg
&
PHY_CTL1_SPEEDUPLX_MASK
;
if
((
PHY_CTL1_100HALFDUPLEX_MASK
==
data
)
||
(
PHY_CTL1_100FULLDUPLEX_MASK
==
data
))
{
/* 100M speed. */
*
speed
=
kPHY_Speed100M
;
}
else
{
/* 10M speed. */
*
speed
=
kPHY_Speed10M
;
}
}
return
result
;
}
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h
已删除
100644 → 0
浏览文件 @
502378cf
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_enet.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*!< Version 2.0.0. */
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U
/*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U
/*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U
/*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U
/*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
/*!< The PHY auto-negotiate advertise register. */
#define PHY_CONTROL1_REG 0x1EU
/*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU
/*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x22U
/*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U
/*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U
/*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U
/*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U
/*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U
/*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U
/*!< The PHY reset bit mask. */
#define PHY_BCTL_SPEED_100M_MASK 0x2000U
/*!< The PHY 100M speed mask. */
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U
/*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U
/*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U
/*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U
/*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U
/*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U
/*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U
/*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U
/*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U
/*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U
/*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U
/*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U
/*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_100BaseT4_ABILITY_MASK 0x200U
/*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U
/*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U
/*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U
/*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U
/*!< The PHY has the 10M full duplex ability.*/
/*! @brief Defines the PHY status. */
enum
_phy_status
{
kStatus_PHY_SMIVisitTimeout
=
MAKE_STATUS
(
kStatusGroup_PHY
,
1
),
/*!< ENET PHY SMI visit timeout. */
kStatus_PHY_AutoNegotiateFail
=
MAKE_STATUS
(
kStatusGroup_PHY
,
2
)
/*!< ENET PHY AutoNegotiate Fail. */
};
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
typedef
enum
_phy_speed
{
kPHY_Speed10M
=
0U
,
/*!< ENET PHY 10M speed. */
kPHY_Speed100M
/*!< ENET PHY 100M speed. */
}
phy_speed_t
;
/*! @brief Defines the PHY link duplex. */
typedef
enum
_phy_duplex
{
kPHY_HalfDuplex
=
0U
,
/*!< ENET PHY half duplex. */
kPHY_FullDuplex
/*!< ENET PHY full duplex. */
}
phy_duplex_t
;
/*! @brief Defines the PHY loopback mode. */
typedef
enum
_phy_loop
{
kPHY_LocalLoop
=
0U
,
/*!< ENET PHY local loopback. */
kPHY_RemoteLoop
/*!< ENET PHY remote loopback. */
}
phy_loop_t
;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern
"C"
{
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t
PHY_Init
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
srcClock_Hz
);
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_Write
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
data
);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_Read
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
*
dataPtr
);
/*!
* @brief Enables/disables PHY loopback.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* the two loopback mode should not be both set. when one loopback mode is set
* the other one should be disabled.
* @param speed PHY speed for loopback mode.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY loopback success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_EnableLoopback
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_loop_t
mode
,
phy_speed_t
speed
,
bool
enable
);
/*!
* @brief Gets the PHY link status.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_GetLinkStatus
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
bool
*
status
);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_GetLinkSpeedDuplex
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_speed_t
*
speed
,
phy_duplex_t
*
duplex
);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif
/* _FSL_PHY_H_ */
bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h
浏览文件 @
3b07c8d5
...
...
@@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x4000
1
#define RT_VER_NUM 0x4000
3
/* RT-Thread Components */
...
...
@@ -78,11 +78,9 @@
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CPUTIME
#define RT_USING_PHY
#define RT_USING_PIN
/* Using WiFi */
/* Using USB */
...
...
@@ -95,11 +93,56 @@
/* Socket abstraction layer */
/*
light weight TCP/IP stack
*/
/*
Network interface device
*/
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/*
Modbus master and slave
stack */
/*
light weight TCP/IP
stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.200"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* AT commands */
...
...
@@ -163,6 +206,14 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_ETH
#define BSP_USING_PHY
#define PHY_DEVICE_ADDRESS 2
#define PHY_USING_KSZ8081
#define PHY_RESET_PORT 1
#define PHY_RESET_PIN 9
#define FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
/* Board extended module Drivers */
...
...
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