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体验新版 GitCode,发现更多精彩内容 >>
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864ae989
编写于
12月 26, 2018
作者:
S
SummerGift
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[bsp][stm32] add stm32f767-atk-apollo bsp
上级
04a16870
变更
41
展开全部
隐藏空白更改
内联
并排
Showing
41 changed file
with
13018 addition
and
79 deletion
+13018
-79
bsp/stm32/stm32f767-atk-apollo/.config
bsp/stm32/stm32f767-atk-apollo/.config
+364
-0
bsp/stm32/stm32f767-atk-apollo/.gitignore
bsp/stm32/stm32f767-atk-apollo/.gitignore
+42
-0
bsp/stm32/stm32f767-atk-apollo/Kconfig
bsp/stm32/stm32f767-atk-apollo/Kconfig
+21
-0
bsp/stm32/stm32f767-atk-apollo/README.md
bsp/stm32/stm32f767-atk-apollo/README.md
+130
-0
bsp/stm32/stm32f767-atk-apollo/SConscript
bsp/stm32/stm32f767-atk-apollo/SConscript
+14
-0
bsp/stm32/stm32f767-atk-apollo/SConstruct
bsp/stm32/stm32f767-atk-apollo/SConstruct
+58
-0
bsp/stm32/stm32f767-atk-apollo/applications/SConscript
bsp/stm32/stm32f767-atk-apollo/applications/SConscript
+12
-0
bsp/stm32/stm32f767-atk-apollo/applications/main.c
bsp/stm32/stm32f767-atk-apollo/applications/main.c
+33
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject
...stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject
+13
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc
...tm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc
+412
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/main.h
...stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/main.h
+91
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h
...7-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h
+458
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h
...m32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h
+84
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c
...stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c
+607
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
...67-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
+797
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c
...m32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c
+217
-0
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/system_stm32f7xx.c
...767-atk-apollo/board/CubeMX_Config/Src/system_stm32f7xx.c
+278
-0
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
+155
-0
bsp/stm32/stm32f767-atk-apollo/board/SConscript
bsp/stm32/stm32f767-atk-apollo/board/SConscript
+40
-0
bsp/stm32/stm32f767-atk-apollo/board/board.c
bsp/stm32/stm32f767-atk-apollo/board/board.c
+68
-0
bsp/stm32/stm32f767-atk-apollo/board/board.h
bsp/stm32/stm32f767-atk-apollo/board/board.h
+41
-0
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf
+28
-0
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds
+144
-0
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.sct
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.sct
+15
-0
bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
+77
-0
bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
+34
-0
bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
+58
-0
bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
+65
-0
bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
+65
-0
bsp/stm32/stm32f767-atk-apollo/figures/board.jpg
bsp/stm32/stm32f767-atk-apollo/figures/board.jpg
+0
-0
bsp/stm32/stm32f767-atk-apollo/project.ewp
bsp/stm32/stm32f767-atk-apollo/project.ewp
+2509
-0
bsp/stm32/stm32f767-atk-apollo/project.eww
bsp/stm32/stm32f767-atk-apollo/project.eww
+10
-0
bsp/stm32/stm32f767-atk-apollo/project.uvoptx
bsp/stm32/stm32f767-atk-apollo/project.uvoptx
+1768
-0
bsp/stm32/stm32f767-atk-apollo/project.uvprojx
bsp/stm32/stm32f767-atk-apollo/project.uvprojx
+1061
-0
bsp/stm32/stm32f767-atk-apollo/rtconfig.h
bsp/stm32/stm32f767-atk-apollo/rtconfig.h
+173
-0
bsp/stm32/stm32f767-atk-apollo/rtconfig.py
bsp/stm32/stm32f767-atk-apollo/rtconfig.py
+134
-0
bsp/stm32/stm32f767-atk-apollo/template.ewp
bsp/stm32/stm32f767-atk-apollo/template.ewp
+2074
-0
bsp/stm32/stm32f767-atk-apollo/template.eww
bsp/stm32/stm32f767-atk-apollo/template.eww
+10
-0
bsp/stm32/stm32f767-atk-apollo/template.uvoptx
bsp/stm32/stm32f767-atk-apollo/template.uvoptx
+191
-0
bsp/stm32/stm32f767-atk-apollo/template.uvprojx
bsp/stm32/stm32f767-atk-apollo/template.uvprojx
+394
-0
bsp/stm32f40x/project.uvprojx
bsp/stm32f40x/project.uvprojx
+273
-79
未找到文件。
bsp/stm32/stm32f767-atk-apollo/.config
0 → 100644
浏览文件 @
864ae989
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX
=
8
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE
=
4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32
=
y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX
=
32
CONFIG_RT_TICK_PER_SECOND
=
1000
CONFIG_RT_USING_OVERFLOW_CHECK
=
y
CONFIG_RT_USING_HOOK
=
y
CONFIG_RT_USING_IDLE_HOOK
=
y
CONFIG_RT_IDEL_HOOK_LIST_SIZE
=
4
CONFIG_IDLE_THREAD_STACK_SIZE
=
1024
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG
=
y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE
=
y
CONFIG_RT_USING_MUTEX
=
y
CONFIG_RT_USING_EVENT
=
y
CONFIG_RT_USING_MAILBOX
=
y
CONFIG_RT_USING_MESSAGEQUEUE
=
y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL
=
y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM
=
y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP
=
y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE
=
y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE
=
y
CONFIG_RT_CONSOLEBUF_SIZE
=
128
CONFIG_RT_CONSOLE_DEVICE_NAME
=
"uart1"
CONFIG_RT_VER_NUM
=
0
x40000
CONFIG_ARCH_ARM
=
y
CONFIG_ARCH_ARM_CORTEX_M
=
y
CONFIG_ARCH_ARM_CORTEX_M7
=
y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT
=
y
CONFIG_RT_USING_USER_MAIN
=
y
CONFIG_RT_MAIN_THREAD_STACK_SIZE
=
2048
CONFIG_RT_MAIN_THREAD_PRIORITY
=
10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH
=
y
CONFIG_FINSH_THREAD_NAME
=
"tshell"
CONFIG_FINSH_USING_HISTORY
=
y
CONFIG_FINSH_HISTORY_LINES
=
5
CONFIG_FINSH_USING_SYMTAB
=
y
CONFIG_FINSH_USING_DESCRIPTION
=
y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY
=
20
CONFIG_FINSH_THREAD_STACK_SIZE
=
4096
CONFIG_FINSH_CMD_SIZE
=
80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH
=
y
CONFIG_FINSH_USING_MSH_DEFAULT
=
y
CONFIG_FINSH_USING_MSH_ONLY
=
y
CONFIG_FINSH_ARG_MAX
=
10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC
=
y
CONFIG_RT_PIPE_BUFSZ
=
512
CONFIG_RT_USING_SERIAL
=
y
CONFIG_RT_SERIAL_USING_DMA
=
y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using WiFi
#
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# ARM CMSIS
#
# CONFIG_RT_USING_CMSIS_OS is not set
# CONFIG_RT_USING_RTT_CMSIS is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
CONFIG_SOC_FAMILY_STM32
=
y
CONFIG_SOC_SERIES_STM32F7
=
y
#
# Hardware Drivers Config
#
CONFIG_SOC_STM32F767IG
=
y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART
=
y
# CONFIG_BSP_USING_RS232 is not set
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_QSPI_FLASH is not set
# CONFIG_BSP_USING_MPU6050 is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO
=
y
CONFIG_BSP_USING_UART1
=
y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_USING_SPI5 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_I2C2 is not set
# CONFIG_BSP_USING_I2C3 is not set
# CONFIG_BSP_USING_I2C4 is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
#
# Board extended module Drivers
#
bsp/stm32/stm32f767-atk-apollo/.gitignore
0 → 100644
浏览文件 @
864ae989
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h
bsp/stm32/stm32f767-atk-apollo/Kconfig
0 → 100644
浏览文件 @
864ae989
mainmenu "RT-Thread Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"
bsp/stm32/stm32f767-atk-apollo/README.md
0 → 100644
浏览文件 @
864ae989
# STM32F767 阿波罗开发板 BSP 说明
## 简介
本文档为 RT-Thread 开发团队为 STM32F767 阿波罗开发板提供的 BSP (板级支持包) 说明。
主要内容如下:
-
开发板资源介绍
-
BSP 快速上手
-
进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP,将 RT-Thread 运行在开发板上。在进阶使用指南章节,将会介绍更多高级功能,帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
阿波罗 STM32F767 是正点原子推出的一款基于 ARM Cortex-M7 内核的开发板,最高主频为 216Mhz,该开发板具有丰富的板载资源,可以充分发挥 STM32F767 的芯片性能。
开发板外观如下图所示:
![
board
](
figures/board.jpg
)
该开发板常用
**板载资源**
如下:
-
MCU:STM32f767,主频 216MHz,1MB FLASH ,512KB RAM ,16K CACHE
-
外部 SDRAM:W9825G6KH, 32MB
-
外部 NAND FLASH: MT29F4G08, 512MB
-
外部 SPI FLASH: W25Q256, 32M
-
常用外设
-
LED:2个,DS0(红色,PB1),DS1(绿色,PB0)
-
按键:4个,KEY_UP(兼具唤醒功能,PA0),K0(PH3),K1(PH2),K2(PC13)
-
常用接口:USB 转串口、SD 卡接口、以太网接口、LCD 接口
-
调试接口,标准 JTAG/SWD
开发板更多详细信息请参考正点原子
[
STM32 阿波罗开发板介绍
](
https://eboard.taobao.com/index.htm
)
。
## 外设支持
本 BSP 目前对外设的支持情况如下:
|
**板载外设**
|
**支持情况**
|
**备注**
|
| :----------------- | :----------: | :------------------------------------- |
| USB 转串口 | 支持 | |
| RS232 | 支持 | 和以太网冲突,如需使用该外设,请使用 CubeMX 重新配置 UART2 管脚 |
| QSPI Flash | 即将支持 | |
| 以太网 | 支持 | |
| MPU9250六轴传感器 | 支持 | |
| SDRAM | 支持 | |
| SD卡 | 即将支持 | |
| CAN | 即将支持 | |
| EMW1062 | 暂不支持 | |
|
**片上外设**
|
**支持情况**
|
**备注**
|
| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
| UART | 支持 | |
| SPI | 支持 | |
| I2C | 支持 | 软件 I2C |
| ADC | 即将支持 | |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 即将支持 | 已适配
[
FAL
](
https://github.com/RT-Thread-packages/fal
)
|
| SDIO | 暂不支持 | 即将支持 |
| PWM | 暂不支持 | 即将支持 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
|
**扩展模块**
|
**支持情况**
|
**备注**
|
| 暂无 | 暂不支持 | 暂不支持 |
## 使用说明
使用说明分为如下两个章节:
-
快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明,遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上,看到实验效果 。
-
进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多板载资源,实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程,并且支持 GCC 开发环境。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC,打开电源开关。
#### 编译下载
双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
> 工程默认配置使用 Jlink 仿真器下载程序,在通过 Jlink 连接开发板的基础上,点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后,系统会自动运行,LED 闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息:
```
bash
\
| /
- RT - Thread Operating System
/ |
\
4.0.0 build Dec 10 2018
2006 - 2018 Copyright by rt-thread team
msh
>
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口1 的功能,如果需使用 SD 卡、Flash 等更多高级功能,需要利用 ENV 工具对BSP 进行配置,步骤如下:
1.
在 bsp 下打开 env 工具。
2.
输入
`menuconfig`
命令配置工程,配置好之后保存退出。
3.
输入
`pkgs --update`
命令更新软件包。
4.
输入
`scons --target=mdk4/mdk5/iar`
命令重新生成工程。
本章节更多详细的介绍请参考
[
BSP 进阶使用指南
](
../docs/BSP进阶使用指南.md
)
。
## 注意事项
暂无
## 联系人信息
维护人:
-
[
SummerGift
](
https://github.com/SummerGGift
)
\ No newline at end of file
bsp/stm32/stm32f767-atk-apollo/SConscript
0 → 100644
浏览文件 @
864ae989
# for module compiling
import
os
Import
(
'RTT_ROOT'
)
cwd
=
str
(
Dir
(
'#'
))
objs
=
[]
list
=
os
.
listdir
(
cwd
)
for
d
in
list
:
path
=
os
.
path
.
join
(
cwd
,
d
)
if
os
.
path
.
isfile
(
os
.
path
.
join
(
path
,
'SConscript'
)):
objs
=
objs
+
SConscript
(
os
.
path
.
join
(
d
,
'SConscript'
))
Return
(
'objs'
)
bsp/stm32/stm32f767-atk-apollo/SConstruct
0 → 100644
浏览文件 @
864ae989
import
os
import
sys
import
rtconfig
if
os
.
getenv
(
'RTT_ROOT'
):
RTT_ROOT
=
os
.
getenv
(
'RTT_ROOT'
)
else
:
RTT_ROOT
=
os
.
path
.
normpath
(
os
.
getcwd
()
+
'/../../..'
)
sys
.
path
=
sys
.
path
+
[
os
.
path
.
join
(
RTT_ROOT
,
'tools'
)]
try
:
from
building
import
*
except
:
print
(
'Cannot found RT-Thread root directory, please check RTT_ROOT'
)
print
(
RTT_ROOT
)
exit
(
-
1
)
TARGET
=
'rt-thread.'
+
rtconfig
.
TARGET_EXT
env
=
Environment
(
tools
=
[
'mingw'
],
AS
=
rtconfig
.
AS
,
ASFLAGS
=
rtconfig
.
AFLAGS
,
CC
=
rtconfig
.
CC
,
CCFLAGS
=
rtconfig
.
CFLAGS
,
AR
=
rtconfig
.
AR
,
ARFLAGS
=
'-rc'
,
LINK
=
rtconfig
.
LINK
,
LINKFLAGS
=
rtconfig
.
LFLAGS
)
env
.
PrependENVPath
(
'PATH'
,
rtconfig
.
EXEC_PATH
)
if
rtconfig
.
PLATFORM
==
'iar'
:
env
.
Replace
(
CCCOM
=
[
'$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'
])
env
.
Replace
(
ARFLAGS
=
[
''
])
env
.
Replace
(
LINKCOM
=
[
'$LINK $SOURCES $LINKFLAGS -o $TARGET --map rt-thread.map'
])
Export
(
'RTT_ROOT'
)
Export
(
'rtconfig'
)
SDK_ROOT
=
os
.
path
.
abspath
(
'./'
)
if
os
.
path
.
exists
(
SDK_ROOT
+
'/libraries'
):
libraries_path_prefix
=
SDK_ROOT
+
'/libraries'
else
:
libraries_path_prefix
=
os
.
path
.
dirname
(
SDK_ROOT
)
+
'/libraries'
SDK_LIB
=
libraries_path_prefix
Export
(
'SDK_LIB'
)
# prepare building environment
objs
=
PrepareBuilding
(
env
,
RTT_ROOT
,
has_libcpu
=
False
)
stm32_library
=
'STM32F7xx_HAL'
rtconfig
.
BSP_LIBRARY_TYPE
=
stm32_library
# include libraries
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
stm32_library
,
'SConscript'
)))
# include drivers
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
'HAL_Drivers'
,
'SConscript'
)))
# make a building
DoBuilding
(
TARGET
,
objs
)
bsp/stm32/stm32f767-atk-apollo/applications/SConscript
0 → 100644
浏览文件 @
864ae989
import
rtconfig
from
building
import
*
cwd
=
GetCurrentDir
()
CPPPATH
=
[
cwd
,
str
(
Dir
(
'#'
))]
src
=
Split
(
"""
main.c
"""
)
group
=
DefineGroup
(
'Applications'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
)
Return
(
'group'
)
bsp/stm32/stm32f767-atk-apollo/applications/main.c
0 → 100644
浏览文件 @
864ae989
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 BalanceTWK first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include "drv_gpio.h"
/* defined the LED0 pin: PB1 */
#define LED0_PIN GET_PIN(B, 1)
int
main
(
void
)
{
int
count
=
1
;
/* set LED0 pin mode to output */
rt_pin_mode
(
LED0_PIN
,
PIN_MODE_OUTPUT
);
while
(
count
++
)
{
rt_pin_write
(
LED0_PIN
,
PIN_HIGH
);
rt_thread_mdelay
(
500
);
rt_pin_write
(
LED0_PIN
,
PIN_LOW
);
rt_thread_mdelay
(
500
);
}
return
RT_EOK
;
}
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject
0 → 100644
浏览文件 @
864ae989
[PreviousGenFiles]
HeaderPath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc
HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h;
SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src
SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedKeilFiles]
SourceFiles=..\Src\main.c;..\Src\stm32f7xx_it.c;..\Src\stm32f7xx_hal_msp.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;../\Src/system_stm32f7xx.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;../\Src/system_stm32f7xx.c;../Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;null;
HeaderPath=..\Drivers\STM32F7xx_HAL_Driver\Inc;..\Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F7xx\Include;..\Drivers\CMSIS\Include;..\Inc;
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc
0 → 100644
浏览文件 @
864ae989
#MicroXplorer Configuration settings - do not modify
CORTEX_M7.CPU_DCache=Enabled
CORTEX_M7.CPU_ICache=Enabled
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,PREFETCH_ENABLE
CORTEX_M7.PREFETCH_ENABLE=1
ETH.IPParameters=MediaInterface
ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F7
Mcu.IP0=CORTEX_M7
Mcu.IP1=ETH
Mcu.IP10=USART1
Mcu.IP11=USART2
Mcu.IP12=USART3
Mcu.IP2=FMC
Mcu.IP3=IWDG
Mcu.IP4=NVIC
Mcu.IP5=QUADSPI
Mcu.IP6=RCC
Mcu.IP7=RTC
Mcu.IP8=SPI2
Mcu.IP9=SYS
Mcu.IPNb=13
Mcu.Name=STM32F767I(G-I)Tx
Mcu.Package=LQFP176
Mcu.Pin0=PC14/OSC32_IN
Mcu.Pin1=PC15/OSC32_OUT
Mcu.Pin10=PF8
Mcu.Pin11=PF9
Mcu.Pin12=PH0/OSC_IN
Mcu.Pin13=PH1/OSC_OUT
Mcu.Pin14=PC0
Mcu.Pin15=PC1
Mcu.Pin16=PC2
Mcu.Pin17=PC3
Mcu.Pin18=PA1
Mcu.Pin19=PA2
Mcu.Pin2=PF0
Mcu.Pin20=PA3
Mcu.Pin21=PA7
Mcu.Pin22=PC4
Mcu.Pin23=PC5
Mcu.Pin24=PB2
Mcu.Pin25=PF11
Mcu.Pin26=PF12
Mcu.Pin27=PF13
Mcu.Pin28=PF14
Mcu.Pin29=PF15
Mcu.Pin3=PF1
Mcu.Pin30=PG0
Mcu.Pin31=PG1
Mcu.Pin32=PE7
Mcu.Pin33=PE8
Mcu.Pin34=PE9
Mcu.Pin35=PE10
Mcu.Pin36=PE11
Mcu.Pin37=PE12
Mcu.Pin38=PE13
Mcu.Pin39=PE14
Mcu.Pin4=PF2
Mcu.Pin40=PE15
Mcu.Pin41=PB10
Mcu.Pin42=PB11
Mcu.Pin43=PB13
Mcu.Pin44=PB14
Mcu.Pin45=PB15
Mcu.Pin46=PD8
Mcu.Pin47=PD9
Mcu.Pin48=PD10
Mcu.Pin49=PD14
Mcu.Pin5=PF3
Mcu.Pin50=PD15
Mcu.Pin51=PG2
Mcu.Pin52=PG4
Mcu.Pin53=PG5
Mcu.Pin54=PG8
Mcu.Pin55=PA9
Mcu.Pin56=PA10
Mcu.Pin57=PA13
Mcu.Pin58=PA14
Mcu.Pin59=PC11
Mcu.Pin6=PF4
Mcu.Pin60=PD0
Mcu.Pin61=PD1
Mcu.Pin62=PD5
Mcu.Pin63=PG13
Mcu.Pin64=PG14
Mcu.Pin65=PG15
Mcu.Pin66=PB6
Mcu.Pin67=VP_IWDG_VS_IWDG
Mcu.Pin68=VP_RTC_VS_RTC_Activate
Mcu.Pin69=VP_SYS_VS_Systick
Mcu.Pin7=PF5
Mcu.Pin8=PF6
Mcu.Pin9=PF7
Mcu.PinsNb=70
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F767IGTx
MxCube.Version=5.0.0
MxDb.Version=DB.5.0.0
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
PA1.Mode=RMII
PA1.Signal=ETH_REF_CLK
PA10.Locked=true
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA2.Mode=RMII
PA2.Signal=ETH_MDIO
PA3.Mode=Asynchronous
PA3.Signal=USART2_RX
PA7.Mode=RMII
PA7.Signal=ETH_CRS_DV
PA9.Locked=true
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB10.Mode=Asynchronous
PB10.Signal=USART3_TX
PB11.Mode=RMII
PB11.Signal=ETH_TX_EN
PB13.Locked=true
PB13.Mode=Full_Duplex_Master
PB13.Signal=SPI2_SCK
PB14.Locked=true
PB14.Mode=Full_Duplex_Master
PB14.Signal=SPI2_MISO
PB15.Locked=true
PB15.Mode=Full_Duplex_Master
PB15.Signal=SPI2_MOSI
PB2.Locked=true
PB2.Mode=Single Bank 1
PB2.Signal=QUADSPI_CLK
PB6.Locked=true
PB6.Mode=Single Bank 1
PB6.Signal=QUADSPI_BK1_NCS
PC0.Signal=FMC_SDNWE
PC1.Mode=RMII
PC1.Signal=ETH_MDC
PC11.Mode=Asynchronous
PC11.Signal=USART3_RX
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.Mode=SdramChipSelect1_1
PC2.Signal=FMC_SDNE0
PC3.Mode=SdramChipSelect1_1
PC3.Signal=FMC_SDCKE0
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
PC5.Signal=ETH_RXD1
PCC.Checker=false
PCC.Line=STM32F7x7
PCC.MCU=STM32F767I(G-I)Tx
PCC.PartNumber=STM32F767IGTx
PCC.Seq0=0
PCC.Series=STM32F7
PCC.Temperature=25
PCC.Vdd=3.3
PD0.Signal=FMC_D2_DA2
PD1.Signal=FMC_D3_DA3
PD10.Signal=FMC_D15_DA15
PD14.Signal=FMC_D0_DA0
PD15.Signal=FMC_D1_DA1
PD5.Mode=Asynchronous
PD5.Signal=USART2_TX
PD8.Signal=FMC_D13_DA13
PD9.Signal=FMC_D14_DA14
PE10.Signal=FMC_D7_DA7
PE11.Signal=FMC_D8_DA8
PE12.Signal=FMC_D9_DA9
PE13.Signal=FMC_D10_DA10
PE14.Signal=FMC_D11_DA11
PE15.Signal=FMC_D12_DA12
PE7.Signal=FMC_D4_DA4
PE8.Signal=FMC_D5_DA5
PE9.Signal=FMC_D6_DA6
PF0.Signal=FMC_A0
PF1.Signal=FMC_A1
PF11.Signal=FMC_SDNRAS
PF12.Signal=FMC_A6
PF13.Signal=FMC_A7
PF14.Signal=FMC_A8
PF15.Signal=FMC_A9
PF2.Signal=FMC_A2
PF3.Signal=FMC_A3
PF4.Signal=FMC_A4
PF5.Signal=FMC_A5
PF6.Locked=true
PF6.Mode=Single Bank 1
PF6.Signal=QUADSPI_BK1_IO3
PF7.Locked=true
PF7.Mode=Single Bank 1
PF7.Signal=QUADSPI_BK1_IO2
PF8.Locked=true
PF8.Mode=Single Bank 1
PF8.Signal=QUADSPI_BK1_IO0
PF9.Locked=true
PF9.Mode=Single Bank 1
PF9.Signal=QUADSPI_BK1_IO1
PG0.Signal=FMC_A10
PG1.Signal=FMC_A11
PG13.Locked=true
PG13.Mode=RMII
PG13.Signal=ETH_TXD0
PG14.Mode=RMII
PG14.Signal=ETH_TXD1
PG15.Signal=FMC_SDNCAS
PG2.Signal=FMC_A12
PG4.Signal=FMC_A14_BA0
PG5.Signal=FMC_A15_BA1
PG8.Signal=FMC_SDCLK
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
PH1/OSC_OUT.Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F767IGTx
ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.14.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=CubeMX_Config.ioc
ProjectManager.ProjectName=CubeMX_Config
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_QUADSPI_Init-QUADSPI-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_USART2_UART_Init-USART2-false-HAL-true,9-MX_USART3_UART_Init-USART3-false-HAL-true,10-MX_ETH_Init-ETH-false-HAL-true,11-MX_IWDG_Init-IWDG-false-HAL-true,12-MX_FMC_Init-FMC-false-HAL-true
RCC.AHBFreq_Value=216000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=54000000
RCC.APB1TimFreq_Value=108000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=108000000
RCC.APB2TimFreq_Value=216000000
RCC.CECFreq_Value=32786.88524590164
RCC.CortexFreq_Value=216000000
RCC.DFSDMAudioFreq_Value=96000000
RCC.DFSDMFreq_Value=108000000
RCC.EthernetFreq_Value=216000000
RCC.FCLKCortexFreq_Value=216000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=216000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=54000000
RCC.I2C2Freq_Value=54000000
RCC.I2C3Freq_Value=54000000
RCC.I2C4Freq_Value=54000000
RCC.I2SFreq_Value=96000000
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.LCDTFTFreq_Value=48000000
RCC.LPTIM1Freq_Value=54000000
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=216000000
RCC.PLLCLKFreq_Value=216000000
RCC.PLLI2SPCLKFreq_Value=96000000
RCC.PLLI2SQCLKFreq_Value=96000000
RCC.PLLI2SRCLKFreq_Value=96000000
RCC.PLLI2SRoutputFreq_Value=96000000
RCC.PLLM=25
RCC.PLLN=432
RCC.PLLQCLKFreq_Value=216000000
RCC.PLLQoutputFreq_Value=216000000
RCC.PLLRFreq_Value=216000000
RCC.PLLSAIPCLKFreq_Value=96000000
RCC.PLLSAIQCLKFreq_Value=96000000
RCC.PLLSAIRCLKFreq_Value=96000000
RCC.PLLSAIoutputFreq_Value=96000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RNGFreq_Value=216000000
RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.SAI1Freq_Value=96000000
RCC.SAI2Freq_Value=96000000
RCC.SDMMC2Freq_Value=216000000
RCC.SDMMCFreq_Value=216000000
RCC.SPDIFRXFreq_Value=96000000
RCC.SYSCLKFreq_VALUE=216000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=54000000
RCC.UART5Freq_Value=54000000
RCC.UART7Freq_Value=54000000
RCC.UART8Freq_Value=54000000
RCC.USART1Freq_Value=108000000
RCC.USART2Freq_Value=54000000
RCC.USART3Freq_Value=54000000
RCC.USART6Freq_Value=108000000
RCC.USBFreq_Value=216000000
RCC.VCOI2SOutputFreq_Value=192000000
RCC.VCOInputFreq_Value=1000000
RCC.VCOOutputFreq_Value=432000000
RCC.VCOSAIOutputFreq_Value=192000000
SH.FMC_A0.0=FMC_A0,13b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,13b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,13b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,13b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A12.0=FMC_A12,13b-sda1
SH.FMC_A12.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,13b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,13b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,13b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,13b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,13b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,13b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,13b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,13b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,13b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,13b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1
SH.FMC_SDNWE.ConfNb=1
SPI2.CalculateBaudRate=27.0 MBits/s
SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualType=VM_MASTER
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
USART2.IPParameters=VirtualMode-Asynchronous
USART2.VirtualMode-Asynchronous=VM_ASYNC
USART3.IPParameters=VirtualMode-Asynchronous
USART3.VirtualMode-Asynchronous=VM_ASYNC
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/main.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void
Error_Handler
(
void
);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif
/* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h
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/**
******************************************************************************
* @file stm32f7xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_CONF_H
#define __STM32F7xx_HAL_CONF_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LPTIM_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED
/* #define HAL_RNG_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_MDIOS_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_EXTI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000U)
/*!< Value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U)
/*!< Time out for HSE start up, in ms */
#endif
/* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U)
/*!< LSI Typical Value in Hz*/
#endif
/* LSI_VALUE */
/*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U)
/*!< Value of the External Low Speed oscillator in Hz */
#endif
/* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U)
/*!< Time out for LSE start up, in ms */
#endif
/* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U)
/*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U)
/*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define ART_ACCLERATOR_ENABLE 0U
/* To enable instruction cache and prefetch */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
/* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
/* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U)
/* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U)
/* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* LAN8742A_PHY_ADDRESS Address*/
#define LAN8742A_PHY_ADDRESS 1
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00U)
/*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01U)
/*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U)
/*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U)
/*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U)
/*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U)
/*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U)
/*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U)
/*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U)
/*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U)
/*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U)
/*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U)
/*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U)
/*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U)
/*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U)
/*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10U)
/*!< PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U)
/*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U)
/*!< PHY Duplex mask */
#define PHY_ISFR ((uint16_t)0x000BU)
/*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((uint16_t)0x000BU)
/*!< PHY Link down inturrupt */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f7xx_hal_rcc.h"
#endif
/* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f7xx_hal_exti.h"
#endif
/* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f7xx_hal_gpio.h"
#endif
/* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f7xx_hal_dma.h"
#endif
/* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f7xx_hal_cortex.h"
#endif
/* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f7xx_hal_adc.h"
#endif
/* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f7xx_hal_can.h"
#endif
/* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f7xx_hal_cec.h"
#endif
/* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f7xx_hal_crc.h"
#endif
/* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f7xx_hal_cryp.h"
#endif
/* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f7xx_hal_dma2d.h"
#endif
/* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f7xx_hal_dac.h"
#endif
/* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f7xx_hal_dcmi.h"
#endif
/* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f7xx_hal_eth.h"
#endif
/* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f7xx_hal_flash.h"
#endif
/* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f7xx_hal_sram.h"
#endif
/* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f7xx_hal_nor.h"
#endif
/* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f7xx_hal_nand.h"
#endif
/* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f7xx_hal_sdram.h"
#endif
/* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f7xx_hal_hash.h"
#endif
/* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f7xx_hal_i2c.h"
#endif
/* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f7xx_hal_i2s.h"
#endif
/* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f7xx_hal_iwdg.h"
#endif
/* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32f7xx_hal_lptim.h"
#endif
/* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f7xx_hal_ltdc.h"
#endif
/* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f7xx_hal_pwr.h"
#endif
/* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32f7xx_hal_qspi.h"
#endif
/* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f7xx_hal_rng.h"
#endif
/* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f7xx_hal_rtc.h"
#endif
/* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f7xx_hal_sai.h"
#endif
/* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f7xx_hal_sd.h"
#endif
/* HAL_SD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f7xx_hal_mmc.h"
#endif
/* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f7xx_hal_spdifrx.h"
#endif
/* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f7xx_hal_spi.h"
#endif
/* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f7xx_hal_tim.h"
#endif
/* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f7xx_hal_uart.h"
#endif
/* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f7xx_hal_usart.h"
#endif
/* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f7xx_hal_irda.h"
#endif
/* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f7xx_hal_smartcard.h"
#endif
/* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f7xx_hal_wwdg.h"
#endif
/* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f7xx_hal_pcd.h"
#endif
/* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f7xx_hal_hcd.h"
#endif
/* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32f7xx_hal_dfsdm.h"
#endif
/* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32f7xx_hal_dsi.h"
#endif
/* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_JPEG_MODULE_ENABLED
#include "stm32f7xx_hal_jpeg.h"
#endif
/* HAL_JPEG_MODULE_ENABLED */
#ifdef HAL_MDIOS_MODULE_ENABLED
#include "stm32f7xx_hal_mdios.h"
#endif
/* HAL_MDIOS_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f7xx_hal_smbus.h"
#endif
/* HAL_SMBUS_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void
assert_failed
(
uint8_t
*
file
,
uint32_t
line
);
#else
#define assert_param(expr) ((void)0U)
#endif
/* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif
/* __STM32F7xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f7xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_IT_H
#define __STM32F7xx_IT_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void
NMI_Handler
(
void
);
void
HardFault_Handler
(
void
);
void
MemManage_Handler
(
void
);
void
BusFault_Handler
(
void
);
void
UsageFault_Handler
(
void
);
void
SVC_Handler
(
void
);
void
DebugMon_Handler
(
void
);
void
PendSV_Handler
(
void
);
void
SysTick_Handler
(
void
);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif
/* __STM32F7xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c
0 → 100644
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ETH_HandleTypeDef
heth
;
IWDG_HandleTypeDef
hiwdg
;
QSPI_HandleTypeDef
hqspi
;
RTC_HandleTypeDef
hrtc
;
SPI_HandleTypeDef
hspi2
;
UART_HandleTypeDef
huart1
;
UART_HandleTypeDef
huart2
;
UART_HandleTypeDef
huart3
;
SDRAM_HandleTypeDef
hsdram1
;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void
SystemClock_Config
(
void
);
static
void
MX_GPIO_Init
(
void
);
static
void
MX_USART1_UART_Init
(
void
);
static
void
MX_RTC_Init
(
void
);
static
void
MX_QUADSPI_Init
(
void
);
static
void
MX_SPI2_Init
(
void
);
static
void
MX_USART2_UART_Init
(
void
);
static
void
MX_USART3_UART_Init
(
void
);
static
void
MX_ETH_Init
(
void
);
static
void
MX_IWDG_Init
(
void
);
static
void
MX_FMC_Init
(
void
);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int
main
(
void
)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache
();
/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache
();
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init
();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config
();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init
();
MX_USART1_UART_Init
();
MX_RTC_Init
();
MX_QUADSPI_Init
();
MX_SPI2_Init
();
MX_USART2_UART_Init
();
MX_USART3_UART_Init
();
MX_ETH_Init
();
MX_IWDG_Init
();
MX_FMC_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while
(
1
)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void
SystemClock_Config
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
=
{
0
};
/**Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess
();
__HAL_RCC_LSEDRIVE_CONFIG
(
RCC_LSEDRIVE_LOW
);
/**Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE
();
__HAL_PWR_VOLTAGESCALING_CONFIG
(
PWR_REGULATOR_VOLTAGE_SCALE1
);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_LSI
|
RCC_OSCILLATORTYPE_HSE
|
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
RCC_OscInitStruct
.
LSIState
=
RCC_LSI_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
25
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
432
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Activate the Over-Drive mode
*/
if
(
HAL_PWREx_EnableOverDrive
()
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV4
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV2
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_7
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
|
RCC_PERIPHCLK_USART1
|
RCC_PERIPHCLK_USART2
|
RCC_PERIPHCLK_USART3
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
PeriphClkInitStruct
.
Usart1ClockSelection
=
RCC_USART1CLKSOURCE_PCLK2
;
PeriphClkInitStruct
.
Usart2ClockSelection
=
RCC_USART2CLKSOURCE_PCLK1
;
PeriphClkInitStruct
.
Usart3ClockSelection
=
RCC_USART3CLKSOURCE_PCLK1
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief ETH Initialization Function
* @param None
* @retval None
*/
static
void
MX_ETH_Init
(
void
)
{
/* USER CODE BEGIN ETH_Init 0 */
/* USER CODE END ETH_Init 0 */
uint8_t
MACAddr
[
6
]
;
/* USER CODE BEGIN ETH_Init 1 */
/* USER CODE END ETH_Init 1 */
heth
.
Instance
=
ETH
;
heth
.
Init
.
AutoNegotiation
=
ETH_AUTONEGOTIATION_ENABLE
;
heth
.
Init
.
PhyAddress
=
LAN8742A_PHY_ADDRESS
;
MACAddr
[
0
]
=
0x00
;
MACAddr
[
1
]
=
0x80
;
MACAddr
[
2
]
=
0xE1
;
MACAddr
[
3
]
=
0x00
;
MACAddr
[
4
]
=
0x00
;
MACAddr
[
5
]
=
0x00
;
heth
.
Init
.
MACAddr
=
&
MACAddr
[
0
];
heth
.
Init
.
RxMode
=
ETH_RXPOLLING_MODE
;
heth
.
Init
.
ChecksumMode
=
ETH_CHECKSUM_BY_HARDWARE
;
heth
.
Init
.
MediaInterface
=
ETH_MEDIA_INTERFACE_RMII
;
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
if
(
HAL_ETH_Init
(
&
heth
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN ETH_Init 2 */
/* USER CODE END ETH_Init 2 */
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static
void
MX_IWDG_Init
(
void
)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg
.
Instance
=
IWDG
;
hiwdg
.
Init
.
Prescaler
=
IWDG_PRESCALER_4
;
hiwdg
.
Init
.
Window
=
4095
;
hiwdg
.
Init
.
Reload
=
4095
;
if
(
HAL_IWDG_Init
(
&
hiwdg
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief QUADSPI Initialization Function
* @param None
* @retval None
*/
static
void
MX_QUADSPI_Init
(
void
)
{
/* USER CODE BEGIN QUADSPI_Init 0 */
/* USER CODE END QUADSPI_Init 0 */
/* USER CODE BEGIN QUADSPI_Init 1 */
/* USER CODE END QUADSPI_Init 1 */
/* QUADSPI parameter configuration*/
hqspi
.
Instance
=
QUADSPI
;
hqspi
.
Init
.
ClockPrescaler
=
255
;
hqspi
.
Init
.
FifoThreshold
=
1
;
hqspi
.
Init
.
SampleShifting
=
QSPI_SAMPLE_SHIFTING_NONE
;
hqspi
.
Init
.
FlashSize
=
1
;
hqspi
.
Init
.
ChipSelectHighTime
=
QSPI_CS_HIGH_TIME_1_CYCLE
;
hqspi
.
Init
.
ClockMode
=
QSPI_CLOCK_MODE_0
;
hqspi
.
Init
.
FlashID
=
QSPI_FLASH_ID_1
;
hqspi
.
Init
.
DualFlash
=
QSPI_DUALFLASH_DISABLE
;
if
(
HAL_QSPI_Init
(
&
hqspi
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN QUADSPI_Init 2 */
/* USER CODE END QUADSPI_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static
void
MX_RTC_Init
(
void
)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/**Initialize RTC Only
*/
hrtc
.
Instance
=
RTC
;
hrtc
.
Init
.
HourFormat
=
RTC_HOURFORMAT_24
;
hrtc
.
Init
.
AsynchPrediv
=
127
;
hrtc
.
Init
.
SynchPrediv
=
255
;
hrtc
.
Init
.
OutPut
=
RTC_OUTPUT_DISABLE
;
hrtc
.
Init
.
OutPutPolarity
=
RTC_OUTPUT_POLARITY_HIGH
;
hrtc
.
Init
.
OutPutType
=
RTC_OUTPUT_TYPE_OPENDRAIN
;
if
(
HAL_RTC_Init
(
&
hrtc
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static
void
MX_SPI2_Init
(
void
)
{
/* USER CODE BEGIN SPI2_Init 0 */
/* USER CODE END SPI2_Init 0 */
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2
.
Instance
=
SPI2
;
hspi2
.
Init
.
Mode
=
SPI_MODE_MASTER
;
hspi2
.
Init
.
Direction
=
SPI_DIRECTION_2LINES
;
hspi2
.
Init
.
DataSize
=
SPI_DATASIZE_4BIT
;
hspi2
.
Init
.
CLKPolarity
=
SPI_POLARITY_LOW
;
hspi2
.
Init
.
CLKPhase
=
SPI_PHASE_1EDGE
;
hspi2
.
Init
.
NSS
=
SPI_NSS_SOFT
;
hspi2
.
Init
.
BaudRatePrescaler
=
SPI_BAUDRATEPRESCALER_2
;
hspi2
.
Init
.
FirstBit
=
SPI_FIRSTBIT_MSB
;
hspi2
.
Init
.
TIMode
=
SPI_TIMODE_DISABLE
;
hspi2
.
Init
.
CRCCalculation
=
SPI_CRCCALCULATION_DISABLE
;
hspi2
.
Init
.
CRCPolynomial
=
7
;
hspi2
.
Init
.
CRCLength
=
SPI_CRC_LENGTH_DATASIZE
;
hspi2
.
Init
.
NSSPMode
=
SPI_NSS_PULSE_ENABLE
;
if
(
HAL_SPI_Init
(
&
hspi2
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
/**
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_USART1_UART_Init
(
void
)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1
.
Instance
=
USART1
;
huart1
.
Init
.
BaudRate
=
115200
;
huart1
.
Init
.
WordLength
=
UART_WORDLENGTH_8B
;
huart1
.
Init
.
StopBits
=
UART_STOPBITS_1
;
huart1
.
Init
.
Parity
=
UART_PARITY_NONE
;
huart1
.
Init
.
Mode
=
UART_MODE_TX_RX
;
huart1
.
Init
.
HwFlowCtl
=
UART_HWCONTROL_NONE
;
huart1
.
Init
.
OverSampling
=
UART_OVERSAMPLING_16
;
huart1
.
Init
.
OneBitSampling
=
UART_ONE_BIT_SAMPLE_DISABLE
;
huart1
.
AdvancedInit
.
AdvFeatureInit
=
UART_ADVFEATURE_NO_INIT
;
if
(
HAL_UART_Init
(
&
huart1
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/**
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static
void
MX_USART2_UART_Init
(
void
)
{
/* USER CODE BEGIN USART2_Init 0 */
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2
.
Instance
=
USART2
;
huart2
.
Init
.
BaudRate
=
115200
;
huart2
.
Init
.
WordLength
=
UART_WORDLENGTH_8B
;
huart2
.
Init
.
StopBits
=
UART_STOPBITS_1
;
huart2
.
Init
.
Parity
=
UART_PARITY_NONE
;
huart2
.
Init
.
Mode
=
UART_MODE_TX_RX
;
huart2
.
Init
.
HwFlowCtl
=
UART_HWCONTROL_NONE
;
huart2
.
Init
.
OverSampling
=
UART_OVERSAMPLING_16
;
huart2
.
Init
.
OneBitSampling
=
UART_ONE_BIT_SAMPLE_DISABLE
;
huart2
.
AdvancedInit
.
AdvFeatureInit
=
UART_ADVFEATURE_NO_INIT
;
if
(
HAL_UART_Init
(
&
huart2
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
/**
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static
void
MX_USART3_UART_Init
(
void
)
{
/* USER CODE BEGIN USART3_Init 0 */
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3
.
Instance
=
USART3
;
huart3
.
Init
.
BaudRate
=
115200
;
huart3
.
Init
.
WordLength
=
UART_WORDLENGTH_8B
;
huart3
.
Init
.
StopBits
=
UART_STOPBITS_1
;
huart3
.
Init
.
Parity
=
UART_PARITY_NONE
;
huart3
.
Init
.
Mode
=
UART_MODE_TX_RX
;
huart3
.
Init
.
HwFlowCtl
=
UART_HWCONTROL_NONE
;
huart3
.
Init
.
OverSampling
=
UART_OVERSAMPLING_16
;
huart3
.
Init
.
OneBitSampling
=
UART_ONE_BIT_SAMPLE_DISABLE
;
huart3
.
AdvancedInit
.
AdvFeatureInit
=
UART_ADVFEATURE_NO_INIT
;
if
(
HAL_UART_Init
(
&
huart3
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
/* FMC initialization function */
static
void
MX_FMC_Init
(
void
)
{
FMC_SDRAM_TimingTypeDef
SdramTiming
;
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1
.
Instance
=
FMC_SDRAM_DEVICE
;
/* hsdram1.Init */
hsdram1
.
Init
.
SDBank
=
FMC_SDRAM_BANK1
;
hsdram1
.
Init
.
ColumnBitsNumber
=
FMC_SDRAM_COLUMN_BITS_NUM_8
;
hsdram1
.
Init
.
RowBitsNumber
=
FMC_SDRAM_ROW_BITS_NUM_13
;
hsdram1
.
Init
.
MemoryDataWidth
=
FMC_SDRAM_MEM_BUS_WIDTH_16
;
hsdram1
.
Init
.
InternalBankNumber
=
FMC_SDRAM_INTERN_BANKS_NUM_4
;
hsdram1
.
Init
.
CASLatency
=
FMC_SDRAM_CAS_LATENCY_1
;
hsdram1
.
Init
.
WriteProtection
=
FMC_SDRAM_WRITE_PROTECTION_DISABLE
;
hsdram1
.
Init
.
SDClockPeriod
=
FMC_SDRAM_CLOCK_DISABLE
;
hsdram1
.
Init
.
ReadBurst
=
FMC_SDRAM_RBURST_DISABLE
;
hsdram1
.
Init
.
ReadPipeDelay
=
FMC_SDRAM_RPIPE_DELAY_0
;
/* SdramTiming */
SdramTiming
.
LoadToActiveDelay
=
16
;
SdramTiming
.
ExitSelfRefreshDelay
=
16
;
SdramTiming
.
SelfRefreshTime
=
16
;
SdramTiming
.
RowCycleDelay
=
16
;
SdramTiming
.
WriteRecoveryTime
=
16
;
SdramTiming
.
RPDelay
=
16
;
SdramTiming
.
RCDDelay
=
16
;
if
(
HAL_SDRAM_Init
(
&
hsdram1
,
&
SdramTiming
)
!=
HAL_OK
)
{
Error_Handler
(
);
}
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static
void
MX_GPIO_Init
(
void
)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOF_CLK_ENABLE
();
__HAL_RCC_GPIOH_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
__HAL_RCC_GPIOE_CLK_ENABLE
();
__HAL_RCC_GPIOD_CLK_ENABLE
();
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void
Error_Handler
(
void
)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void
assert_failed
(
uint8_t
*
file
,
uint32_t
line
)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif
/* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
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点击以展开。
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f7xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f7xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M7 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void
NMI_Handler
(
void
)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void
HardFault_Handler
(
void
)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void
MemManage_Handler
(
void
)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void
BusFault_Handler
(
void
)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void
UsageFault_Handler
(
void
)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void
SVC_Handler
(
void
)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void
DebugMon_Handler
(
void
)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void
PendSV_Handler
(
void
)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void
SysTick_Handler
(
void
)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick
();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F7xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f7xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/system_stm32f7xx.c
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/**
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx_system
* @{
*/
/** @addtogroup STM32F7xx_System_Private_Includes
* @{
*/
#include "stm32f7xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000)
/*!< Default value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00
/*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t
SystemCoreClock
=
16000000
;
const
uint8_t
AHBPrescTable
[
16
]
=
{
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
,
6
,
7
,
8
,
9
};
const
uint8_t
APBPrescTable
[
8
]
=
{
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
};
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void
SystemInit
(
void
)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB
->
CPACR
|=
((
3UL
<<
10
*
2
)
|
(
3UL
<<
11
*
2
));
/* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC
->
CR
|=
(
uint32_t
)
0x00000001
;
/* Reset CFGR register */
RCC
->
CFGR
=
0x00000000
;
/* Reset HSEON, CSSON and PLLON bits */
RCC
->
CR
&=
(
uint32_t
)
0xFEF6FFFF
;
/* Reset PLLCFGR register */
RCC
->
PLLCFGR
=
0x24003010
;
/* Reset HSEBYP bit */
RCC
->
CR
&=
(
uint32_t
)
0xFFFBFFFF
;
/* Disable all interrupts */
RCC
->
CIR
=
0x00000000
;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB
->
VTOR
=
RAMDTCM_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal SRAM */
#else
SCB
->
VTOR
=
FLASH_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void
SystemCoreClockUpdate
(
void
)
{
uint32_t
tmp
=
0
,
pllvco
=
0
,
pllp
=
2
,
pllsource
=
0
,
pllm
=
2
;
/* Get SYSCLK source -------------------------------------------------------*/
tmp
=
RCC
->
CFGR
&
RCC_CFGR_SWS
;
switch
(
tmp
)
{
case
0x00
:
/* HSI used as system clock source */
SystemCoreClock
=
HSI_VALUE
;
break
;
case
0x04
:
/* HSE used as system clock source */
SystemCoreClock
=
HSE_VALUE
;
break
;
case
0x08
:
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource
=
(
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLSRC
)
>>
22
;
pllm
=
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLM
;
if
(
pllsource
!=
0
)
{
/* HSE used as PLL clock source */
pllvco
=
(
HSE_VALUE
/
pllm
)
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
6
);
}
else
{
/* HSI used as PLL clock source */
pllvco
=
(
HSI_VALUE
/
pllm
)
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
6
);
}
pllp
=
(((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLP
)
>>
16
)
+
1
)
*
2
;
SystemCoreClock
=
pllvco
/
pllp
;
break
;
default:
SystemCoreClock
=
HSI_VALUE
;
break
;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp
=
AHBPrescTable
[((
RCC
->
CFGR
&
RCC_CFGR_HPRE
)
>>
4
)];
/* HCLK frequency */
SystemCoreClock
>>=
tmp
;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
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menu "Hardware Drivers Config"
config SOC_STM32F767IG
bool
select SOC_SERIES_STM32F7
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart1)"
select BSP_USING_UART1
default y
config BSP_USING_RS232
bool "Enable RS232 (uart2 pin conflict with Ethernet)"
select BSP_USING_UART2
default n
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (W25Q256 qspi)"
select BSP_USING_QSPI
select RT_USING_SFUD
select RT_SFUD_USING_QSPI
default n
config BSP_USING_MPU9250
bool "Enable MPU 9250 (i2c2)"
select BSP_USING_I2C2
select PKG_USING_MPU6XXX
default n
config PHY_USING_LAN8720A
bool
config BSP_USING_ETH
bool "Enable Ethernet"
default n
select RT_USING_LWIP
select PHY_USING_LAN8720A
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
default y
config BSP_USING_UART2
bool "Enable UART2"
select RT_USING_SERIAL
default n
config BSP_USING_UART3
bool "Enable UART3"
select RT_USING_SERIAL
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
select RT_USING_SPI
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
comment "Notice: PB8 --> 24; PB9 --> 25"
config BSP_I2C1_SCL_PIN
int "I2C1 scl pin number"
range 1 176
default 24
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 1 176
default 25
endif
menuconfig BSP_USING_I2C2
bool "Enable I2C2 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C2
comment "Notice: PH4 --> 116; PH5 --> 117"
config BSP_I2C2_SCL_PIN
int "i2c2 scl pin number"
range 1 176
default 116
config BSP_I2C2_SDA_PIN
int "I2C2 sda pin number"
range 1 176
default 117
endif
config BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
endmenu
menu "Board extended module Drivers"
endmenu
endmenu
bsp/stm32/stm32f767-atk-apollo/board/SConscript
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import
os
import
rtconfig
from
building
import
*
Import
(
'SDK_LIB'
)
cwd
=
GetCurrentDir
()
# add general drivers
src
=
Split
(
'''
board.c
CubeMX_Config/Src/stm32f7xx_hal_msp.c
'''
)
if
GetDepend
([
'BSP_USING_ETH'
]):
src
+=
Glob
(
'ports/phy_reset.c'
)
if
GetDepend
([
'BSP_USING_QSPI_FLASH'
]):
src
+=
Glob
(
'ports/drv_qspi_flash.c'
)
if
GetDepend
([
'BSP_USING_SDCARD'
]):
src
+=
Glob
(
'ports/sdcard_port.c'
)
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
path
+=
[
cwd
+
'/ports'
]
startup_path_prefix
=
SDK_LIB
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
startup_path_prefix
+
'/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s'
]
elif
rtconfig
.
CROSS_TOOL
==
'keil'
:
src
+=
[
startup_path_prefix
+
'/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/arm/startup_stm32f767xx.s'
]
elif
rtconfig
.
CROSS_TOOL
==
'iar'
:
src
+=
[
startup_path_prefix
+
'/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/startup_stm32f767xx.s'
]
CPPDEFINES
=
[
'STM32F767xx'
]
group
=
DefineGroup
(
'Drivers'
,
src
,
depend
=
[
''
],
CPPPATH
=
path
,
CPPDEFINES
=
CPPDEFINES
)
Return
(
'group'
)
\ No newline at end of file
bsp/stm32/stm32f767-atk-apollo/board/board.c
0 → 100644
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
*/
#include "board.h"
void
SystemClock_Config
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
=
{
0
};
/**Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess
();
__HAL_RCC_LSEDRIVE_CONFIG
(
RCC_LSEDRIVE_LOW
);
/**Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE
();
__HAL_PWR_VOLTAGESCALING_CONFIG
(
PWR_REGULATOR_VOLTAGE_SCALE1
);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
|
RCC_OSCILLATORTYPE_LSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
LSEState
=
RCC_LSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
25
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
432
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Activate the Over-Drive mode
*/
if
(
HAL_PWREx_EnableOverDrive
()
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV4
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV2
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_7
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_RTC
|
RCC_PERIPHCLK_USART1
;
PeriphClkInitStruct
.
RTCClockSelection
=
RCC_RTCCLKSOURCE_LSE
;
PeriphClkInitStruct
.
Usart1ClockSelection
=
RCC_USART1CLKSOURCE_PCLK2
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
bsp/stm32/stm32f767-atk-apollo/board/board.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-5 SummerGift change to new framework
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <stm32f7xx.h>
#include "drv_common.h"
#define STM32_SRAM_SIZE (512)
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern
int
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern
int
__bss_end
;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END STM32_SRAM_END
void
SystemClock_Config
(
void
);
#endif
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x0000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.lds
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/*
* linker script for STM32F4xx with GNU ld
* bernard.xiong 2009-10-14
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
_etext = .;
} > ROM = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > ROM
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >RAM
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > RAM
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/stm32/stm32f767-atk-apollo/board/linker_scripts/link.sct
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20020000 0x00060000 { ; RW data
.ANY (+RW +ZI)
}
}
bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-27 zylx change to new framework
*/
#include <board.h>
#include <drv_qspi.h>
#include <rtdevice.h>
#include <rthw.h>
#include <finsh.h>
#ifdef BSP_USING_QSPI_FLASH
#include "spi_flash.h"
#include "spi_flash_sfud.h"
char
w25qxx_read_status_register2
(
struct
rt_qspi_device
*
device
)
{
/* 0x35 read status register2 */
char
instruction
=
0x35
,
status
;
rt_qspi_send_then_recv
(
device
,
&
instruction
,
1
,
&
status
,
1
);
return
status
;
}
void
w25qxx_write_enable
(
struct
rt_qspi_device
*
device
)
{
/* 0x06 write enable */
char
instruction
=
0x06
;
rt_qspi_send
(
device
,
&
instruction
,
1
);
}
void
w25qxx_enter_qspi_mode
(
struct
rt_qspi_device
*
device
)
{
char
status
=
0
;
/* 0x38 enter qspi mode */
char
instruction
=
0x38
;
char
write_status2_buf
[
2
]
=
{
0
};
/* 0x31 write status register2 */
write_status2_buf
[
0
]
=
0x31
;
status
=
w25qxx_read_status_register2
(
device
);
if
(
!
(
status
&
0x02
))
{
status
|=
1
<<
1
;
w25qxx_write_enable
(
device
);
write_status2_buf
[
1
]
=
status
;
rt_qspi_send
(
device
,
&
write_status2_buf
,
2
);
rt_qspi_send
(
device
,
&
instruction
,
1
);
rt_kprintf
(
"flash already enter qspi mode
\n
"
);
rt_thread_mdelay
(
10
);
}
}
static
int
rt_hw_qspi_flash_with_sfud_init
(
void
)
{
stm32_qspi_bus_attach_device
(
"qspi1"
,
"qspi10"
,
RT_NULL
,
4
,
w25qxx_enter_qspi_mode
,
RT_NULL
);
/* init w25q128 */
if
(
RT_NULL
==
rt_sfud_flash_probe
(
"w25q128"
,
"qspi10"
))
{
return
-
RT_ERROR
;
}
return
RT_EOK
;
}
INIT_COMPONENT_EXPORT
(
rt_hw_qspi_flash_with_sfud_init
);
#endif
/* BSP_USING_QSPI_FLASH */
bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern
const
struct
fal_flash_dev
stm32_onchip_flash
;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 1008 * 1024, 0},\
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 1008* 1024 , 16 * 1024, 0},\
}
#endif
/* FAL_PART_HAS_TABLE_CFG */
#endif
/* _FAL_CFG_H_ */
bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-21 SummerGift add port file
*/
#include <rtthread.h>
#include "pcf8574.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.pcf8574_port"
#include <drv_log.h>
#define ETH_RESET_IO 7 //PHY RESET PIN
#define I2C_BUS_NAME "i2c2"
#define PCF8574_ADDR 0x20
/* pcf8574 hardware init */
pcf8574_device_t
pcf8574_hw_init
(
char
*
dev_name
,
int
addr
)
{
static
pcf8574_device_t
dev
;
if
(
dev
==
RT_NULL
)
{
dev
=
pcf8574_init
(
dev_name
,
addr
);
if
(
dev
==
RT_NULL
)
{
LOG_E
(
"i2c_bus %s for PCF8574 not found!"
,
dev_name
);
return
RT_NULL
;
}
else
{
return
dev
;
}
}
else
{
return
dev
;
}
}
/* phy reset */
void
phy_reset
(
void
)
{
pcf8574_device_t
dev
=
pcf8574_hw_init
(
I2C_BUS_NAME
,
PCF8574_ADDR
);
if
(
dev
==
RT_NULL
)
{
LOG_E
(
"can't get pcf8574 device"
);
return
;
}
pcf8574_pin_write
(
dev
,
ETH_RESET_IO
,
1
);
rt_thread_mdelay
(
100
);
pcf8574_pin_write
(
dev
,
ETH_RESET_IO
,
0
);
rt_thread_mdelay
(
100
);
}
bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-13 balanceTWK add sdcard port file
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#include <dfs_elm.h>
#include <dfs_fs.h>
#include <dfs_posix.h>
#define DBG_ENABLE
#define DBG_SECTION_NAME "app.card"
#define DBG_COLOR
#define DBG_LEVEL DBG_INFO
#include <rtdbg.h>
void
sd_mount
(
void
*
parameter
)
{
while
(
1
)
{
rt_thread_mdelay
(
500
);
if
(
rt_device_find
(
"sd0"
)
!=
RT_NULL
)
{
if
(
dfs_mount
(
"sd0"
,
"/"
,
"elm"
,
0
,
0
)
==
RT_EOK
)
{
LOG_I
(
"sd card mount to '/'"
);
break
;
}
else
{
LOG_W
(
"sd card mount to '/' failed!"
);
}
}
}
}
int
stm32_sdcard_mount
(
void
)
{
rt_thread_t
tid
;
tid
=
rt_thread_create
(
"sd_mount"
,
sd_mount
,
RT_NULL
,
1024
,
RT_THREAD_PRIORITY_MAX
-
2
,
20
);
if
(
tid
!=
RT_NULL
)
{
rt_thread_startup
(
tid
);
}
else
{
LOG_E
(
"create sd_mount thread err!"
);
}
return
RT_EOK
;
}
INIT_APP_EXPORT
(
stm32_sdcard_mount
);
#endif
/* BSP_USING_SDCARD */
bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 16
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 9
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 13
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 3
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 1
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_COUNT ((uint32_t)0x02AB)
#define SDRAM_SIZE ((uint32_t)0x2000000)
/* Timing configuration for W9825G6KH-6 */
/* 90 MHz of SD clock frequency (180MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 7x11.90ns */
#define EXITSELFREFRESHDELAY 8
/* TRAS: 4x11.90ns */
#define SELFREFRESHTIME 6
/* TRC: 7x11.90ns */
#define ROWCYCLEDELAY 6
/* TWR: 2 Clock cycles */
#define WRITERECOVERYTIME 2
/* TRP: 2x11.90ns */
#define RPDELAY 2
/* TRCD: 2x11.90ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif
bsp/stm32/stm32f767-atk-apollo/figures/board.jpg
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bsp/stm32/stm32f767-atk-apollo/project.ewp
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>
$WS_DIR$\project.ewp
</path>
</project>
<batchBuild/>
</workspace>
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bsp/stm32/stm32f767-atk-apollo/rtconfig.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40000
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M7
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_USING_PIN
/* Using WiFi */
/* Using USB */
/* POSIX layer and C standard library */
/* Network */
/* Socket abstraction layer */
/* light weight TCP/IP stack */
/* Modbus master and slave stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* ARM CMSIS */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F7
/* Hardware Drivers Config */
#define SOC_STM32F767IG
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART1
/* Board extended module Drivers */
#endif
bsp/stm32/stm32f767-atk-apollo/rtconfig.py
0 → 100644
浏览文件 @
864ae989
import
os
# toolchains options
ARCH
=
'arm'
CPU
=
'cortex-m7'
CROSS_TOOL
=
'gcc'
# bsp lib config
BSP_LIBRARY_TYPE
=
None
if
os
.
getenv
(
'RTT_CC'
):
CROSS_TOOL
=
os
.
getenv
(
'RTT_CC'
)
if
os
.
getenv
(
'RTT_ROOT'
):
RTT_ROOT
=
os
.
getenv
(
'RTT_ROOT'
)
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if
CROSS_TOOL
==
'gcc'
:
PLATFORM
=
'gcc'
EXEC_PATH
=
r
'C:\Users\XXYYZZ'
elif
CROSS_TOOL
==
'keil'
:
PLATFORM
=
'armcc'
EXEC_PATH
=
r
'C:/Keil_v5'
elif
CROSS_TOOL
==
'iar'
:
PLATFORM
=
'iar'
EXEC_PATH
=
r
'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if
os
.
getenv
(
'RTT_EXEC_PATH'
):
EXEC_PATH
=
os
.
getenv
(
'RTT_EXEC_PATH'
)
BUILD
=
'debug'
if
PLATFORM
==
'gcc'
:
# toolchains
PREFIX
=
'arm-none-eabi-'
CC
=
PREFIX
+
'gcc'
AS
=
PREFIX
+
'gcc'
AR
=
PREFIX
+
'ar'
LINK
=
PREFIX
+
'gcc'
TARGET_EXT
=
'elf'
SIZE
=
PREFIX
+
'size'
OBJDUMP
=
PREFIX
+
'objdump'
OBJCPY
=
PREFIX
+
'objcopy'
DEVICE
=
' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS
=
DEVICE
+
' -std=c99 -Dgcc'
AFLAGS
=
' -c'
+
DEVICE
+
' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS
=
DEVICE
+
' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH
=
''
LPATH
=
''
if
BUILD
==
'debug'
:
CFLAGS
+=
' -O0 -gdwarf-2 -g'
AFLAGS
+=
' -gdwarf-2'
else
:
CFLAGS
+=
' -O2'
POST_ACTION
=
OBJCPY
+
' -O binary $TARGET rtthread.bin
\n
'
+
SIZE
+
' $TARGET
\n
'
elif
PLATFORM
==
'armcc'
:
# toolchains
CC
=
'armcc'
AS
=
'armasm'
AR
=
'armar'
LINK
=
'armlink'
TARGET_EXT
=
'axf'
DEVICE
=
' --cpu Cortex-M7.fp.sp'
CFLAGS
=
'-c '
+
DEVICE
+
' --apcs=interwork --c99'
AFLAGS
=
DEVICE
+
' --apcs=interwork '
LFLAGS
=
DEVICE
+
' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS
+=
' -I'
+
EXEC_PATH
+
'/ARM/ARMCC/include'
LFLAGS
+=
' --libpath='
+
EXEC_PATH
+
'/ARM/ARMCC/lib'
CFLAGS
+=
' -D__MICROLIB '
AFLAGS
+=
' --pd "__MICROLIB SETA 1" '
LFLAGS
+=
' --library_type=microlib '
EXEC_PATH
+=
'/ARM/ARMCC/bin/'
if
BUILD
==
'debug'
:
CFLAGS
+=
' -g -O0'
AFLAGS
+=
' -g'
else
:
CFLAGS
+=
' -O2'
CXXFLAGS
=
CFLAGS
POST_ACTION
=
'fromelf --bin $TARGET --output rtthread.bin
\n
fromelf -z $TARGET'
elif
PLATFORM
==
'iar'
:
# toolchains
CC
=
'iccarm'
AS
=
'iasmarm'
AR
=
'iarchive'
LINK
=
'ilinkarm'
TARGET_EXT
=
'out'
DEVICE
=
'-Dewarm'
CFLAGS
=
DEVICE
CFLAGS
+=
' --diag_suppress Pa050'
CFLAGS
+=
' --no_cse'
CFLAGS
+=
' --no_unroll'
CFLAGS
+=
' --no_inline'
CFLAGS
+=
' --no_code_motion'
CFLAGS
+=
' --no_tbaa'
CFLAGS
+=
' --no_clustering'
CFLAGS
+=
' --no_scheduling'
CFLAGS
+=
' --endian=little'
CFLAGS
+=
' --cpu=Cortex-M7'
CFLAGS
+=
' -e'
CFLAGS
+=
' --fpu=VFPv5_sp'
CFLAGS
+=
' --dlib_config "'
+
EXEC_PATH
+
'/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS
+=
' --silent'
AFLAGS
=
DEVICE
AFLAGS
+=
' -s+'
AFLAGS
+=
' -w+'
AFLAGS
+=
' -r'
AFLAGS
+=
' --cpu Cortex-M7'
AFLAGS
+=
' --fpu VFPv5_sp'
AFLAGS
+=
' -S'
if
BUILD
==
'debug'
:
CFLAGS
+=
' --debug'
CFLAGS
+=
' -On'
else
:
CFLAGS
+=
' -Oh'
LFLAGS
=
' --config "board/linker_scripts/link.icf"'
LFLAGS
+=
' --entry __iar_program_start'
EXEC_PATH
=
EXEC_PATH
+
'/arm/bin/'
POST_ACTION
=
'ielftool --bin $TARGET rtthread.bin'
\ No newline at end of file
bsp/stm32/stm32f767-atk-apollo/template.ewp
0 → 100644
浏览文件 @
864ae989
此差异已折叠。
点击以展开。
bsp/stm32/stm32f767-atk-apollo/template.eww
0 → 100644
浏览文件 @
864ae989
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>
$WS_DIR$\template.ewp
</path>
</project>
<batchBuild/>
</workspace>
bsp/stm32/stm32f767-atk-apollo/template.uvoptx
0 → 100644
浏览文件 @
864ae989
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt
xmlns:xsi=
"http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation=
"project_optx.xsd"
>
<SchemaVersion>
1.0
</SchemaVersion>
<Header>
### uVision Project, (C) Keil Software
</Header>
<Extensions>
<cExt>
*.c
</cExt>
<aExt>
*.s*; *.src; *.a*
</aExt>
<oExt>
*.obj; *.o
</oExt>
<lExt>
*.lib
</lExt>
<tExt>
*.txt; *.h; *.inc
</tExt>
<pExt>
*.plm
</pExt>
<CppX>
*.cpp
</CppX>
<nMigrate>
0
</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>
0
</dwLowDateTime>
<dwHighDateTime>
0
</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>
rt-thread
</TargetName>
<ToolsetNumber>
0x4
</ToolsetNumber>
<ToolsetName>
ARM-ADS
</ToolsetName>
<TargetOption>
<CLKADS>
12000000
</CLKADS>
<OPTTT>
<gFlags>
1
</gFlags>
<BeepAtEnd>
1
</BeepAtEnd>
<RunSim>
0
</RunSim>
<RunTarget>
1
</RunTarget>
<RunAbUc>
0
</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>
1
</HexSelection>
<FlashByte>
65535
</FlashByte>
<HexRangeLowAddress>
0
</HexRangeLowAddress>
<HexRangeHighAddress>
0
</HexRangeHighAddress>
<HexOffset>
0
</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>
79
</PageWidth>
<PageLength>
66
</PageLength>
<TabStop>
8
</TabStop>
<ListingPath>
.\build\keil\List\
</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>
1
</CreateCListing>
<CreateAListing>
1
</CreateAListing>
<CreateLListing>
1
</CreateLListing>
<CreateIListing>
0
</CreateIListing>
<AsmCond>
1
</AsmCond>
<AsmSymb>
1
</AsmSymb>
<AsmXref>
0
</AsmXref>
<CCond>
1
</CCond>
<CCode>
0
</CCode>
<CListInc>
0
</CListInc>
<CSymb>
0
</CSymb>
<LinkerCodeListing>
0
</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>
1
</LMap>
<LComments>
1
</LComments>
<LGenerateSymbols>
1
</LGenerateSymbols>
<LLibSym>
1
</LLibSym>
<LLines>
1
</LLines>
<LLocSym>
1
</LLocSym>
<LPubSym>
1
</LPubSym>
<LXref>
0
</LXref>
<LExpSel>
0
</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>
1
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<IsCurrentTarget>
1
</IsCurrentTarget>
</OPTFL>
<CpuCode>
18
</CpuCode>
<DebugOpt>
<uSim>
0
</uSim>
<uTrg>
1
</uTrg>
<sLdApp>
1
</sLdApp>
<sGomain>
1
</sGomain>
<sRbreak>
1
</sRbreak>
<sRwatch>
1
</sRwatch>
<sRmem>
1
</sRmem>
<sRfunc>
1
</sRfunc>
<sRbox>
1
</sRbox>
<tLdApp>
1
</tLdApp>
<tGomain>
1
</tGomain>
<tRbreak>
1
</tRbreak>
<tRwatch>
1
</tRwatch>
<tRmem>
1
</tRmem>
<tRfunc>
0
</tRfunc>
<tRbox>
1
</tRbox>
<tRtrace>
1
</tRtrace>
<sRSysVw>
1
</sRSysVw>
<tRSysVw>
1
</tRSysVw>
<sRunDeb>
0
</sRunDeb>
<sLrtime>
0
</sLrtime>
<bEvRecOn>
1
</bEvRecOn>
<bSchkAxf>
0
</bSchkAxf>
<bTchkAxf>
0
</bTchkAxf>
<nTsel>
4
</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>
Segger\JL2CM3.dll
</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
JL2CM3
</Key>
<Name>
-U59400616 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(5BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06451041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
UL2CM3
</Key>
<Name>
UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20020000 -FF0STM32F7x_1024 -FF1STM32F7x_1024dual -FL0100000 -FL1100000 -FS08000000 -FS18000000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM)
</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>
0
</THDelay>
</Tracepoint>
<DebugFlag>
<trace>
0
</trace>
<periodic>
0
</periodic>
<aLwin>
0
</aLwin>
<aCover>
0
</aCover>
<aSer1>
0
</aSer1>
<aSer2>
0
</aSer2>
<aPa>
0
</aPa>
<viewmode>
0
</viewmode>
<vrSel>
0
</vrSel>
<aSym>
0
</aSym>
<aTbox>
0
</aTbox>
<AscS1>
0
</AscS1>
<AscS2>
0
</AscS2>
<AscS3>
0
</AscS3>
<aSer3>
0
</aSer3>
<eProf>
0
</eProf>
<aLa>
0
</aLa>
<aPa1>
0
</aPa1>
<AscS4>
0
</AscS4>
<aSer4>
0
</aSer4>
<StkLoc>
0
</StkLoc>
<TrcWin>
0
</TrcWin>
<newCpu>
0
</newCpu>
<uProt>
0
</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>
0
</bLintAuto>
<bAutoGenD>
0
</bAutoGenD>
<LntExFlags>
0
</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>
1
</Enable>
<EnableLog>
0
</EnableLog>
<Protocol>
2
</Protocol>
<DbgClock>
10000000
</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>
Source Group 1
</GroupName>
<tvExp>
0
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<cbSel>
0
</cbSel>
<RteFlg>
0
</RteFlg>
</Group>
</ProjectOpt>
bsp/stm32/stm32f767-atk-apollo/template.uvprojx
0 → 100644
浏览文件 @
864ae989
此差异已折叠。
点击以展开。
bsp/stm32f40x/project.uvprojx
浏览文件 @
864ae989
此差异已折叠。
点击以展开。
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