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2488624a
编写于
11月 21, 2017
作者:
S
SummerGift
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct.
上级
334da974
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
100 addition
and
100 deletion
+100
-100
libcpu/arm/am335x/mmu.c
libcpu/arm/am335x/mmu.c
+25
-25
libcpu/arm/armv6/mmu.c
libcpu/arm/armv6/mmu.c
+27
-27
libcpu/arm/dm36x/mmu.c
libcpu/arm/dm36x/mmu.c
+27
-27
libcpu/arm/s3c24x0/mmu.c
libcpu/arm/s3c24x0/mmu.c
+21
-21
未找到文件。
libcpu/arm/am335x/mmu.c
浏览文件 @
2488624a
...
...
@@ -255,16 +255,16 @@ void mmu_setttbase(register rt_uint32_t i)
* set by page table entry
*/
value
=
0
;
asm
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0x55555555
;
asm
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable
()
...
...
@@ -272,12 +272,12 @@ void mmu_enable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable
()
...
...
@@ -285,12 +285,12 @@ void mmu_disable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_icache
()
...
...
@@ -298,12 +298,12 @@ void mmu_enable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_dcache
()
...
...
@@ -311,12 +311,12 @@ void mmu_enable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_icache
()
...
...
@@ -324,12 +324,12 @@ void mmu_disable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_dcache
()
...
...
@@ -337,12 +337,12 @@ void mmu_disable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
...
...
@@ -350,12 +350,12 @@ void mmu_enable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
...
...
@@ -363,17 +363,17 @@ void mmu_disable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_clean_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
...
...
@@ -384,7 +384,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
32
;
}
}
...
...
@@ -397,19 +397,19 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
32
;
}
}
void
mmu_invalidate_tlb
()
{
asm
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
#endif
...
...
libcpu/arm/armv6/mmu.c
浏览文件 @
2488624a
...
...
@@ -253,16 +253,16 @@ void mmu_setttbase(register rt_uint32_t i)
* set by page table entry
*/
value
=
0
;
asm
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0x55555555
;
asm
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable
()
...
...
@@ -270,7 +270,7 @@ void mmu_enable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
0x1
;
/* Enables the extended page tables to be configured for
...
...
@@ -279,7 +279,7 @@ void mmu_enable()
i
|=
(
1
<<
13
);
/* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable
()
...
...
@@ -287,12 +287,12 @@ void mmu_disable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_icache
()
...
...
@@ -300,12 +300,12 @@ void mmu_enable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_dcache
()
...
...
@@ -313,12 +313,12 @@ void mmu_enable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_icache
()
...
...
@@ -326,12 +326,12 @@ void mmu_disable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_dcache
()
...
...
@@ -339,12 +339,12 @@ void mmu_disable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
...
...
@@ -352,12 +352,12 @@ void mmu_enable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
...
...
@@ -365,17 +365,17 @@ void mmu_disable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_clean_invalidated_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
...
...
@@ -386,7 +386,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -400,7 +400,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -413,24 +413,24 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
void
mmu_invalidate_tlb
()
{
asm
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_dcache_all
()
{
asm
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
}
#endif
...
...
libcpu/arm/dm36x/mmu.c
浏览文件 @
2488624a
...
...
@@ -253,16 +253,16 @@ void mmu_setttbase(register rt_uint32_t i)
* set by page table entry
*/
value
=
0
;
asm
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
::
"r"
(
value
));
value
=
0x55555555
;
asm
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c3, c0, 0"
::
"r"
(
value
));
asm
volatile
(
"mcr p15, 0, %0, c2, c0, 0"
::
"r"
(
i
));
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable
()
...
...
@@ -270,7 +270,7 @@ void mmu_enable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
0x1
;
i
|=
(
1
<<
13
);
/* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
...
...
@@ -279,7 +279,7 @@ void mmu_enable()
i
&=
~
(
1
<<
9
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable
()
...
...
@@ -287,12 +287,12 @@ void mmu_disable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_icache
()
...
...
@@ -300,12 +300,12 @@ void mmu_enable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_dcache
()
...
...
@@ -313,12 +313,12 @@ void mmu_enable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_icache
()
...
...
@@ -326,12 +326,12 @@ void mmu_disable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_dcache
()
...
...
@@ -339,12 +339,12 @@ void mmu_disable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
...
...
@@ -352,12 +352,12 @@ void mmu_enable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
...
...
@@ -365,17 +365,17 @@ void mmu_disable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_clean_invalidated_dcache
(
rt_uint32_t
buffer
,
rt_uint32_t
size
)
...
...
@@ -386,7 +386,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -400,7 +400,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c10, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
...
...
@@ -413,24 +413,24 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
while
(
ptr
<
buffer
+
size
)
{
asm
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 1"
:
:
"r"
(
ptr
));
ptr
+=
CACHE_LINE_SIZE
;
}
}
void
mmu_invalidate_tlb
()
{
asm
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_dcache_all
()
{
asm
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c6, 0"
:
:
"r"
(
0
));
}
#endif
...
...
libcpu/arm/s3c24x0/mmu.c
浏览文件 @
2488624a
...
...
@@ -43,12 +43,12 @@
#ifdef __GNUC__
void
mmu_setttbase
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15, 0, %0, c2, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c2, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_set_domain
(
register
rt_uint32_t
i
)
{
asm
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15,0, %0, c3, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable
()
...
...
@@ -56,12 +56,12 @@ void mmu_enable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable
()
...
...
@@ -69,12 +69,12 @@ void mmu_disable()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
0x1
;
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_icache
()
...
...
@@ -82,12 +82,12 @@ void mmu_enable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_dcache
()
...
...
@@ -95,12 +95,12 @@ void mmu_enable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_icache
()
...
...
@@ -108,12 +108,12 @@ void mmu_disable_icache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
12
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_dcache
()
...
...
@@ -121,12 +121,12 @@ void mmu_disable_dcache()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
2
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_enable_alignfault
()
...
...
@@ -134,12 +134,12 @@ void mmu_enable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
|=
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_disable_alignfault
()
...
...
@@ -147,27 +147,27 @@ void mmu_disable_alignfault()
register
rt_uint32_t
i
;
/* read control register */
asm
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
asm
volatile
(
"mrc p15, 0, %0, c1, c0, 0"
:
"=r"
(
i
));
i
&=
~
(
1
<<
1
);
/* write back to control register */
asm
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
asm
volatile
(
"mcr p15, 0, %0, c1, c0, 0"
:
:
"r"
(
i
));
}
void
mmu_clean_invalidated_cache_index
(
int
index
)
{
asm
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
asm
volatile
(
"mcr p15, 0, %0, c7, c14, 2"
:
:
"r"
(
index
));
}
void
mmu_invalidate_tlb
()
{
asm
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c8, c7, 0"
:
:
"r"
(
0
));
}
void
mmu_invalidate_icache
()
{
asm
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
asm
volatile
(
"mcr p15, 0, %0, c7, c5, 0"
:
:
"r"
(
0
));
}
#endif
...
...
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